Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(92)

Side by Side Diff: src/mips/assembler-mips.cc

Issue 2535703002: MIPS: Optimize load/store with large offset on MIPSr6 (Closed)
Patch Set: Created 4 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « no previous file | src/mips64/assembler-mips64.cc » ('j') | src/mips64/assembler-mips64.cc » ('J')
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 1762 matching lines...) Expand 10 before | Expand all | Expand 10 after
1773 emit(instr); 1773 emit(instr);
1774 } 1774 }
1775 1775
1776 1776
1777 // ------------Memory-instructions------------- 1777 // ------------Memory-instructions-------------
1778 1778
1779 // Helper for base-reg + offset, when offset is larger than int16. 1779 // Helper for base-reg + offset, when offset is larger than int16.
1780 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { 1780 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
1781 DCHECK(!src.rm().is(at)); 1781 DCHECK(!src.rm().is(at));
1782 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask); 1782 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1783 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. 1783 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
ivica.bogosavljevic 2016/11/28 13:13:46 It is possible to optimize this sequence of code a
Marija Antic 2016/11/28 13:36:12 Done.
1784 addu(at, at, src.rm()); // Add base register. 1784 addu(at, at, src.rm()); // Add base register.
1785 } 1785 }
1786 1786
1787 // Helper for base-reg + upper part of offset, when offset is larger than int16. 1787 // Helper for base-reg + upper part of offset, when offset is larger than int16.
1788 // Loads higher part of the offset to AT register. 1788 // Loads higher part of the offset to AT register.
1789 // Returns lower part of the offset to be used as offset 1789 // Returns lower part of the offset to be used as offset
1790 // in Load/Store instructions 1790 // in Load/Store instructions
1791 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) { 1791 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) {
1792 DCHECK(!src.rm().is(at)); 1792 DCHECK(!src.rm().is(at));
1793 int32_t hi = (src.offset_ >> kLuiShift) & kImm16Mask; 1793 int32_t hi = (src.offset_ >> kLuiShift) & kImm16Mask;
1794 // If the highest bit of the lower part of the offset is 1, this would make 1794 // If the highest bit of the lower part of the offset is 1, this would make
1795 // the offset in the load/store instruction negative. We need to compensate 1795 // the offset in the load/store instruction negative. We need to compensate
1796 // for this by adding 1 to the upper part of the offset. 1796 // for this by adding 1 to the upper part of the offset.
1797 if (src.offset_ & kNegOffset) { 1797 if (src.offset_ & kNegOffset) {
1798 hi += 1; 1798 hi += 1;
1799 } 1799 }
1800 lui(at, hi); 1800
1801 addu(at, at, src.rm()); 1801 if (IsMipsArchVariant(kMips32r6)) {
1802 aui(at, src.rm(), hi);
1803 } else {
1804 lui(at, hi);
1805 addu(at, at, src.rm());
1806 }
1802 return (src.offset_ & kImm16Mask); 1807 return (src.offset_ & kImm16Mask);
1803 } 1808 }
1804 1809
1805 // Helper for loading base-reg + upper offset's part to AT reg when we are using 1810 // Helper for loading base-reg + upper offset's part to AT reg when we are using
1806 // two 32-bit loads/stores instead of one 64-bit 1811 // two 32-bit loads/stores instead of one 64-bit
1807 int32_t Assembler::LoadUpperOffsetForTwoMemoryAccesses(const MemOperand& src) { 1812 int32_t Assembler::LoadUpperOffsetForTwoMemoryAccesses(const MemOperand& src) {
1808 DCHECK(!src.rm().is(at)); 1813 DCHECK(!src.rm().is(at));
1809 if (is_int16((src.offset_ & kImm16Mask) + kIntSize)) { 1814 if (is_int16((src.offset_ & kImm16Mask) + kIntSize)) {
1810 // Only if lower part of offset + kIntSize fits in 16bits 1815 // Only if lower part of offset + kIntSize fits in 16bits
1811 return LoadRegPlusUpperOffsetPartToAt(src); 1816 return LoadRegPlusUpperOffsetPartToAt(src);
(...skipping 1447 matching lines...) Expand 10 before | Expand all | Expand 10 after
3259 3264
3260 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 3265 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3261 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); 3266 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t));
3262 } 3267 }
3263 } 3268 }
3264 3269
3265 } // namespace internal 3270 } // namespace internal
3266 } // namespace v8 3271 } // namespace v8
3267 3272
3268 #endif // V8_TARGET_ARCH_MIPS 3273 #endif // V8_TARGET_ARCH_MIPS
OLDNEW
« no previous file with comments | « no previous file | src/mips64/assembler-mips64.cc » ('j') | src/mips64/assembler-mips64.cc » ('J')

Powered by Google App Engine
This is Rietveld 408576698