MIPS: Optimize load/store with large offset on MIPSr6

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1762 matching lines @@
   emit(instr);
 }
 
 
 // ------------Memory-instructions-------------
 
 // Helper for base-reg + offset, when offset is larger than int16.
 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
   DCHECK(!src.rm().is(at));
   lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
   ori(at, at, src.offset_ & kImm16Mask);  // Load 32-bit offset.

[ivica.bogosavljevic, 2016/11/28 13:13:46]

It is possible to optimize this sequence of code as well.

instead of 
LUI at, upper(src.offset)
ORI at, lower(src.offset)
ADDU at, at, src.rm

we could write

AUI at, src.rm, upper(src.offset)
ADDIU at, at, lower(src.offset)

[Marija Antic, 2016/11/28 13:36:12]

Done.

   addu(at, at, src.rm());  // Add base register.
 }
 
 // Helper for base-reg + upper part of offset, when offset is larger than int16.
 // Loads higher part of the offset to AT register.
 // Returns lower part of the offset to be used as offset
 // in Load/Store instructions
 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) {
   DCHECK(!src.rm().is(at));
   int32_t hi = (src.offset_ >> kLuiShift) & kImm16Mask;
   // If the highest bit of the lower part of the offset is 1, this would make
   // the offset in the load/store instruction negative. We need to compensate
   // for this by adding 1 to the upper part of the offset.
   if (src.offset_ & kNegOffset) {
     hi += 1;
   }
-  lui(at, hi);
-  addu(at, at, src.rm());
+
+  if (IsMipsArchVariant(kMips32r6)) {
+    aui(at, src.rm(), hi);
+  } else {
+    lui(at, hi);
+    addu(at, at, src.rm());
+  }
   return (src.offset_ & kImm16Mask);
 }
 
 // Helper for loading base-reg + upper offset's part to AT reg when we are using
 // two 32-bit loads/stores instead of one 64-bit
 int32_t Assembler::LoadUpperOffsetForTwoMemoryAccesses(const MemOperand& src) {
   DCHECK(!src.rm().is(at));
   if (is_int16((src.offset_ & kImm16Mask) + kIntSize)) {
     // Only if lower part of offset + kIntSize fits in 16bits
     return LoadRegPlusUpperOffsetPartToAt(src);
@@ skipping 1447 matching lines @@
 
   if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
     Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t));
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS