[Turbofan] Add ARM support for simd128 moves and swaps.

test/cctest/test-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1237 matching lines @@
     uint32_t srcA0;
     uint32_t srcA1;
     uint32_t dstA0;
     uint32_t dstA1;
     uint32_t dstA2;
     uint32_t dstA3;
     uint32_t dstA4;
     uint32_t dstA5;
     uint32_t dstA6;
     uint32_t dstA7;
+    uint32_t vmov_src[4], vmov_dst[4];
+    uint32_t veor_src[4], veor_dst[4];
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles and floats.
   Assembler assm(isolate, NULL, 0);
 
 
   if (CpuFeatures::IsSupported(NEON)) {
     CpuFeatureScope scope(&assm, NEON);
@@ skipping 12 matching lines @@
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, dstA0))));
     __ vst1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
 
     // The same expansion, but with different source and destination registers.
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, srcA0))));
     __ vld1(Neon8, NeonListOperand(d1), NeonMemOperand(r4));
     __ vmovl(NeonU8, q1, d1);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, dstA4))));
     __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
 
+    // Test vmov for q-registers.
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmov_src))));
+    __ vld1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
+    __ vmov(q1, q0);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmov_dst))));
+    __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+
+    // Test veor for q-registers.
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, veor_src))));
+    __ vld1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, veor_dst))));
+    __ vld1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+    __ veor(q1, q1, q0);
+    __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+
+    // Restore and return.
     __ ldm(ia_w, sp, r4.bit() | pc.bit());
 
     CodeDesc desc;
     assm.GetCode(&desc);
     Handle<Code> code = isolate->factory()->NewCode(
         desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
 #ifdef DEBUG
     OFStream os(stdout);
     code->Print(os);
 #endif
@@ skipping 17 matching lines @@
     t.srcA0 = 0x41424344;
     t.srcA1 = 0x81828384;
     t.dstA0 = 0;
     t.dstA1 = 0;
     t.dstA2 = 0;
     t.dstA3 = 0;
     t.dstA4 = 0;
     t.dstA5 = 0;
     t.dstA6 = 0;
     t.dstA7 = 0;
+    t.vmov_src[0] = t.vmov_src[1] = t.vmov_src[2] = t.vmov_src[3] = 1;
+    t.vmov_dst[0] = t.vmov_dst[1] = t.vmov_dst[2] = t.vmov_dst[3] = 0;
+    t.veor_src[0] = t.veor_src[1] = t.veor_src[2] = t.veor_src[3] = 0xAA;
+    t.veor_dst[0] = t.veor_dst[1] = t.veor_dst[2] = t.veor_dst[3] = 0x55;
     Object* dummy = CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0);
     USE(dummy);
     CHECK_EQ(0x01020304u, t.dst0);
     CHECK_EQ(0x11121314u, t.dst1);
     CHECK_EQ(0x21222324u, t.dst2);
     CHECK_EQ(0x31323334u, t.dst3);
     CHECK_EQ(0x41424344u, t.dst4);
     CHECK_EQ(0x51525354u, t.dst5);
     CHECK_EQ(0x61626364u, t.dst6);
     CHECK_EQ(0x71727374u, t.dst7);
     CHECK_EQ(0x00430044u, t.dstA0);
     CHECK_EQ(0x00410042u, t.dstA1);
     CHECK_EQ(0x00830084u, t.dstA2);
     CHECK_EQ(0x00810082u, t.dstA3);
     CHECK_EQ(0x00430044u, t.dstA4);
     CHECK_EQ(0x00410042u, t.dstA5);
     CHECK_EQ(0x00830084u, t.dstA6);
     CHECK_EQ(0x00810082u, t.dstA7);
+    CHECK_EQ(1u, t.vmov_dst[0]);
+    CHECK_EQ(1u, t.vmov_dst[1]);
+    CHECK_EQ(1u, t.vmov_dst[2]);
+    CHECK_EQ(1u, t.vmov_dst[3]);
+    CHECK_EQ(0xFFu, t.veor_dst[0]);
+    CHECK_EQ(0xFFu, t.veor_dst[1]);
+    CHECK_EQ(0xFFu, t.veor_dst[2]);
+    CHECK_EQ(0xFFu, t.veor_dst[3]);
   }
 }
 
 
 TEST(16) {
   // Test the pkh, uxtb, uxtab and uxtb16 instructions.
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
 
@@ skipping 1519 matching lines @@
   {
     uint64_t strh = 0;
     uint64_t str = 0;
     dummy = CALL_GENERATED_CODE(isolate, f, &strh, &str, 3, 0xfedcba98, 0);
     CHECK_EQ(UINT64_C(0x000000ba98000000), strh);
     CHECK_EQ(UINT64_C(0x00fedcba98000000), str);
   }
 }
 
 TEST(vswp) {
+  if (!CpuFeatures::IsSupported(NEON)) return;
+
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
   Assembler assm(isolate, NULL, 0);
 
   typedef struct {
     double result0;
     double result1;
     double result2;
     double result3;
+    double result4;
+    double result5;
+    double result6;
+    double result7;
   } T;
   T t;
 
   __ vmov(d0, 1.0);
   __ vmov(d1, -1.0);
   __ vswp(d0, d1);
   __ vstr(d0, r0, offsetof(T, result0));
   __ vstr(d1, r0, offsetof(T, result1));
 
   if (CpuFeatures::IsSupported(VFP32DREGS)) {
     __ vmov(d30, 1.0);
     __ vmov(d31, -1.0);
     __ vswp(d30, d31);
     __ vstr(d30, r0, offsetof(T, result2));
     __ vstr(d31, r0, offsetof(T, result3));
   }
 
+  // q-register swap.
+  __ vmov(d8, 1.0);
+  __ vmov(d9, 2.0);
+  __ vmov(d10, 3.0);
+  __ vmov(d11, 4.0);
+  __ vswp(q4, q5);
+  __ vstr(d8, r0, offsetof(T, result4));
+  __ vstr(d9, r0, offsetof(T, result5));
+  __ vstr(d10, r0, offsetof(T, result6));
+  __ vstr(d11, r0, offsetof(T, result7));
+
   __ bx(lr);
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
 #ifdef DEBUG
   OFStream os(stdout);
   code->Print(os);
 #endif
   F3 f = FUNCTION_CAST<F3>(code->entry());
   Object* dummy = CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0);
   USE(dummy);
   CHECK_EQ(-1.0, t.result0);
   CHECK_EQ(1.0, t.result1);
   if (CpuFeatures::IsSupported(VFP32DREGS)) {
     CHECK_EQ(-1.0, t.result2);
     CHECK_EQ(1.0, t.result3);
   }
+  CHECK_EQ(3.0, t.result4);
+  CHECK_EQ(4.0, t.result5);
+  CHECK_EQ(1.0, t.result6);
+  CHECK_EQ(2.0, t.result7);
 }
 
 TEST(regress4292_b) {
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
 
   Assembler assm(isolate, NULL, 0);
   Label end;
   __ mov(r0, Operand(isolate->factory()->infinity_value()));
@@ skipping 40 matching lines @@
   HandleScope scope(isolate);
 
   Assembler assm(isolate, NULL, 0);
   __ mov(r0, Operand(isolate->factory()->infinity_value()));
   __ BlockConstPoolFor(1019);
   for (int i = 0; i < 1019; ++i) __ nop();
   __ vldr(d0, MemOperand(r0, 0));
 }
 
 #undef __