[Turbofan] Add ARM support for simd128 moves and swaps.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_ARM
 
@@ skipping 3725 matching lines @@
         UNIMPLEMENTED();  // Not used by V8.
     }
   } else {
     UNIMPLEMENTED();  // Not used by V8.
   }
 }
 
 
 void Simulator::DecodeSpecialCondition(Instruction* instr) {
   switch (instr->SpecialValue()) {
+    case 4:
+      if (instr->Bits(21, 20) == 2 && instr->Bits(11, 8) == 1 &&
+          instr->Bit(4) == 1) {
+        // vmov Qd, Qm
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        uint32_t data[4];
+        get_q_register(Vm, data);
+        set_q_register(Vd, data);
+      } else {
+        UNIMPLEMENTED();
+      }
+      break;
     case 5:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl signed
         if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
         int Vm = (instr->Bit(5) << 4) | instr->VmValue();
         int imm3 = instr->Bits(21, 19);
         if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
         int esize = 8 * imm3;
         int elements = 64 / esize;
         int8_t from[8];
         get_d_register(Vm, reinterpret_cast<uint64_t*>(from));
         int16_t to[8];
         int e = 0;
         while (e < elements) {
           to[e] = from[e];
           e++;
         }
         set_q_register(Vd, reinterpret_cast<uint64_t*>(to));
       } else {
         UNIMPLEMENTED();
       }
       break;
+    case 6:
+      if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 1 &&
+          instr->Bit(4) == 1) {
+        if (instr->Bit(6) == 0) {
+          // veor Dd, Dn, Dm
+          int Vd = instr->VFPDRegValue(kDoublePrecision);
+          int Vn = instr->VFPNRegValue(kDoublePrecision);
+          int Vm = instr->VFPMRegValue(kDoublePrecision);
+          uint64_t n_data, m_data;
+          get_d_register(Vn, &n_data);
+          get_d_register(Vm, &m_data);
+          n_data ^= m_data;
+          set_d_register(Vd, &n_data);
+
+        } else {
+          // veor Qd, Qn, Qm
+          int Vd = instr->VFPDRegValue(kSimd128Precision);
+          int Vn = instr->VFPNRegValue(kSimd128Precision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          uint32_t n_data[4], m_data[4];
+          get_q_register(Vn, n_data);
+          get_q_register(Vm, m_data);
+          for (int i = 0; i < 4; i++) n_data[i] ^= m_data[i];
+          set_q_register(Vd, n_data);
+        }
+      } else {
+        UNIMPLEMENTED();
+      }
+      break;
     case 7:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl unsigned
         if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
         int Vm = (instr->Bit(5) << 4) | instr->VmValue();
         int imm3 = instr->Bits(21, 19);
         if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
         int esize = 8 * imm3;
         int elements = 64 / esize;
         uint8_t from[8];
         get_d_register(Vm, reinterpret_cast<uint64_t*>(from));
         uint16_t to[8];
         int e = 0;
         while (e < elements) {
           to[e] = from[e];
           e++;
         }
         set_q_register(Vd, reinterpret_cast<uint64_t*>(to));
       } else if ((instr->Bits(21, 16) == 0x32) && (instr->Bits(11, 7) == 0) &&
                  (instr->Bit(4) == 0)) {
-        int vd = instr->VFPDRegValue(kDoublePrecision);
-        int vm = instr->VFPMRegValue(kDoublePrecision);
         if (instr->Bit(6) == 0) {
           // vswp Dd, Dm.
           uint64_t dval, mval;
+          int vd = instr->VFPDRegValue(kDoublePrecision);
+          int vm = instr->VFPMRegValue(kDoublePrecision);
           get_d_register(vd, &dval);
           get_d_register(vm, &mval);
           set_d_register(vm, &dval);
           set_d_register(vd, &mval);
         } else {
-          // Q register vswp unimplemented.
-          UNIMPLEMENTED();
+          // vswp Qd, Qm.
+          uint32_t dval[4], mval[4];
+          int vd = instr->VFPDRegValue(kSimd128Precision);
+          int vm = instr->VFPMRegValue(kSimd128Precision);
+          get_q_register(vd, dval);
+          get_q_register(vm, mval);
+          set_q_register(vm, dval);
+          set_q_register(vd, mval);
         }
       } else {
         UNIMPLEMENTED();
       }
       break;
     case 8:
       if (instr->Bits(21, 20) == 0) {
         // vst1
         int Vd = (instr->Bit(22) << 4) | instr->VdValue();
         int Rn = instr->VnValue();
@@ skipping 501 matching lines @@
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM