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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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295 int code() const { | 295 int code() const { |
296 DCHECK(is_valid()); | 296 DCHECK(is_valid()); |
297 return reg_code; | 297 return reg_code; |
298 } | 298 } |
299 void split_code(int* vm, int* m) const { | 299 void split_code(int* vm, int* m) const { |
300 DCHECK(is_valid()); | 300 DCHECK(is_valid()); |
301 int encoded_code = reg_code << 1; | 301 int encoded_code = reg_code << 1; |
302 *m = (encoded_code & 0x10) >> 4; | 302 *m = (encoded_code & 0x10) >> 4; |
303 *vm = encoded_code & 0x0F; | 303 *vm = encoded_code & 0x0F; |
304 } | 304 } |
| 305 DwVfpRegister low() const { |
| 306 DwVfpRegister reg; |
| 307 reg.reg_code = reg_code * 2; |
| 308 |
| 309 DCHECK(reg.is_valid()); |
| 310 return reg; |
| 311 } |
| 312 DwVfpRegister high() const { |
| 313 DwVfpRegister reg; |
| 314 reg.reg_code = reg_code * 2 + 1; |
| 315 |
| 316 DCHECK(reg.is_valid()); |
| 317 return reg; |
| 318 } |
305 | 319 |
306 int reg_code; | 320 int reg_code; |
307 }; | 321 }; |
308 | 322 |
309 | 323 |
310 typedef QwNeonRegister QuadRegister; | 324 typedef QwNeonRegister QuadRegister; |
311 | 325 |
312 typedef QwNeonRegister Simd128Register; | 326 typedef QwNeonRegister Simd128Register; |
313 | 327 |
314 // Support for the VFP registers s0 to s31 (d0 to d15). | 328 // Support for the VFP registers s0 to s31 (d0 to d15). |
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396 const QwNeonRegister q13 = { 13 }; | 410 const QwNeonRegister q13 = { 13 }; |
397 const QwNeonRegister q14 = { 14 }; | 411 const QwNeonRegister q14 = { 14 }; |
398 const QwNeonRegister q15 = { 15 }; | 412 const QwNeonRegister q15 = { 15 }; |
399 | 413 |
400 | 414 |
401 // Aliases for double registers. Defined using #define instead of | 415 // Aliases for double registers. Defined using #define instead of |
402 // "static const DwVfpRegister&" because Clang complains otherwise when a | 416 // "static const DwVfpRegister&" because Clang complains otherwise when a |
403 // compilation unit that includes this header doesn't use the variables. | 417 // compilation unit that includes this header doesn't use the variables. |
404 #define kFirstCalleeSavedDoubleReg d8 | 418 #define kFirstCalleeSavedDoubleReg d8 |
405 #define kLastCalleeSavedDoubleReg d15 | 419 #define kLastCalleeSavedDoubleReg d15 |
| 420 // kDoubleRegZero and kScratchDoubleReg must pair to form kScratchQuadReg. |
406 #define kDoubleRegZero d14 | 421 #define kDoubleRegZero d14 |
407 #define kScratchDoubleReg d15 | 422 #define kScratchDoubleReg d15 |
408 | 423 // After using kScratchQuadReg, kDoubleRegZero must be reset to 0. |
| 424 #define kScratchQuadReg q7 |
409 | 425 |
410 // Coprocessor register | 426 // Coprocessor register |
411 struct CRegister { | 427 struct CRegister { |
412 bool is_valid() const { return 0 <= reg_code && reg_code < 16; } | 428 bool is_valid() const { return 0 <= reg_code && reg_code < 16; } |
413 bool is(CRegister creg) const { return reg_code == creg.reg_code; } | 429 bool is(CRegister creg) const { return reg_code == creg.reg_code; } |
414 int code() const { | 430 int code() const { |
415 DCHECK(is_valid()); | 431 DCHECK(is_valid()); |
416 return reg_code; | 432 return reg_code; |
417 } | 433 } |
418 int bit() const { | 434 int bit() const { |
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1306 | 1322 |
1307 // All these APIs support D0 to D31 and Q0 to Q15. | 1323 // All these APIs support D0 to D31 and Q0 to Q15. |
1308 void vld1(NeonSize size, | 1324 void vld1(NeonSize size, |
1309 const NeonListOperand& dst, | 1325 const NeonListOperand& dst, |
1310 const NeonMemOperand& src); | 1326 const NeonMemOperand& src); |
1311 void vst1(NeonSize size, | 1327 void vst1(NeonSize size, |
1312 const NeonListOperand& src, | 1328 const NeonListOperand& src, |
1313 const NeonMemOperand& dst); | 1329 const NeonMemOperand& dst); |
1314 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); | 1330 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); |
1315 | 1331 |
1316 // Currently, vswp supports only D0 to D31. | 1332 void vmov(const QwNeonRegister dst, const QwNeonRegister src); |
1317 void vswp(DwVfpRegister srcdst0, DwVfpRegister srcdst1); | 1333 void vswp(DwVfpRegister dst, DwVfpRegister src); |
| 1334 void vswp(QwNeonRegister dst, QwNeonRegister src); |
| 1335 void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2); |
| 1336 void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2); |
1318 | 1337 |
1319 // Pseudo instructions | 1338 // Pseudo instructions |
1320 | 1339 |
1321 // Different nop operations are used by the code generator to detect certain | 1340 // Different nop operations are used by the code generator to detect certain |
1322 // states of the generated code. | 1341 // states of the generated code. |
1323 enum NopMarkerTypes { | 1342 enum NopMarkerTypes { |
1324 NON_MARKING_NOP = 0, | 1343 NON_MARKING_NOP = 0, |
1325 DEBUG_BREAK_NOP, | 1344 DEBUG_BREAK_NOP, |
1326 // IC markers. | 1345 // IC markers. |
1327 PROPERTY_ACCESS_INLINED, | 1346 PROPERTY_ACCESS_INLINED, |
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1601 return (const_pool_blocked_nesting_ > 0) || | 1620 return (const_pool_blocked_nesting_ > 0) || |
1602 (pc_offset() < no_const_pool_before_); | 1621 (pc_offset() < no_const_pool_before_); |
1603 } | 1622 } |
1604 | 1623 |
1605 bool VfpRegisterIsAvailable(DwVfpRegister reg) { | 1624 bool VfpRegisterIsAvailable(DwVfpRegister reg) { |
1606 DCHECK(reg.is_valid()); | 1625 DCHECK(reg.is_valid()); |
1607 return IsEnabled(VFP32DREGS) || | 1626 return IsEnabled(VFP32DREGS) || |
1608 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters); | 1627 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters); |
1609 } | 1628 } |
1610 | 1629 |
| 1630 bool VfpRegisterIsAvailable(QwNeonRegister reg) { |
| 1631 DCHECK(reg.is_valid()); |
| 1632 return IsEnabled(VFP32DREGS) || |
| 1633 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters / 2); |
| 1634 } |
| 1635 |
1611 private: | 1636 private: |
1612 int next_buffer_check_; // pc offset of next buffer check | 1637 int next_buffer_check_; // pc offset of next buffer check |
1613 | 1638 |
1614 // Code generation | 1639 // Code generation |
1615 // The relocation writer's position is at least kGap bytes below the end of | 1640 // The relocation writer's position is at least kGap bytes below the end of |
1616 // the generated instructions. This is so that multi-instruction sequences do | 1641 // the generated instructions. This is so that multi-instruction sequences do |
1617 // not have to check for overflow. The same is true for writes of large | 1642 // not have to check for overflow. The same is true for writes of large |
1618 // relocation info entries. | 1643 // relocation info entries. |
1619 static const int kGap = 32; | 1644 static const int kGap = 32; |
1620 | 1645 |
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1707 explicit EnsureSpace(Assembler* assembler) { | 1732 explicit EnsureSpace(Assembler* assembler) { |
1708 assembler->CheckBuffer(); | 1733 assembler->CheckBuffer(); |
1709 } | 1734 } |
1710 }; | 1735 }; |
1711 | 1736 |
1712 | 1737 |
1713 } // namespace internal | 1738 } // namespace internal |
1714 } // namespace v8 | 1739 } // namespace v8 |
1715 | 1740 |
1716 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1741 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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