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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <stdarg.h> | 5 #include <stdarg.h> |
6 #include <stdlib.h> | 6 #include <stdlib.h> |
7 #include <cmath> | 7 #include <cmath> |
8 | 8 |
9 #if V8_TARGET_ARCH_ARM | 9 #if V8_TARGET_ARCH_ARM |
10 | 10 |
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3736 UNIMPLEMENTED(); // Not used by V8. | 3736 UNIMPLEMENTED(); // Not used by V8. |
3737 } | 3737 } |
3738 } else { | 3738 } else { |
3739 UNIMPLEMENTED(); // Not used by V8. | 3739 UNIMPLEMENTED(); // Not used by V8. |
3740 } | 3740 } |
3741 } | 3741 } |
3742 | 3742 |
3743 | 3743 |
3744 void Simulator::DecodeSpecialCondition(Instruction* instr) { | 3744 void Simulator::DecodeSpecialCondition(Instruction* instr) { |
3745 switch (instr->SpecialValue()) { | 3745 switch (instr->SpecialValue()) { |
| 3746 case 4: |
| 3747 if (instr->Bits(27, 23) == 4 && instr->Bits(21, 20) == 2 && |
| 3748 instr->Bits(11, 8) == 1 && instr->Bit(4) == 1) { |
| 3749 // vmov Qd, Qm |
| 3750 int Vd = instr->VFPDRegValue(kSimd128Precision); |
| 3751 int Vm = instr->VFPMRegValue(kSimd128Precision); |
| 3752 uint32_t data[4]; |
| 3753 get_q_register(Vm, data); |
| 3754 set_q_register(Vd, data); |
| 3755 } else { |
| 3756 UNIMPLEMENTED(); |
| 3757 } |
| 3758 break; |
3746 case 5: | 3759 case 5: |
3747 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && | 3760 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && |
3748 (instr->Bit(4) == 1)) { | 3761 (instr->Bit(4) == 1)) { |
3749 // vmovl signed | 3762 // vmovl signed |
3750 if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED(); | 3763 if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED(); |
3751 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); | 3764 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); |
3752 int Vm = (instr->Bit(5) << 4) | instr->VmValue(); | 3765 int Vm = (instr->Bit(5) << 4) | instr->VmValue(); |
3753 int imm3 = instr->Bits(21, 19); | 3766 int imm3 = instr->Bits(21, 19); |
3754 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED(); | 3767 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED(); |
3755 int esize = 8 * imm3; | 3768 int esize = 8 * imm3; |
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3782 get_d_register(Vm, reinterpret_cast<uint64_t*>(from)); | 3795 get_d_register(Vm, reinterpret_cast<uint64_t*>(from)); |
3783 uint16_t to[8]; | 3796 uint16_t to[8]; |
3784 int e = 0; | 3797 int e = 0; |
3785 while (e < elements) { | 3798 while (e < elements) { |
3786 to[e] = from[e]; | 3799 to[e] = from[e]; |
3787 e++; | 3800 e++; |
3788 } | 3801 } |
3789 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); | 3802 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); |
3790 } else if ((instr->Bits(21, 16) == 0x32) && (instr->Bits(11, 7) == 0) && | 3803 } else if ((instr->Bits(21, 16) == 0x32) && (instr->Bits(11, 7) == 0) && |
3791 (instr->Bit(4) == 0)) { | 3804 (instr->Bit(4) == 0)) { |
3792 int vd = instr->VFPDRegValue(kDoublePrecision); | |
3793 int vm = instr->VFPMRegValue(kDoublePrecision); | |
3794 if (instr->Bit(6) == 0) { | 3805 if (instr->Bit(6) == 0) { |
3795 // vswp Dd, Dm. | 3806 // vswp Dd, Dm. |
3796 uint64_t dval, mval; | 3807 uint64_t dval, mval; |
| 3808 int vd = instr->VFPDRegValue(kDoublePrecision); |
| 3809 int vm = instr->VFPMRegValue(kDoublePrecision); |
3797 get_d_register(vd, &dval); | 3810 get_d_register(vd, &dval); |
3798 get_d_register(vm, &mval); | 3811 get_d_register(vm, &mval); |
3799 set_d_register(vm, &dval); | 3812 set_d_register(vm, &dval); |
3800 set_d_register(vd, &mval); | 3813 set_d_register(vd, &mval); |
3801 } else { | 3814 } else { |
3802 // Q register vswp unimplemented. | 3815 // vswp Qd, Qm. |
3803 UNIMPLEMENTED(); | 3816 uint32_t dval[4], mval[4]; |
| 3817 int vd = instr->VFPDRegValue(kSimd128Precision); |
| 3818 int vm = instr->VFPMRegValue(kSimd128Precision); |
| 3819 get_q_register(vd, dval); |
| 3820 get_q_register(vm, mval); |
| 3821 set_q_register(vm, dval); |
| 3822 set_q_register(vd, mval); |
3804 } | 3823 } |
3805 } else { | 3824 } else { |
3806 UNIMPLEMENTED(); | 3825 UNIMPLEMENTED(); |
3807 } | 3826 } |
3808 break; | 3827 break; |
3809 case 8: | 3828 case 8: |
3810 if (instr->Bits(21, 20) == 0) { | 3829 if (instr->Bits(21, 20) == 0) { |
3811 // vst1 | 3830 // vst1 |
3812 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); | 3831 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); |
3813 int Rn = instr->VnValue(); | 3832 int Rn = instr->VnValue(); |
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4315 set_register(sp, current_sp + sizeof(uintptr_t)); | 4334 set_register(sp, current_sp + sizeof(uintptr_t)); |
4316 return address; | 4335 return address; |
4317 } | 4336 } |
4318 | 4337 |
4319 } // namespace internal | 4338 } // namespace internal |
4320 } // namespace v8 | 4339 } // namespace v8 |
4321 | 4340 |
4322 #endif // USE_SIMULATOR | 4341 #endif // USE_SIMULATOR |
4323 | 4342 |
4324 #endif // V8_TARGET_ARCH_ARM | 4343 #endif // V8_TARGET_ARCH_ARM |
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