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Issue 2523473002: [cleanup] Drop handwritten KeyedStoreIC code (Closed)
Patch Set: rebased Created 4 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #if V8_TARGET_ARCH_X64
6
7 #include "src/codegen.h"
8 #include "src/ic/ic.h"
9 #include "src/ic/stub-cache.h"
10 #include "src/interface-descriptors.h"
11
12 namespace v8 {
13 namespace internal {
14
15 #define __ ACCESS_MASM(masm)
16
17 static void ProbeTable(StubCache* stub_cache, MacroAssembler* masm,
18 StubCache::Table table, Register receiver, Register name,
19 // The offset is scaled by 4, based on
20 // kCacheIndexShift, which is two bits
21 Register offset) {
22 // We need to scale up the pointer by 2 when the offset is scaled by less
23 // than the pointer size.
24 DCHECK(kPointerSize == kInt64Size
25 ? kPointerSizeLog2 == StubCache::kCacheIndexShift + 1
26 : kPointerSizeLog2 == StubCache::kCacheIndexShift);
27 ScaleFactor scale_factor = kPointerSize == kInt64Size ? times_2 : times_1;
28
29 DCHECK_EQ(3u * kPointerSize, sizeof(StubCache::Entry));
30 // The offset register holds the entry offset times four (due to masking
31 // and shifting optimizations).
32 ExternalReference key_offset(stub_cache->key_reference(table));
33 ExternalReference value_offset(stub_cache->value_reference(table));
34 Label miss;
35
36 // Multiply by 3 because there are 3 fields per entry (name, code, map).
37 __ leap(offset, Operand(offset, offset, times_2, 0));
38
39 __ LoadAddress(kScratchRegister, key_offset);
40
41 // Check that the key in the entry matches the name.
42 __ cmpp(name, Operand(kScratchRegister, offset, scale_factor, 0));
43 __ j(not_equal, &miss);
44
45 // Get the map entry from the cache.
46 // Use key_offset + kPointerSize * 2, rather than loading map_offset.
47 DCHECK(stub_cache->map_reference(table).address() -
48 stub_cache->key_reference(table).address() ==
49 kPointerSize * 2);
50 __ movp(kScratchRegister,
51 Operand(kScratchRegister, offset, scale_factor, kPointerSize * 2));
52 __ cmpp(kScratchRegister, FieldOperand(receiver, HeapObject::kMapOffset));
53 __ j(not_equal, &miss);
54
55 // Get the code entry from the cache.
56 __ LoadAddress(kScratchRegister, value_offset);
57 __ movp(kScratchRegister, Operand(kScratchRegister, offset, scale_factor, 0));
58
59 #ifdef DEBUG
60 if (FLAG_test_secondary_stub_cache && table == StubCache::kPrimary) {
61 __ jmp(&miss);
62 } else if (FLAG_test_primary_stub_cache && table == StubCache::kSecondary) {
63 __ jmp(&miss);
64 }
65 #endif
66
67 // Jump to the first instruction in the code stub.
68 __ addp(kScratchRegister, Immediate(Code::kHeaderSize - kHeapObjectTag));
69 __ jmp(kScratchRegister);
70
71 __ bind(&miss);
72 }
73
74 void StubCache::GenerateProbe(MacroAssembler* masm, Register receiver,
75 Register name, Register scratch, Register extra,
76 Register extra2, Register extra3) {
77 Label miss;
78 USE(extra); // The register extra is not used on the X64 platform.
79 USE(extra2); // The register extra2 is not used on the X64 platform.
80 USE(extra3); // The register extra2 is not used on the X64 platform.
81 // Make sure that code is valid. The multiplying code relies on the
82 // entry size being 3 * kPointerSize.
83 DCHECK(sizeof(Entry) == 3 * kPointerSize);
84
85 // Make sure that there are no register conflicts.
86 DCHECK(!scratch.is(receiver));
87 DCHECK(!scratch.is(name));
88
89 // Check scratch register is valid, extra and extra2 are unused.
90 DCHECK(!scratch.is(no_reg));
91 DCHECK(extra2.is(no_reg));
92 DCHECK(extra3.is(no_reg));
93
94 #ifdef DEBUG
95 // If vector-based ics are in use, ensure that scratch doesn't conflict with
96 // the vector and slot registers, which need to be preserved for a handler
97 // call or miss.
98 if (IC::ICUseVector(ic_kind_)) {
99 if (ic_kind_ == Code::LOAD_IC || ic_kind_ == Code::KEYED_LOAD_IC) {
100 Register vector = LoadWithVectorDescriptor::VectorRegister();
101 Register slot = LoadDescriptor::SlotRegister();
102 DCHECK(!AreAliased(vector, slot, scratch));
103 } else {
104 DCHECK(ic_kind_ == Code::STORE_IC || ic_kind_ == Code::KEYED_STORE_IC);
105 Register vector = StoreWithVectorDescriptor::VectorRegister();
106 Register slot = StoreWithVectorDescriptor::SlotRegister();
107 DCHECK(!AreAliased(vector, slot, scratch));
108 }
109 }
110 #endif
111
112 Counters* counters = masm->isolate()->counters();
113 __ IncrementCounter(counters->megamorphic_stub_cache_probes(), 1);
114
115 // Check that the receiver isn't a smi.
116 __ JumpIfSmi(receiver, &miss);
117
118 // Get the map of the receiver and compute the hash.
119 __ movl(scratch, FieldOperand(name, Name::kHashFieldOffset));
120 // Use only the low 32 bits of the map pointer.
121 __ addl(scratch, FieldOperand(receiver, HeapObject::kMapOffset));
122 __ xorp(scratch, Immediate(kPrimaryMagic));
123 // We mask out the last two bits because they are not part of the hash and
124 // they are always 01 for maps. Also in the two 'and' instructions below.
125 __ andp(scratch, Immediate((kPrimaryTableSize - 1) << kCacheIndexShift));
126
127 // Probe the primary table.
128 ProbeTable(this, masm, kPrimary, receiver, name, scratch);
129
130 // Primary miss: Compute hash for secondary probe.
131 __ movl(scratch, FieldOperand(name, Name::kHashFieldOffset));
132 __ addl(scratch, FieldOperand(receiver, HeapObject::kMapOffset));
133 __ xorp(scratch, Immediate(kPrimaryMagic));
134 __ andp(scratch, Immediate((kPrimaryTableSize - 1) << kCacheIndexShift));
135 __ subl(scratch, name);
136 __ addl(scratch, Immediate(kSecondaryMagic));
137 __ andp(scratch, Immediate((kSecondaryTableSize - 1) << kCacheIndexShift));
138
139 // Probe the secondary table.
140 ProbeTable(this, masm, kSecondary, receiver, name, scratch);
141
142 // Cache miss: Fall-through and let caller handle the miss by
143 // entering the runtime system.
144 __ bind(&miss);
145 __ IncrementCounter(counters->megamorphic_stub_cache_misses(), 1);
146 }
147
148
149 #undef __
150 } // namespace internal
151 } // namespace v8
152
153 #endif // V8_TARGET_ARCH_X64
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