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Side by Side Diff: runtime/vm/assembler_arm.h

Issue 252333002: Use GPRs for mints (Closed) Base URL: https://dart.googlecode.com/svn/branches/bleeding_edge/dart
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_ARM_H_ 5 #ifndef VM_ASSEMBLER_ARM_H_
6 #define VM_ASSEMBLER_ARM_H_ 6 #define VM_ASSEMBLER_ARM_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_arm.h directly; use assembler.h instead. 9 #error Do not include assembler_arm.h directly; use assembler.h instead.
10 #endif 10 #endif
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344 344
345 void rsb(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 345 void rsb(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
346 void rsbs(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 346 void rsbs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
347 347
348 void add(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 348 void add(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
349 349
350 void adds(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 350 void adds(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
351 351
352 void adc(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 352 void adc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
353 353
354 void adcs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
355
354 void sbc(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 356 void sbc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
355 357
358 void sbcs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
359
356 void rsc(Register rd, Register rn, ShifterOperand so, Condition cond = AL); 360 void rsc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
357 361
358 void tst(Register rn, ShifterOperand so, Condition cond = AL); 362 void tst(Register rn, ShifterOperand so, Condition cond = AL);
359 363
360 void teq(Register rn, ShifterOperand so, Condition cond = AL); 364 void teq(Register rn, ShifterOperand so, Condition cond = AL);
361 365
362 void cmp(Register rn, ShifterOperand so, Condition cond = AL); 366 void cmp(Register rn, ShifterOperand so, Condition cond = AL);
363 367
364 void cmn(Register rn, ShifterOperand so, Condition cond = AL); 368 void cmn(Register rn, ShifterOperand so, Condition cond = AL);
365 369
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687 void Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL); 691 void Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
688 void Lsl(Register rd, Register rm, Register rs, Condition cond = AL); 692 void Lsl(Register rd, Register rm, Register rs, Condition cond = AL);
689 void Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL); 693 void Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
690 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL); 694 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
691 void Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL); 695 void Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
692 void Asr(Register rd, Register rm, Register rs, Condition cond = AL); 696 void Asr(Register rd, Register rm, Register rs, Condition cond = AL);
693 void Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL); 697 void Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
694 void Ror(Register rd, Register rm, Register rs, Condition cond = AL); 698 void Ror(Register rd, Register rm, Register rs, Condition cond = AL);
695 void Rrx(Register rd, Register rm, Condition cond = AL); 699 void Rrx(Register rd, Register rm, Condition cond = AL);
696 700
701 // Fill rd with the sign of rm.
702 void SignFill(Register rd, Register rm);
regis 2014/05/22 17:09:40 For regularity, you could make this conditional.
703
697 void Vreciprocalqs(QRegister qd, QRegister qm); 704 void Vreciprocalqs(QRegister qd, QRegister qm);
698 void VreciprocalSqrtqs(QRegister qd, QRegister qm); 705 void VreciprocalSqrtqs(QRegister qd, QRegister qm);
699 // If qm must be preserved, then provide a (non-QTMP) temporary. 706 // If qm must be preserved, then provide a (non-QTMP) temporary.
700 void Vsqrtqs(QRegister qd, QRegister qm, QRegister temp); 707 void Vsqrtqs(QRegister qd, QRegister qm, QRegister temp);
701 void Vdivqs(QRegister qd, QRegister qn, QRegister qm); 708 void Vdivqs(QRegister qd, QRegister qn, QRegister qm);
702 709
703 void SmiTag(Register reg, Condition cond = AL) { 710 void SmiTag(Register reg, Condition cond = AL) {
704 Lsl(reg, reg, kSmiTagSize, cond); 711 Lsl(reg, reg, kSmiTagSize, cond);
705 } 712 }
706 713
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907 Register value, 914 Register value,
908 Label* no_update); 915 Label* no_update);
909 916
910 DISALLOW_ALLOCATION(); 917 DISALLOW_ALLOCATION();
911 DISALLOW_COPY_AND_ASSIGN(Assembler); 918 DISALLOW_COPY_AND_ASSIGN(Assembler);
912 }; 919 };
913 920
914 } // namespace dart 921 } // namespace dart
915 922
916 #endif // VM_ASSEMBLER_ARM_H_ 923 #endif // VM_ASSEMBLER_ARM_H_
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