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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
7 | 7 |
8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
9 #include "vm/cpu.h" | 9 #include "vm/cpu.h" |
10 #include "vm/longjump.h" | 10 #include "vm/longjump.h" |
(...skipping 255 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
266 EmitType01(cond, so.type(), SUB, 1, rn, rd, so); | 266 EmitType01(cond, so.type(), SUB, 1, rn, rd, so); |
267 } | 267 } |
268 | 268 |
269 | 269 |
270 void Assembler::adc(Register rd, Register rn, ShifterOperand so, | 270 void Assembler::adc(Register rd, Register rn, ShifterOperand so, |
271 Condition cond) { | 271 Condition cond) { |
272 EmitType01(cond, so.type(), ADC, 0, rn, rd, so); | 272 EmitType01(cond, so.type(), ADC, 0, rn, rd, so); |
273 } | 273 } |
274 | 274 |
275 | 275 |
| 276 void Assembler::adcs(Register rd, Register rn, ShifterOperand so, |
| 277 Condition cond) { |
| 278 EmitType01(cond, so.type(), ADC, 1, rn, rd, so); |
| 279 } |
| 280 |
| 281 |
276 void Assembler::sbc(Register rd, Register rn, ShifterOperand so, | 282 void Assembler::sbc(Register rd, Register rn, ShifterOperand so, |
277 Condition cond) { | 283 Condition cond) { |
278 EmitType01(cond, so.type(), SBC, 0, rn, rd, so); | 284 EmitType01(cond, so.type(), SBC, 0, rn, rd, so); |
279 } | 285 } |
280 | 286 |
281 | 287 |
| 288 void Assembler::sbcs(Register rd, Register rn, ShifterOperand so, |
| 289 Condition cond) { |
| 290 EmitType01(cond, so.type(), SBC, 1, rn, rd, so); |
| 291 } |
| 292 |
| 293 |
282 void Assembler::rsc(Register rd, Register rn, ShifterOperand so, | 294 void Assembler::rsc(Register rd, Register rn, ShifterOperand so, |
283 Condition cond) { | 295 Condition cond) { |
284 EmitType01(cond, so.type(), RSC, 0, rn, rd, so); | 296 EmitType01(cond, so.type(), RSC, 0, rn, rd, so); |
285 } | 297 } |
286 | 298 |
287 | 299 |
288 void Assembler::tst(Register rn, ShifterOperand so, Condition cond) { | 300 void Assembler::tst(Register rn, ShifterOperand so, Condition cond) { |
289 EmitType01(cond, so.type(), TST, 1, rn, R0, so); | 301 EmitType01(cond, so.type(), TST, 1, rn, R0, so); |
290 } | 302 } |
291 | 303 |
(...skipping 1862 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2154 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) { | 2166 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) { |
2155 mov(rd, ShifterOperand(rm, ROR, rs), cond); | 2167 mov(rd, ShifterOperand(rm, ROR, rs), cond); |
2156 } | 2168 } |
2157 | 2169 |
2158 | 2170 |
2159 void Assembler::Rrx(Register rd, Register rm, Condition cond) { | 2171 void Assembler::Rrx(Register rd, Register rm, Condition cond) { |
2160 mov(rd, ShifterOperand(rm, ROR, 0), cond); | 2172 mov(rd, ShifterOperand(rm, ROR, 0), cond); |
2161 } | 2173 } |
2162 | 2174 |
2163 | 2175 |
| 2176 void Assembler::SignFill(Register rd, Register rm) { |
| 2177 Asr(rd, rm, 31); |
| 2178 } |
| 2179 |
| 2180 |
2164 void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) { | 2181 void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) { |
2165 ASSERT(qm != QTMP); | 2182 ASSERT(qm != QTMP); |
2166 ASSERT(qd != QTMP); | 2183 ASSERT(qd != QTMP); |
2167 | 2184 |
2168 // Reciprocal estimate. | 2185 // Reciprocal estimate. |
2169 vrecpeqs(qd, qm); | 2186 vrecpeqs(qd, qm); |
2170 // 2 Newton-Raphson steps. | 2187 // 2 Newton-Raphson steps. |
2171 vrecpsqs(QTMP, qm, qd); | 2188 vrecpsqs(QTMP, qm, qd); |
2172 vmulqs(qd, qd, QTMP); | 2189 vmulqs(qd, qd, QTMP); |
2173 vrecpsqs(QTMP, qm, qd); | 2190 vrecpsqs(QTMP, qm, qd); |
(...skipping 961 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3135 | 3152 |
3136 | 3153 |
3137 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3154 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3138 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3155 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3139 return fpu_reg_names[reg]; | 3156 return fpu_reg_names[reg]; |
3140 } | 3157 } |
3141 | 3158 |
3142 } // namespace dart | 3159 } // namespace dart |
3143 | 3160 |
3144 #endif // defined TARGET_ARCH_ARM | 3161 #endif // defined TARGET_ARCH_ARM |
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