Subzero, MIPS32: Changes for improving sandbox crosstest results

pydir/crosstest.py

Index: pydir/crosstest.py
diff --git a/pydir/crosstest.py b/pydir/crosstest.py
index 075102cc1ec05455f2c394abce2302f4260dc918..6f8ed5716710cc05d7f13b78265ad3284ce5f8c7 100755
--- a/pydir/crosstest.py
+++ b/pydir/crosstest.py
@@ -158,7 +158,9 @@ def main():
                   bitcode] + arch_sz_flags[args.target])
         if args.filetype != 'obj':
             shellcmd(['{bin}/llvm-mc'.format(bin=bindir),
-                      '-triple=' + triple,
+                      '-triple=' + ('mipsel-linux-gnu'

[Jim Stichnoth, 2016/11/21 20:08:39]

Is it possible to use a nacl-specific tuple for MIPS?  This is what the other
targets do, and that may also mean that the new .bundle_align_mode directive in
IceTargetLoweringMIPS32.cpp would not be needed.

[Stefan Maksimovic, 2016/11/22 11:38:13]

This change stems from the fact that when we run the crosstests in asm mode,
llvm-mc does its own sandboxing which results in duplicate instructions
generated, therefore exceeding the maximum bundle size.
We had two options, either to let subzero do the sandboxing and somehow
prevent llvm-mc from doing it, or vice versa.

We opted for the former, since letting llvm-mc do the sandboxing somehow
doesn't isolate t6, t7 and t8 registers which are used for storing masks
used in sandboxing, which in turn get used where they shouldn't be.
The way in which we accomplished that is to change the triple in this very
spot, i.e. from mipsel-nacl to mipsel-linux-gnu.
This in turn required that we generate the .bundle_align_mode directive.

We tried going the other way, but I am unaware whether there is a way to
tell llvm-mc to sequester said registers.

[Jim Stichnoth, 2016/11/22 18:25:30]

Ah, OK, that's very interesting.  Thanks for the explanation.

+                                    if args.target == 'mips32' and args.sandbox
+                                    else triple),
                       '-filetype=obj',
                       '-o=' + obj_sz,
                       asm_sz])