[wasm] Add ProtectedStore instruction

src/compiler/x64/instruction-selector-x64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <algorithm>
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
@@ skipping 162 matching lines @@
     }
   }
 
   bool CanBeBetterLeftOperand(Node* node) const {
     return !selector()->IsLive(node);
   }
 };
 
 namespace {
 
-ArchOpcode GetLoadOpcode(LoadRepresentation load_rep) {
+ArchOpcode GetLoadOpcode(LoadRepresentation load_rep, bool protect) {
   ArchOpcode opcode = kArchNop;
   switch (load_rep.representation()) {
     case MachineRepresentation::kFloat32:
+      DCHECK(!protect);

[titzer, 2016/11/22 10:33:20]

We'll need to support all of these types with protected loads and stores.

Maybe we should encode whether the load/store can trap with another bit in the
instruction opcode?

[Eric Holk, 2016/11/22 23:16:25]

I think this is a better idea. It looks like I can put it in the misc field.

       opcode = kX64Movss;
       break;
     case MachineRepresentation::kFloat64:
+      DCHECK(!protect);
       opcode = kX64Movsd;
       break;
     case MachineRepresentation::kBit:  // Fall through.
     case MachineRepresentation::kWord8:
+      DCHECK(!protect);
       opcode = load_rep.IsSigned() ? kX64Movsxbl : kX64Movzxbl;
       break;
     case MachineRepresentation::kWord16:
+      DCHECK(!protect);
       opcode = load_rep.IsSigned() ? kX64Movsxwl : kX64Movzxwl;
       break;
     case MachineRepresentation::kWord32:
-      opcode = kX64Movl;
+      opcode = protect ? kX64TrapMovl : kX64Movl;
       break;
     case MachineRepresentation::kTaggedSigned:   // Fall through.
     case MachineRepresentation::kTaggedPointer:  // Fall through.
     case MachineRepresentation::kTagged:  // Fall through.
     case MachineRepresentation::kWord64:
+      DCHECK(!protect);
       opcode = kX64Movq;
       break;
     case MachineRepresentation::kSimd128:  // Fall through.
     case MachineRepresentation::kNone:
       UNREACHABLE();
       break;
   }
   return opcode;
 }
 
+ArchOpcode GetStoreOpcode(StoreRepresentation store_rep, bool protect) {
+  switch (store_rep.representation()) {
+    case MachineRepresentation::kFloat32:
+      DCHECK(!protect);
+      return kX64Movss;
+      break;
+    case MachineRepresentation::kFloat64:
+      DCHECK(!protect);
+      return kX64Movsd;
+      break;
+    case MachineRepresentation::kBit:  // Fall through.
+    case MachineRepresentation::kWord8:
+      DCHECK(!protect);
+      return kX64Movb;
+      break;
+    case MachineRepresentation::kWord16:
+      DCHECK(!protect);
+      return kX64Movw;
+      break;
+    case MachineRepresentation::kWord32:
+      return protect ? kX64TrapMovl : kX64Movl;
+      break;
+    case MachineRepresentation::kTaggedSigned:   // Fall through.
+    case MachineRepresentation::kTaggedPointer:  // Fall through.
+    case MachineRepresentation::kTagged:         // Fall through.
+    case MachineRepresentation::kWord64:
+      DCHECK(!protect);
+      return kX64Movq;
+      break;
+    case MachineRepresentation::kSimd128:  // Fall through.
+    case MachineRepresentation::kNone:
+      UNREACHABLE();
+      return kArchNop;
+  }
+}
+
 }  // namespace
 
 void InstructionSelector::VisitLoad(Node* node) {
   LoadRepresentation load_rep = LoadRepresentationOf(node->op());
   X64OperandGenerator g(this);
 
-  ArchOpcode opcode = GetLoadOpcode(load_rep);
+  const bool protect = false;
+  ArchOpcode opcode = GetLoadOpcode(load_rep, protect);
   InstructionOperand outputs[1];
   outputs[0] = g.DefineAsRegister(node);
   InstructionOperand inputs[3];
   size_t input_count = 0;
   AddressingMode mode =
       g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
   InstructionCode code = opcode | AddressingModeField::encode(mode);
   Emit(code, 1, outputs, input_count, inputs);
 }
 
 void InstructionSelector::VisitProtectedLoad(Node* node) {
   LoadRepresentation load_rep = LoadRepresentationOf(node->op());
   X64OperandGenerator g(this);
 
-  ArchOpcode opcode = GetLoadOpcode(load_rep);
+  const bool protect = true;
+  ArchOpcode opcode = GetLoadOpcode(load_rep, protect);
   InstructionOperand outputs[1];
   outputs[0] = g.DefineAsRegister(node);
   InstructionOperand inputs[4];
   size_t input_count = 0;
   AddressingMode mode =
       g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
   // Add the context parameter as an input.
   inputs[input_count++] = g.UseUniqueRegister(node->InputAt(2));
   // Add the source position as an input
   inputs[input_count++] = g.UseImmediate(node->InputAt(3));
@@ skipping 40 matching lines @@
         record_write_mode = RecordWriteMode::kValueIsAny;
         break;
     }
     InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
     size_t const temp_count = arraysize(temps);
     InstructionCode code = kArchStoreWithWriteBarrier;
     code |= AddressingModeField::encode(addressing_mode);
     code |= MiscField::encode(static_cast<int>(record_write_mode));
     Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
   } else {
-    ArchOpcode opcode = kArchNop;
-    switch (rep) {
-      case MachineRepresentation::kFloat32:
-        opcode = kX64Movss;
-        break;
-      case MachineRepresentation::kFloat64:
-        opcode = kX64Movsd;
-        break;
-      case MachineRepresentation::kBit:  // Fall through.
-      case MachineRepresentation::kWord8:
-        opcode = kX64Movb;
-        break;
-      case MachineRepresentation::kWord16:
-        opcode = kX64Movw;
-        break;
-      case MachineRepresentation::kWord32:
-        opcode = kX64Movl;
-        break;
-      case MachineRepresentation::kTaggedSigned:   // Fall through.
-      case MachineRepresentation::kTaggedPointer:  // Fall through.
-      case MachineRepresentation::kTagged:  // Fall through.
-      case MachineRepresentation::kWord64:
-        opcode = kX64Movq;
-        break;
-      case MachineRepresentation::kSimd128:  // Fall through.
-      case MachineRepresentation::kNone:
-        UNREACHABLE();
-        return;
-    }
+    const bool protect = false;
+    ArchOpcode opcode = GetStoreOpcode(store_rep, protect);
     InstructionOperand inputs[4];
     size_t input_count = 0;
     AddressingMode addressing_mode =
         g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
     InstructionCode code =
         opcode | AddressingModeField::encode(addressing_mode);
     InstructionOperand value_operand =
         g.CanBeImmediate(value) ? g.UseImmediate(value) : g.UseRegister(value);
     inputs[input_count++] = value_operand;
     Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
          inputs);
   }
 }
 
+void InstructionSelector::VisitProtectedStore(Node* node) {
+  X64OperandGenerator g(this);
+  Node* base = node->InputAt(0);
+  Node* index = node->InputAt(1);
+  Node* value = node->InputAt(2);
+  Node* context = node->InputAt(3);
+  Node* position = node->InputAt(4);
+
+  StoreRepresentation store_rep = StoreRepresentationOf(node->op());
+  WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind();
+  MachineRepresentation rep = store_rep.representation();
+
+  const bool protect = true;
+  ArchOpcode opcode = GetStoreOpcode(store_rep, protect);
+  InstructionOperand inputs[6];
+  size_t input_count = 0;
+  AddressingMode addressing_mode =
+      g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
+  InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
+  InstructionOperand value_operand =
+      g.CanBeImmediate(value) ? g.UseImmediate(value) : g.UseRegister(value);
+  inputs[input_count++] = value_operand;
+  inputs[input_count++] = g.UseRegister(context);
+  inputs[input_count++] = g.UseImmediate(position);
+  Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
+}
+
 // Architecture supports unaligned access, therefore VisitLoad is used instead
 void InstructionSelector::VisitUnalignedLoad(Node* node) { UNREACHABLE(); }
 
 // Architecture supports unaligned access, therefore VisitStore is used instead
 void InstructionSelector::VisitUnalignedStore(Node* node) { UNREACHABLE(); }
 
 void InstructionSelector::VisitCheckedLoad(Node* node) {
   CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op());
   X64OperandGenerator g(this);
   Node* const buffer = node->InputAt(0);
@@ skipping 2034 matching lines @@
 // static
 MachineOperatorBuilder::AlignmentRequirements
 InstructionSelector::AlignmentRequirements() {
   return MachineOperatorBuilder::AlignmentRequirements::
       FullUnalignedAccessSupport();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8