MIPS[64]: Disable Add/Shl to Lsa optimization if operand is immediate

MIPS[64]: Disable Add/Shl to Lsa optimization if operand is immediate

Add/Shl to Lsa optimization doesn't yield any performance increase in case
one of the operand is immediate, because Lsa cannot use the immediate so
we use an extra instruction to load the immediate to register. On MIPSR2 and
less this optimization leads to performance degradation, since Lsa is not
supported on these architectures and it is emulated using Add/Shl which
do support immediate as operand for Add.

BUG=

Committed: https://crrev.com/591a7ce05b6cbec052126b8b540b7176db455819
Cr-Commit-Position: refs/heads/master@{#41143}

[ivica.bogosavljevic, 2016-11-17 15:24:54]

ivica.bogosavljevic@imgtec.com changed reviewers:
+ dusan.simicic@imgtec.com, ilija.pavlovic.imgtec@gmail.com,
miran.karic@imgtec.com, predrag.rudic@imgtec.com

[ivica.bogosavljevic, 2016-11-17 15:24:54]

PTAL

[Ilija.Pavlovic1, 2016-11-18 07:30:19]

ilija.pavlovic@imgtec.com changed reviewers:
+ Ilija.Pavlovic@imgtec.com

[Ilija.Pavlovic1, 2016-11-18 07:30:19]

lgtm

[miran.karic, 2016-11-18 13:41:47]

miran.karic@imgtec.com changed reviewers:
+ Miran.Karic@imgtec.com, ilija.pavlovic@imgtec.com
- Ilija.Pavlovic@imgtec.com

[miran.karic, 2016-11-18 13:41:47]

lgtm

[ivica.bogosavljevic, 2016-11-21 13:34:43]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[commit-bot: I haz the power, 2016-11-21 13:34:47]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-11-21 14:04:14]

CQ is committing da patch.

Bot data: {"patchset_id": 1, "attempt_start_ts": 1479735283646650, "parent_rev":
["e78299684d8d3d3d7134d2cdb096f2e0121d9a01", null], "commit_rev":
["68771b7bd78e03683797b44a041d77c921967372", null]}

[commit-bot: I haz the power, 2016-11-21 14:04:21]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-11-21 14:04:51]

Description was changed from

==========
MIPS[64]: Disable Add/Shl to Lsa optimization if operand is immediate

Add/Shl to Lsa optimization doesn't yield any performance increase in case
one of the operand is immediate, because Lsa cannot use the immediate so
we use an extra instruction to load the immediate to register. On MIPSR2 and
less this optimization leads to performance degradation, since Lsa is not
supported on these architectures and it is emulated using Add/Shl which
do support immediate as operand for Add.

BUG=
==========

to

==========
MIPS[64]: Disable Add/Shl to Lsa optimization if operand is immediate

Add/Shl to Lsa optimization doesn't yield any performance increase in case
one of the operand is immediate, because Lsa cannot use the immediate so
we use an extra instruction to load the immediate to register. On MIPSR2 and
less this optimization leads to performance degradation, since Lsa is not
supported on these architectures and it is emulated using Add/Shl which
do support immediate as operand for Add.

BUG=

Committed: https://crrev.com/591a7ce05b6cbec052126b8b540b7176db455819
Cr-Commit-Position: refs/heads/master@{#41143}
==========

[commit-bot: I haz the power, 2016-11-21 14:04:52]

Patchset 1 (id:??) landed as
https://crrev.com/591a7ce05b6cbec052126b8b540b7176db455819
Cr-Commit-Position: refs/heads/master@{#41143}