[Subzero][MIPS] Implements atomic intrinsics for MIPS32

src/IceAssemblerMIPS32.cpp

Index: src/IceAssemblerMIPS32.cpp
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp
index c35dff0b672398c642558c4850212da12503fc63..2360b9c7a21b40a4f657d17fa5119d875e38a755 100644
--- a/src/IceAssemblerMIPS32.cpp
+++ b/src/IceAssemblerMIPS32.cpp
@@ -696,6 +696,12 @@ void AssemblerMIPS32::ldc1(const Operand *OpRt, const Operand *OpBase,
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::ll(const Operand *OpRt, const Operand *OpBase,
+                         const uint32_t Offset) {
+  static constexpr IValueT Opcode = 0xC0000000;
+  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "ll");
+}
+
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
   switch (OpRt->getType()) {
@@ -959,6 +965,12 @@ void AssemblerMIPS32::ret(void) {
   nop(); // delay slot
 }
 
+void AssemblerMIPS32::sc(const Operand *OpRt, const Operand *OpBase,
+                         const uint32_t Offset) {
+  static constexpr IValueT Opcode = 0xE0000000;
+  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sc");
+}
+
 void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt,
                           const uint32_t Sa) {
   static constexpr IValueT Opcode = 0x00000000;
@@ -1122,6 +1134,11 @@ void AssemblerMIPS32::swc1(const Operand *OpRt, const Operand *OpBase,
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::sync() {
+  static constexpr IValueT Opcode = 0x0000000f;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::teq(const Operand *OpRs, const Operand *OpRt,
                           const uint32_t TrapCode) {
   IValueT Opcode = 0x00000034;