[Subzero][MIPS] Implements atomic intrinsics for MIPS32

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 157 matching lines @@
   void _and(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32And>(Dest, Src0, Src1);
   }
 
   void _andi(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Andi>(Dest, Src, Imm);
   }
 
   void _br(CfgNode *Target) { Context.insert<InstMIPS32Br>(Target); }
 
+  void _br(CfgNode *Target, const InstMIPS32Label *Label) {
+    Context.insert<InstMIPS32Br>(Target, Label);
+  }
+
   void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0,
            Operand *Src1, CondMIPS32::Cond Condition) {
     Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1,
                                  Condition);
   }
 
   void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0,
            CondMIPS32::Cond Condition) {
     Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition);
   }
@@ skipping 134 matching lines @@
   }
 
   void _divu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Divu>(Dest, Src0, Src1);
   }
 
   void _ldc1(Variable *Value, OperandMIPS32Mem *Mem, RelocOp Reloc = RO_No) {
     Context.insert<InstMIPS32Ldc1>(Value, Mem, Reloc);
   }
 
+  void _ll(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Ll>(Value, Mem);
+  }
+
   void _lw(Variable *Value, OperandMIPS32Mem *Mem) {
     Context.insert<InstMIPS32Lw>(Value, Mem);
   }
 
   void _lwc1(Variable *Value, OperandMIPS32Mem *Mem, RelocOp Reloc = RO_No) {
     Context.insert<InstMIPS32Lwc1>(Value, Mem, Reloc);
   }
 
   void _lui(Variable *Dest, Operand *Src, RelocOp Reloc = RO_No) {
     Context.insert<InstMIPS32Lui>(Dest, Src, Reloc);
@@ skipping 125 matching lines @@
   }
 
   void _or(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Or>(Dest, Src0, Src1);
   }
 
   void _ori(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Ori>(Dest, Src, Imm);
   }
 
+  InstMIPS32Sc *_sc(Variable *Value, OperandMIPS32Mem *Mem) {
+    return Context.insert<InstMIPS32Sc>(Value, Mem);
+  }
+
   void _sdc1(Variable *Value, OperandMIPS32Mem *Mem) {
     Context.insert<InstMIPS32Sdc1>(Value, Mem);
   }
 
   void _sll(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Sll>(Dest, Src, Imm);
   }
 
   void _sllv(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Sllv>(Dest, Src0, Src1);
@@ skipping 56 matching lines @@
   }
 
   void _sw(Variable *Value, OperandMIPS32Mem *Mem) {
     Context.insert<InstMIPS32Sw>(Value, Mem);
   }
 
   void _swc1(Variable *Value, OperandMIPS32Mem *Mem) {
     Context.insert<InstMIPS32Swc1>(Value, Mem);
   }
 
+  void _sync() { Context.insert<InstMIPS32Sync>(); }
+
   void _teq(Variable *Src0, Variable *Src1, uint32_t TrapCode) {
     Context.insert<InstMIPS32Teq>(Src0, Src1, TrapCode);
   }
 
   void _trunc_l_d(Variable *Dest, Variable *Src) {
     Context.insert<InstMIPS32Trunc_l_d>(Dest, Src);
   }
 
   void _trunc_l_s(Variable *Dest, Variable *Src) {
     Context.insert<InstMIPS32Trunc_l_s>(Dest, Src);
@@ skipping 176 matching lines @@
                             Operand *Src0, Operand *Src1);
   void lowerAssign(const InstAssign *Instr) override;
   void lowerBr(const InstBr *Instr) override;
   void lowerBreakpoint(const InstBreakpoint *Instr) override;
   void lowerCall(const InstCall *Instr) override;
   void lowerCast(const InstCast *Instr) override;
   void lowerExtractElement(const InstExtractElement *Instr) override;
   void lowerFcmp(const InstFcmp *Instr) override;
   void lowerIcmp(const InstIcmp *Instr) override;
   void lower64Icmp(const InstIcmp *Instr);
+  void createArithInst(Intrinsics::AtomicRMWOperation Operation, Variable *Dest,
+                       Variable *Src0, Variable *Src1);
   void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override;
   void lowerInsertElement(const InstInsertElement *Instr) override;
   void lowerLoad(const InstLoad *Instr) override;
   void lowerPhi(const InstPhi *Instr) override;
   void lowerRet(const InstRet *Instr) override;
   void lowerSelect(const InstSelect *Instr) override;
   void lowerShuffleVector(const InstShuffleVector *Instr) override;
   void lowerStore(const InstStore *Instr) override;
   void lowerSwitch(const InstSwitch *Instr) override;
   void lowerUnreachable(const InstUnreachable *Instr) override;
@@ skipping 271 matching lines @@
   uint32_t Flags1 = AFL_FLAGS1_ODDSPREG;
   uint32_t Flags2 = AFL_FLAGS2_NONE;
 
   MipsABIFlagsSection() = default;
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H