[Subzero][MIPS] Implements atomic intrinsics for MIPS32

src/IceAssemblerMIPS32.h

 //===- subzero/src/IceAssemblerMIPS32.h - Assembler for MIPS ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 177 matching lines @@
 
   void jal(const ConstantRelocatable *Target);
 
   void jalr(const Operand *OpRs, const Operand *OpRd);
 
   void lui(const Operand *OpRt, const Operand *OpImm, const RelocOp Reloc);
 
   void ldc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
             const RelocOp Reloc);
 
+  void ll(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
+
   void lw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
 
   void lwc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
             const RelocOp Reloc);
 
   void mfc1(const Operand *OpRt, const Operand *OpFs);
 
   void mfhi(const Operand *OpRd);
 
   void mflo(const Operand *OpRd);
@@ skipping 37 matching lines @@
   void multu(const Operand *OpRs, const Operand *OpRt);
 
   void nor(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void or_(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void ori(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void ret(void);
 
+  void sc(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
+
   void sll(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
   void sllv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
 
   void slt(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
@@ skipping 18 matching lines @@
   void subu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void sdc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
             const RelocOp Reloc);
 
   void sw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
 
   void swc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
             const RelocOp Reloc);
 
+  void sync();
+
   void teq(const Operand *OpRs, const Operand *OpRt, const uint32_t TrapCode);
 
   void trunc_l_d(const Operand *OpFd, const Operand *OpFs);
 
   void trunc_l_s(const Operand *OpFd, const Operand *OpFs);
 
   void trunc_w_d(const Operand *OpFd, const Operand *OpFs);
 
   void trunc_w_s(const Operand *OpFd, const Operand *OpFs);
 
@@ skipping 79 matching lines @@
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERMIPS32_H