[Subzero][MIPS] Implements atomic intrinsics for MIPS32

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 678 matching lines @@
   } else {
     llvm::report_fatal_error("ldc1: Invalid 2nd operand");
   }
 
   Opcode |= Base << 21;
   Opcode |= Rt << 16;
   Opcode |= Imm16;
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::ll(const Operand *OpRt, const Operand *OpBase,
+                         const uint32_t Offset) {
+  static constexpr IValueT Opcode = 0xC0000000;
+  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "ll");
+}
+
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
   switch (OpRt->getType()) {
   case IceType_i1:
   case IceType_i8: {
     static constexpr IValueT Opcode = 0x80000000;
     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb");
     break;
   }
   case IceType_i16: {
@@ skipping 243 matching lines @@
   static constexpr IValueT Opcode = 0x34000000;
   emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori");
 }
 
 void AssemblerMIPS32::ret(void) {
   static constexpr IValueT Opcode = 0x03E00008; // JR $31
   emitInst(Opcode);
   nop(); // delay slot
 }
 
+void AssemblerMIPS32::sc(const Operand *OpRt, const Operand *OpBase,
+                         const uint32_t Offset) {
+  static constexpr IValueT Opcode = 0xE0000000;
+  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sc");
+}
+
 void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt,
                           const uint32_t Sa) {
   static constexpr IValueT Opcode = 0x00000000;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll");
 }
 
 void AssemblerMIPS32::sllv(const Operand *OpRd, const Operand *OpRt,
                            const Operand *OpRs) {
   static constexpr IValueT Opcode = 0x00000004;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv");
@@ skipping 143 matching lines @@
   } else {
     llvm::report_fatal_error("swc1: Invalid 2nd operand");
   }
 
   Opcode |= Base << 21;
   Opcode |= Rt << 16;
   Opcode |= Imm16;
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::sync() {
+  IValueT Opcode = 0x0000000f;

[Jim Stichnoth, 2016/11/17 05:35:38]

static constexpr like the others?

[sagar.thakur, 2016/11/17 10:57:28]

Done.

+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::teq(const Operand *OpRs, const Operand *OpRt,
                           const uint32_t TrapCode) {
   IValueT Opcode = 0x00000034;
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", "teq");
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", "teq");
   Opcode |= (TrapCode & 0xFFFFF) << 6;
   Opcode |= Rt << 16;
   Opcode |= Rs << 21;
   emitInst(Opcode);
 }
@@ skipping 99 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice