| Index: runtime/vm/instructions_arm64.cc
|
| diff --git a/runtime/vm/instructions_arm64.cc b/runtime/vm/instructions_arm64.cc
|
| index 0895ae9a5bf517e9401563d111036473c91a233a..b7b26b52b2af72273c01bde8cada3b6697ba57b3 100644
|
| --- a/runtime/vm/instructions_arm64.cc
|
| +++ b/runtime/vm/instructions_arm64.cc
|
| @@ -26,10 +26,8 @@ CallPattern::CallPattern(uword pc, const Code& code)
|
| ASSERT(*(reinterpret_cast<uint32_t*>(end_) - 1) == 0xd63f0200);
|
|
|
| Register reg;
|
| - ic_data_load_end_ =
|
| - InstructionPattern::DecodeLoadWordFromPool(end_ - 2 * Instr::kInstrSize,
|
| - ®,
|
| - &target_code_pool_index_);
|
| + ic_data_load_end_ = InstructionPattern::DecodeLoadWordFromPool(
|
| + end_ - 2 * Instr::kInstrSize, ®, &target_code_pool_index_);
|
| ASSERT(reg == CODE_REG);
|
| }
|
|
|
| @@ -44,13 +42,10 @@ NativeCallPattern::NativeCallPattern(uword pc, const Code& code)
|
| ASSERT(*(reinterpret_cast<uint32_t*>(end_) - 1) == 0xd63f0200);
|
|
|
| Register reg;
|
| - uword native_function_load_end =
|
| - InstructionPattern::DecodeLoadWordFromPool(end_ - 2 * Instr::kInstrSize,
|
| - ®,
|
| - &target_code_pool_index_);
|
| + uword native_function_load_end = InstructionPattern::DecodeLoadWordFromPool(
|
| + end_ - 2 * Instr::kInstrSize, ®, &target_code_pool_index_);
|
| ASSERT(reg == CODE_REG);
|
| - InstructionPattern::DecodeLoadWordFromPool(native_function_load_end,
|
| - ®,
|
| + InstructionPattern::DecodeLoadWordFromPool(native_function_load_end, ®,
|
| &native_function_pool_index_);
|
| ASSERT(reg == R5);
|
| }
|
| @@ -76,7 +71,7 @@ NativeFunction NativeCallPattern::native_function() const {
|
|
|
| void NativeCallPattern::set_native_function(NativeFunction func) const {
|
| object_pool_.SetRawValueAt(native_function_pool_index_,
|
| - reinterpret_cast<uword>(func));
|
| + reinterpret_cast<uword>(func));
|
| }
|
|
|
|
|
| @@ -210,7 +205,7 @@ uword InstructionPattern::DecodeLoadWordFromPool(uword end,
|
|
|
| // Last instruction is always an ldr into a 64-bit X register.
|
| ASSERT(instr->IsLoadStoreRegOp() && (instr->Bit(22) == 1) &&
|
| - (instr->Bits(30, 2) == 3));
|
| + (instr->Bits(30, 2) == 3));
|
|
|
| // Grab the destination register from the ldr instruction.
|
| *reg = instr->RtField();
|
| @@ -261,9 +256,7 @@ uword InstructionPattern::DecodeLoadWordFromPool(uword end,
|
| }
|
|
|
|
|
| -bool DecodeLoadObjectFromPoolOrThread(uword pc,
|
| - const Code& code,
|
| - Object* obj) {
|
| +bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
|
| ASSERT(code.ContainsInstructionAt(pc));
|
|
|
| Instr* instr = Instr::At(pc);
|
| @@ -299,7 +292,7 @@ void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
|
| Instr* instr = Instr::At(start);
|
| const int32_t upper12 = offset & 0x00fff000;
|
| const int32_t lower12 = offset & 0x00000fff;
|
| - ASSERT((offset & 0xff000000) == 0); // Can't encode > 24 bits.
|
| + ASSERT((offset & 0xff000000) == 0); // Can't encode > 24 bits.
|
| ASSERT(((lower12 >> 3) << 3) == lower12); // 8-byte aligned.
|
| instr->SetImm12Bits(instr->InstructionBits(), lower12 >> 3);
|
|
|
| @@ -313,9 +306,7 @@ void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
|
| RawICData* CallPattern::IcData() {
|
| if (ic_data_.IsNull()) {
|
| Register reg;
|
| - InstructionPattern::DecodeLoadObject(ic_data_load_end_,
|
| - object_pool_,
|
| - ®,
|
| + InstructionPattern::DecodeLoadObject(ic_data_load_end_, object_pool_, ®,
|
| &ic_data_);
|
| ASSERT(reg == R5);
|
| }
|
| @@ -344,14 +335,11 @@ SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
|
| ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0200);
|
|
|
| Register reg;
|
| - uword data_load_end =
|
| - InstructionPattern::DecodeLoadWordFromPool(pc - Instr::kInstrSize,
|
| - ®,
|
| - &data_pool_index_);
|
| + uword data_load_end = InstructionPattern::DecodeLoadWordFromPool(
|
| + pc - Instr::kInstrSize, ®, &data_pool_index_);
|
| ASSERT(reg == R5);
|
| InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
|
| - ®,
|
| - &target_pool_index_);
|
| + ®, &target_pool_index_);
|
| ASSERT(reg == CODE_REG);
|
| }
|
|
|
| @@ -362,8 +350,7 @@ RawObject* SwitchableCallPattern::data() const {
|
|
|
|
|
| RawCode* SwitchableCallPattern::target() const {
|
| - return reinterpret_cast<RawCode*>(
|
| - object_pool_.ObjectAt(target_pool_index_));
|
| + return reinterpret_cast<RawCode*>(object_pool_.ObjectAt(target_pool_index_));
|
| }
|
|
|
|
|
| @@ -379,9 +366,7 @@ void SwitchableCallPattern::SetTarget(const Code& target) const {
|
| }
|
|
|
|
|
| -ReturnPattern::ReturnPattern(uword pc)
|
| - : pc_(pc) {
|
| -}
|
| +ReturnPattern::ReturnPattern(uword pc) : pc_(pc) {}
|
|
|
|
|
| bool ReturnPattern::IsValid() const {
|
|
|