| Index: runtime/vm/cpu_test.cc
|
| diff --git a/runtime/vm/cpu_test.cc b/runtime/vm/cpu_test.cc
|
| index 7ffbe6fbac892ceba943b3d2d9222a8f1e977ea1..3b13c0fd981b5f6b875a262acf1adaeea7bcff89 100644
|
| --- a/runtime/vm/cpu_test.cc
|
| +++ b/runtime/vm/cpu_test.cc
|
| @@ -17,19 +17,19 @@ UNIT_TEST_CASE(Id) {
|
| #elif defined(TARGET_ARCH_ARM)
|
| #if defined(HOST_ARCH_ARM)
|
| EXPECT_STREQ("arm", CPU::Id());
|
| -#else // defined(HOST_ARCH_ARM)
|
| +#else // defined(HOST_ARCH_ARM)
|
| EXPECT_STREQ("simarm", CPU::Id());
|
| #endif // defined(HOST_ARCH_ARM)
|
| #elif defined(TARGET_ARCH_ARM64)
|
| #if defined(HOST_ARCH_ARM64)
|
| EXPECT_STREQ("arm64", CPU::Id());
|
| -#else // defined(HOST_ARCH_ARM64)
|
| +#else // defined(HOST_ARCH_ARM64)
|
| EXPECT_STREQ("simarm64", CPU::Id());
|
| #endif // defined(HOST_ARCH_ARM64)
|
| #elif defined(TARGET_ARCH_MIPS)
|
| #if defined(HOST_ARCH_MIPS)
|
| EXPECT_STREQ("mips", CPU::Id());
|
| -#else // defined(HOST_ARCH_MIPS)
|
| +#else // defined(HOST_ARCH_MIPS)
|
| EXPECT_STREQ("simmips", CPU::Id());
|
| #endif // defined(HOST_ARCH_MIPS)
|
| #elif defined(TARGET_ARCH_DBC)
|
|
|