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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 // Declares a Simulator for MIPS instructions if we are not generating a native | 5 // Declares a Simulator for MIPS instructions if we are not generating a native |
6 // MIPS binary. This Simulator allows us to run and debug MIPS code generation | 6 // MIPS binary. This Simulator allows us to run and debug MIPS code generation |
7 // on regular desktop machines. | 7 // on regular desktop machines. |
8 // Dart calls into generated code by "calling" the InvokeDartCode stub, | 8 // Dart calls into generated code by "calling" the InvokeDartCode stub, |
9 // which will start execution in the Simulator or forwards to the real entry | 9 // which will start execution in the Simulator or forwards to the real entry |
10 // on a MIPS HW platform. | 10 // on a MIPS HW platform. |
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51 float get_fregister_float(FRegister freg) const; | 51 float get_fregister_float(FRegister freg) const; |
52 double get_fregister_double(FRegister freg) const; | 52 double get_fregister_double(FRegister freg) const; |
53 int64_t get_fregister_long(FRegister freg) const; | 53 int64_t get_fregister_long(FRegister freg) const; |
54 | 54 |
55 void set_dregister_bits(DRegister freg, int64_t value); | 55 void set_dregister_bits(DRegister freg, int64_t value); |
56 void set_dregister(DRegister freg, double value); | 56 void set_dregister(DRegister freg, double value); |
57 | 57 |
58 int64_t get_dregister_bits(DRegister freg) const; | 58 int64_t get_dregister_bits(DRegister freg) const; |
59 double get_dregister(DRegister freg) const; | 59 double get_dregister(DRegister freg) const; |
60 | 60 |
61 int32_t get_sp() const { | 61 int32_t get_sp() const { return get_register(SPREG); } |
62 return get_register(SPREG); | |
63 } | |
64 | 62 |
65 // Accessor for the pc. | 63 // Accessor for the pc. |
66 void set_pc(int32_t value) { pc_ = value; } | 64 void set_pc(int32_t value) { pc_ = value; } |
67 int32_t get_pc() const { return pc_; } | 65 int32_t get_pc() const { return pc_; } |
68 | 66 |
69 // Accessors for hi, lo registers. | 67 // Accessors for hi, lo registers. |
70 void set_hi_register(int32_t value) { hi_reg_ = value; } | 68 void set_hi_register(int32_t value) { hi_reg_ = value; } |
71 void set_lo_register(int32_t value) { lo_reg_ = value; } | 69 void set_lo_register(int32_t value) { lo_reg_ = value; } |
72 int32_t get_hi_register() const { return hi_reg_; } | 70 int32_t get_hi_register() const { return hi_reg_; } |
73 int32_t get_lo_register() const { return lo_reg_; } | 71 int32_t get_lo_register() const { return lo_reg_; } |
74 | 72 |
75 int32_t get_fcsr_condition_bit(int32_t cc) const { | 73 int32_t get_fcsr_condition_bit(int32_t cc) const { |
76 if (cc == 0) { | 74 if (cc == 0) { |
77 return 23; | 75 return 23; |
78 } else { | 76 } else { |
79 return 24 + cc; | 77 return 24 + cc; |
80 } | 78 } |
81 } | 79 } |
82 | 80 |
83 void set_fcsr_bit(uint32_t cc, bool value) { | 81 void set_fcsr_bit(uint32_t cc, bool value) { |
84 if (value) { | 82 if (value) { |
85 fcsr_ |= (1 << cc); | 83 fcsr_ |= (1 << cc); |
86 } else { | 84 } else { |
87 fcsr_ &= ~(1 << cc); | 85 fcsr_ &= ~(1 << cc); |
88 } | 86 } |
89 } | 87 } |
90 | 88 |
91 bool test_fcsr_bit(uint32_t cc) { | 89 bool test_fcsr_bit(uint32_t cc) { return fcsr_ & (1 << cc); } |
92 return fcsr_ & (1 << cc); | |
93 } | |
94 | 90 |
95 // Accessors to the internal simulator stack base and top. | 91 // Accessors to the internal simulator stack base and top. |
96 uword StackBase() const { return reinterpret_cast<uword>(stack_); } | 92 uword StackBase() const { return reinterpret_cast<uword>(stack_); } |
97 uword StackTop() const; | 93 uword StackTop() const; |
98 | 94 |
99 // Accessor to the instruction counter. | 95 // Accessor to the instruction counter. |
100 uint64_t get_icount() const { return icount_; } | 96 uint64_t get_icount() const { return icount_; } |
101 | 97 |
102 // The thread's top_exit_frame_info refers to a Dart frame in the simulator | 98 // The thread's top_exit_frame_info refers to a Dart frame in the simulator |
103 // stack. The simulator's top_exit_frame_info refers to a C++ frame in the | 99 // stack. The simulator's top_exit_frame_info refers to a C++ frame in the |
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171 uint64_t icount_; | 167 uint64_t icount_; |
172 bool delay_slot_; | 168 bool delay_slot_; |
173 SimulatorSetjmpBuffer* last_setjmp_buffer_; | 169 SimulatorSetjmpBuffer* last_setjmp_buffer_; |
174 uword top_exit_frame_info_; | 170 uword top_exit_frame_info_; |
175 | 171 |
176 // Registered breakpoints. | 172 // Registered breakpoints. |
177 Instr* break_pc_; | 173 Instr* break_pc_; |
178 int32_t break_instr_; | 174 int32_t break_instr_; |
179 | 175 |
180 // Illegal memory access support. | 176 // Illegal memory access support. |
181 static bool IsIllegalAddress(uword addr) { | 177 static bool IsIllegalAddress(uword addr) { return addr < 64 * 1024; } |
182 return addr < 64*1024; | |
183 } | |
184 void HandleIllegalAccess(uword addr, Instr* instr); | 178 void HandleIllegalAccess(uword addr, Instr* instr); |
185 | 179 |
186 // Read and write memory. | 180 // Read and write memory. |
187 void UnalignedAccess(const char* msg, uword addr, Instr* instr); | 181 void UnalignedAccess(const char* msg, uword addr, Instr* instr); |
188 | 182 |
189 // Handles a legal instruction that the simulator does not implement. | 183 // Handles a legal instruction that the simulator does not implement. |
190 void UnimplementedInstruction(Instr* instr); | 184 void UnimplementedInstruction(Instr* instr); |
191 | 185 |
192 void set_pc(uword value) { pc_ = value; } | 186 void set_pc(uword value) { pc_ = value; } |
193 | 187 |
194 void Format(Instr* instr, const char* format); | 188 void Format(Instr* instr, const char* format); |
195 | 189 |
196 inline int8_t ReadB(uword addr); | 190 inline int8_t ReadB(uword addr); |
197 inline uint8_t ReadBU(uword addr); | 191 inline uint8_t ReadBU(uword addr); |
198 inline int16_t ReadH(uword addr, Instr* instr); | 192 inline int16_t ReadH(uword addr, Instr* instr); |
199 inline uint16_t ReadHU(uword addr, Instr *instr); | 193 inline uint16_t ReadHU(uword addr, Instr* instr); |
200 inline intptr_t ReadW(uword addr, Instr* instr); | 194 inline intptr_t ReadW(uword addr, Instr* instr); |
201 | 195 |
202 inline void WriteB(uword addr, uint8_t value); | 196 inline void WriteB(uword addr, uint8_t value); |
203 inline void WriteH(uword addr, uint16_t value, Instr* isntr); | 197 inline void WriteH(uword addr, uint16_t value, Instr* isntr); |
204 inline void WriteW(uword addr, intptr_t value, Instr* instr); | 198 inline void WriteW(uword addr, intptr_t value, Instr* instr); |
205 | 199 |
206 inline double ReadD(uword addr, Instr* instr); | 200 inline double ReadD(uword addr, Instr* instr); |
207 inline void WriteD(uword addr, double value, Instr* instr); | 201 inline void WriteD(uword addr, double value, Instr* instr); |
208 | 202 |
209 // We keep track of 16 exclusive access address tags across all threads. | 203 // We keep track of 16 exclusive access address tags across all threads. |
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231 static void SetExclusiveAccess(uword addr); | 225 static void SetExclusiveAccess(uword addr); |
232 | 226 |
233 // Returns true if the current thread has exclusive access to given address, | 227 // Returns true if the current thread has exclusive access to given address, |
234 // returns false otherwise. In either case, set access to given address to | 228 // returns false otherwise. In either case, set access to given address to |
235 // 'open state' for all threads. | 229 // 'open state' for all threads. |
236 // If given addr is NULL, set access to 'open state' for current | 230 // If given addr is NULL, set access to 'open state' for current |
237 // thread (CLREX). | 231 // thread (CLREX). |
238 static bool HasExclusiveAccessAndOpen(uword addr); | 232 static bool HasExclusiveAccessAndOpen(uword addr); |
239 | 233 |
240 void DoBranch(Instr* instr, bool taken, bool likely); | 234 void DoBranch(Instr* instr, bool taken, bool likely); |
241 void DoBreak(Instr *instr); | 235 void DoBreak(Instr* instr); |
242 | 236 |
243 void DecodeSpecial(Instr* instr); | 237 void DecodeSpecial(Instr* instr); |
244 void DecodeSpecial2(Instr* instr); | 238 void DecodeSpecial2(Instr* instr); |
245 void DecodeRegImm(Instr* instr); | 239 void DecodeRegImm(Instr* instr); |
246 void DecodeCop1(Instr* instr); | 240 void DecodeCop1(Instr* instr); |
247 void InstructionDecode(Instr* instr); | 241 void InstructionDecode(Instr* instr); |
248 | 242 |
249 void Execute(); | 243 void Execute(); |
250 void ExecuteDelaySlot(); | 244 void ExecuteDelaySlot(); |
251 | 245 |
252 // Returns true if tracing of executed instructions is enabled. | 246 // Returns true if tracing of executed instructions is enabled. |
253 bool IsTracingExecution() const; | 247 bool IsTracingExecution() const; |
254 | 248 |
255 // Longjmp support for exceptions. | 249 // Longjmp support for exceptions. |
256 SimulatorSetjmpBuffer* last_setjmp_buffer() { | 250 SimulatorSetjmpBuffer* last_setjmp_buffer() { return last_setjmp_buffer_; } |
257 return last_setjmp_buffer_; | |
258 } | |
259 void set_last_setjmp_buffer(SimulatorSetjmpBuffer* buffer) { | 251 void set_last_setjmp_buffer(SimulatorSetjmpBuffer* buffer) { |
260 last_setjmp_buffer_ = buffer; | 252 last_setjmp_buffer_ = buffer; |
261 } | 253 } |
262 | 254 |
263 friend class SimulatorDebugger; | 255 friend class SimulatorDebugger; |
264 friend class SimulatorSetjmpBuffer; | 256 friend class SimulatorSetjmpBuffer; |
265 DISALLOW_COPY_AND_ASSIGN(Simulator); | 257 DISALLOW_COPY_AND_ASSIGN(Simulator); |
266 }; | 258 }; |
267 | 259 |
268 } // namespace dart | 260 } // namespace dart |
269 | 261 |
270 #endif // RUNTIME_VM_SIMULATOR_MIPS_H_ | 262 #endif // RUNTIME_VM_SIMULATOR_MIPS_H_ |
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