clang-format runtime/vm

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
@@ skipping 51 matching lines @@
 }
 
 
 static intptr_t ToInstructionEnd(intptr_t pos) {
   return (pos | 1);
 }
 
 
 FlowGraphAllocator::FlowGraphAllocator(const FlowGraph& flow_graph,
                                        bool intrinsic_mode)
-  : flow_graph_(flow_graph),
-    reaching_defs_(flow_graph),
-    value_representations_(flow_graph.max_virtual_register_number()),
-    block_order_(flow_graph.reverse_postorder()),
-    postorder_(flow_graph.postorder()),
-    liveness_(flow_graph),
-    vreg_count_(flow_graph.max_virtual_register_number()),
-    live_ranges_(flow_graph.max_virtual_register_number()),
-    cpu_regs_(),
-    fpu_regs_(),
-    blocked_cpu_registers_(),
-    blocked_fpu_registers_(),
-    number_of_registers_(0),
-    registers_(),
-    blocked_registers_(),
-    cpu_spill_slot_count_(0),
-    intrinsic_mode_(intrinsic_mode) {
+    : flow_graph_(flow_graph),
+      reaching_defs_(flow_graph),
+      value_representations_(flow_graph.max_virtual_register_number()),
+      block_order_(flow_graph.reverse_postorder()),
+      postorder_(flow_graph.postorder()),
+      liveness_(flow_graph),
+      vreg_count_(flow_graph.max_virtual_register_number()),
+      live_ranges_(flow_graph.max_virtual_register_number()),
+      cpu_regs_(),
+      fpu_regs_(),
+      blocked_cpu_registers_(),
+      blocked_fpu_registers_(),
+      number_of_registers_(0),
+      registers_(),
+      blocked_registers_(),
+      cpu_spill_slot_count_(0),
+      intrinsic_mode_(intrinsic_mode) {
   for (intptr_t i = 0; i < vreg_count_; i++) {
     live_ranges_.Add(NULL);
   }
   for (intptr_t i = 0; i < vreg_count_; i++) {
     value_representations_.Add(kNoRepresentation);
   }
 
   // All registers are marked as "not blocked" (array initialized to false).
   // Mark the unavailable ones as "blocked" (true).
   for (intptr_t i = 0; i < kNumberOfCpuRegisters; i++) {
@@ skipping 90 matching lines @@
 
         live_in->Add(input->definition()->ssa_temp_index());
         if (input->definition()->HasPairRepresentation()) {
           live_in->Add(ToSecondPairVreg(input->definition()->ssa_temp_index()));
         }
       }
 
       // Add non-argument uses from the deoptimization environment (pushed
       // arguments are not allocated by the register allocator).
       if (current->env() != NULL) {
-        for (Environment::DeepIterator env_it(current->env());
-             !env_it.Done();
+        for (Environment::DeepIterator env_it(current->env()); !env_it.Done();
              env_it.Advance()) {
           Definition* defn = env_it.CurrentValue()->definition();
           if (defn->IsMaterializeObject()) {
             // MaterializeObject instruction is not in the graph.
             // Treat its inputs as part of the environment.
             DeepLiveness(defn->AsMaterializeObject(), live_in);
           } else if (!defn->IsPushArgument() && !defn->IsConstant()) {
             live_in->Add(defn->ssa_temp_index());
             if (defn->HasPairRepresentation()) {
               live_in->Add(ToSecondPairVreg(defn->ssa_temp_index()));
@@ skipping 31 matching lines @@
             const intptr_t second_use = ToSecondPairVreg(use);
             if (!kill_[pred->postorder_number()]->Contains(second_use)) {
               live_in_[pred->postorder_number()]->Add(second_use);
             }
           }
         }
       }
     } else if (block->IsCatchBlockEntry()) {
       // Process initial definitions.
       CatchBlockEntryInstr* catch_entry = block->AsCatchBlockEntry();
-      for (intptr_t i = 0;
-           i < catch_entry->initial_definitions()->length();
+      for (intptr_t i = 0; i < catch_entry->initial_definitions()->length();
            i++) {
         Definition* def = (*catch_entry->initial_definitions())[i];
         const intptr_t vreg = def->ssa_temp_index();
         kill_[catch_entry->postorder_number()]->Add(vreg);
         live_in_[catch_entry->postorder_number()]->Remove(vreg);
       }
     }
   }
 
   // Process initial definitions, ie, constants and incoming parameters.
   for (intptr_t i = 0; i < graph_entry_->initial_definitions()->length(); i++) {
     Definition* def = (*graph_entry_->initial_definitions())[i];
     const intptr_t vreg = def->ssa_temp_index();
     kill_[graph_entry_->postorder_number()]->Add(vreg);
     live_in_[graph_entry_->postorder_number()]->Remove(vreg);
   }
 }
 
 
 UsePosition* LiveRange::AddUse(intptr_t pos, Location* location_slot) {
   ASSERT(location_slot != NULL);
   ASSERT((first_use_interval_->start_ <= pos) &&
          (pos <= first_use_interval_->end_));
   if (uses_ != NULL) {
-    if ((uses_->pos() == pos) &&
-        (uses_->location_slot() == location_slot)) {
+    if ((uses_->pos() == pos) && (uses_->location_slot() == location_slot)) {
       return uses_;
     } else if (uses_->pos() < pos) {
       // If an instruction at position P is using the same value both as
       // a fixed register input and a non-fixed input (in this order) we will
       // add uses both at position P-1 and *then* P which will make
       // uses_ unsorted unless we account for it here.
       UsePosition* insert_after = uses_;
       while ((insert_after->next() != NULL) &&
              (insert_after->next()->pos() < pos)) {
         insert_after = insert_after->next();
@@ skipping 146 matching lines @@
 }
 
 
 // Block location from the start of the instruction to its end.
 void FlowGraphAllocator::BlockLocation(Location loc,
                                        intptr_t from,
                                        intptr_t to) {
   if (loc.IsRegister()) {
     BlockRegisterLocation(loc, from, to, blocked_cpu_registers_, cpu_regs_);
 #if defined(TARGET_ARCH_DBC)
-    last_used_register_ = Utils::Maximum(last_used_register_,
-                                         loc.register_code());
+    last_used_register_ =
+        Utils::Maximum(last_used_register_, loc.register_code());
 #endif
   } else if (loc.IsFpuRegister()) {
     BlockRegisterLocation(loc, from, to, blocked_fpu_registers_, fpu_regs_);
   } else {
     UNREACHABLE();
   }
 }
 
 
 void LiveRange::Print() {
   if (first_use_interval() == NULL) {
     return;
   }
 
-  THR_Print("  live range v%" Pd " [%" Pd ", %" Pd ") in ", vreg(),
-                                                            Start(),
-                                                            End());
+  THR_Print("  live range v%" Pd " [%" Pd ", %" Pd ") in ", vreg(), Start(),
+            End());
   assigned_location().Print();
   if (spill_slot_.HasStackIndex()) {
     intptr_t stack_slot = spill_slot_.stack_index();
     THR_Print(" allocated spill slot: %" Pd "", stack_slot);
   }
   THR_Print("\n");
 
   SafepointPosition* safepoint = first_safepoint();
   while (safepoint != NULL) {
     THR_Print("    Safepoint [%" Pd "]: ", safepoint->pos());
     safepoint->locs()->stack_bitmap()->Print();
     THR_Print("\n");
     safepoint = safepoint->next();
   }
 
   UsePosition* use_pos = uses_;
-  for (UseInterval* interval = first_use_interval_;
-       interval != NULL;
+  for (UseInterval* interval = first_use_interval_; interval != NULL;
        interval = interval->next()) {
-    THR_Print("    use interval [%" Pd ", %" Pd ")\n",
-              interval->start(),
+    THR_Print("    use interval [%" Pd ", %" Pd ")\n", interval->start(),
               interval->end());
     while ((use_pos != NULL) && (use_pos->pos() <= interval->end())) {
       THR_Print("      use at %" Pd "", use_pos->pos());
       if (use_pos->location_slot() != NULL) {
         THR_Print(" as ");
         use_pos->location_slot()->Print();
       }
       THR_Print("\n");
       use_pos = use_pos->next();
     }
@@ skipping 57 matching lines @@
   BitVector* current_interference_set = NULL;
   Zone* zone = flow_graph_.zone();
   for (intptr_t i = 0; i < (block_count - 1); i++) {
     BlockEntryInstr* block = postorder_[i];
 
     BlockInfo* block_info = BlockInfoAt(block->start_pos());
 
     // For every SSA value that is live out of this block, create an interval
     // that covers the whole block.  It will be shortened if we encounter a
     // definition of this value in this block.
-    for (BitVector::Iterator it(liveness_.GetLiveOutSetAt(i));
-         !it.Done();
+    for (BitVector::Iterator it(liveness_.GetLiveOutSetAt(i)); !it.Done();
          it.Advance()) {
       LiveRange* range = GetLiveRange(it.Current());
       range->AddUseInterval(block->start_pos(), block->end_pos());
     }
 
     BlockInfo* loop_header = block_info->loop_header();
     if ((loop_header != NULL) && (loop_header->last_block() == block)) {
-      current_interference_set = new(zone) BitVector(
-          zone, flow_graph_.max_virtual_register_number());
+      current_interference_set =
+          new (zone) BitVector(zone, flow_graph_.max_virtual_register_number());
       ASSERT(loop_header->backedge_interference() == NULL);
       // All values flowing into the loop header are live at the back-edge and
       // can interfere with phi moves.
       current_interference_set->AddAll(
           liveness_.GetLiveInSet(loop_header->entry()));
-      loop_header->set_backedge_interference(
-          current_interference_set);
+      loop_header->set_backedge_interference(current_interference_set);
     }
 
     // Connect outgoing phi-moves that were created in NumberInstructions
     // and find last instruction that contributes to liveness.
-    Instruction* current = ConnectOutgoingPhiMoves(block,
-                                                   current_interference_set);
+    Instruction* current =
+        ConnectOutgoingPhiMoves(block, current_interference_set);
 
     // Now process all instructions in reverse order.
     while (current != block) {
       // Skip parallel moves that we insert while processing instructions.
       if (!current->IsParallelMove()) {
         ProcessOneInstruction(block, current, current_interference_set);
       }
       current = current->previous();
     }
 
 
     // Check if any values live into the loop can be spilled for free.
     if (block_info->is_loop_header()) {
       current_interference_set = NULL;
-      for (BitVector::Iterator it(liveness_.GetLiveInSetAt(i));
-           !it.Done();
+      for (BitVector::Iterator it(liveness_.GetLiveInSetAt(i)); !it.Done();
            it.Advance()) {
         LiveRange* range = GetLiveRange(it.Current());
         if (HasOnlyUnconstrainedUsesInLoop(range, block_info)) {
           range->MarkHasOnlyUnconstrainedUsesInLoop(block_info->loop_id());
         }
       }
     }
 
     if (block->IsJoinEntry()) {
       ConnectIncomingPhiMoves(block->AsJoinEntry());
     } else if (block->IsCatchBlockEntry()) {
       // Process initial definitions.
       CatchBlockEntryInstr* catch_entry = block->AsCatchBlockEntry();
 
       ProcessEnvironmentUses(catch_entry, catch_entry);  // For lazy deopt
 
-      for (intptr_t i = 0;
-           i < catch_entry->initial_definitions()->length();
+      for (intptr_t i = 0; i < catch_entry->initial_definitions()->length();
            i++) {
         Definition* defn = (*catch_entry->initial_definitions())[i];
         LiveRange* range = GetLiveRange(defn->ssa_temp_index());
         range->DefineAt(catch_entry->start_pos());  // Defined at block entry.
         ProcessInitialDefinition(defn, range, catch_entry);
       }
       // Block the two fixed registers used by CatchBlockEntryInstr from the
       // block start to until the end of the instruction so that they are
       // preserved.
       intptr_t start = catch_entry->start_pos();
 #if !defined(TARGET_ARCH_DBC)
       const Register exception_reg = kExceptionObjectReg;
       const Register stacktrace_reg = kStackTraceObjectReg;
 #else
       const intptr_t exception_reg =
           LocalVarIndex(0, catch_entry->exception_var().index());
       const intptr_t stacktrace_reg =
           LocalVarIndex(0, catch_entry->stacktrace_var().index());
 #endif
-      BlockLocation(Location::RegisterLocation(exception_reg),
-                    start,
+      BlockLocation(Location::RegisterLocation(exception_reg), start,
                     ToInstructionEnd(start));
-      BlockLocation(Location::RegisterLocation(stacktrace_reg),
-                    start,
+      BlockLocation(Location::RegisterLocation(stacktrace_reg), start,
                     ToInstructionEnd(start));
     }
   }
 
   // Process incoming parameters and constants.  Do this after all other
   // instructions so that safepoints for all calls have already been found.
   GraphEntryInstr* graph_entry = flow_graph_.graph_entry();
   for (intptr_t i = 0; i < graph_entry->initial_definitions()->length(); i++) {
     Definition* defn = (*graph_entry->initial_definitions())[i];
     ASSERT(!defn->HasPairRepresentation());
@@ skipping 32 matching lines @@
     } else {
       ConstantInstr* constant = defn->AsConstant();
       ASSERT(constant != NULL);
       range->set_assigned_location(Location::Constant(constant));
       range->set_spill_slot(Location::Constant(constant));
       AssignSafepoints(defn, range);
       range->finger()->Initialize(range);
       UsePosition* use =
           range->finger()->FirstRegisterBeneficialUse(block->start_pos());
       if (use != NULL) {
-        LiveRange* tail =
-            SplitBetween(range, block->start_pos(), use->pos());
+        LiveRange* tail = SplitBetween(range, block->start_pos(), use->pos());
         // Parameters and constants are tagged, so allocated to CPU registers.
         ASSERT(constant->representation() == kTagged);
         CompleteRange(tail, Location::kRegister);
       }
       ConvertAllUses(range);
     }
     return;
   }
 #endif
 
@@ skipping 17 matching lines @@
     ASSERT(param->base_reg() == FPREG);
     if (slot_index >= 0) {
       AssignSafepoints(defn, range);
       range->finger()->Initialize(range);
       range->set_assigned_location(Location::RegisterLocation(slot_index));
       SplitInitialDefinitionAt(range, kNormalEntryPos);
       ConvertAllUses(range);
       return;
     }
 #endif  // defined(TARGET_ARCH_DBC)
-    range->set_assigned_location(Location::StackSlot(slot_index,
-                                                     param->base_reg()));
-    range->set_spill_slot(Location::StackSlot(slot_index,
-                                              param->base_reg()));
+    range->set_assigned_location(
+        Location::StackSlot(slot_index, param->base_reg()));
+    range->set_spill_slot(Location::StackSlot(slot_index, param->base_reg()));
 
   } else if (defn->IsCurrentContext()) {
 #if !defined(TARGET_ARCH_DBC)
     const Register context_reg = CTX;
 #else
     const intptr_t context_reg = flow_graph_.num_copied_params();
 #endif
 
     AssignSafepoints(defn, range);
     range->finger()->Initialize(range);
     range->set_assigned_location(Location::RegisterLocation(context_reg));
     if (range->End() > kNormalEntryPos) {
       LiveRange* tail = range->SplitAt(kNormalEntryPos);
       CompleteRange(tail, Location::kRegister);
     }
     ConvertAllUses(range);
     return;
   } else {
     ConstantInstr* constant = defn->AsConstant();
     ASSERT(constant != NULL);
     range->set_assigned_location(Location::Constant(constant));
     range->set_spill_slot(Location::Constant(constant));
   }
   AssignSafepoints(defn, range);
   range->finger()->Initialize(range);
   UsePosition* use =
       range->finger()->FirstRegisterBeneficialUse(block->start_pos());
   if (use != NULL) {
-    LiveRange* tail =
-        SplitBetween(range, block->start_pos(), use->pos());
+    LiveRange* tail = SplitBetween(range, block->start_pos(), use->pos());
     // Parameters and constants are tagged, so allocated to CPU registers.
     CompleteRange(tail, Location::kRegister);
   }
   ConvertAllUses(range);
   if (defn->IsParameter() && (range->spill_slot().stack_index() >= 0)) {
     // Parameters above the frame pointer consume spill slots and are marked
     // in stack maps.
     spill_slots_.Add(range_end);
     quad_spill_slots_.Add(false);
     untagged_spill_slots_.Add(false);
@@ skipping 55 matching lines @@
 //
 //           i  i'
 //  value  --*--)
 //
 // can be read as: use interval for value starts somewhere before instruction
 // and extends until currently processed instruction, there is a use of value
 // at the start of the instruction.
 //
 
 Instruction* FlowGraphAllocator::ConnectOutgoingPhiMoves(
-    BlockEntryInstr* block, BitVector* interfere_at_backedge) {
+    BlockEntryInstr* block,
+    BitVector* interfere_at_backedge) {
   Instruction* last = block->last_instruction();
 
   GotoInstr* goto_instr = last->AsGoto();
   if (goto_instr == NULL) return last;
 
   // If we have a parallel move here then the successor block must be a
   // join with phis.  The phi inputs contribute uses to each predecessor
   // block (and the phi outputs contribute definitions in the successor
   // block).
   if (!goto_instr->HasParallelMove()) return goto_instr->previous();
@@ skipping 26 matching lines @@
     //
     //                 g  g'
     //      value    --*
     //
     intptr_t vreg = val->definition()->ssa_temp_index();
     LiveRange* range = GetLiveRange(vreg);
     if (interfere_at_backedge != NULL) interfere_at_backedge->Add(vreg);
 
     range->AddUseInterval(block->start_pos(), pos);
     range->AddHintedUse(
-        pos,
-        move->src_slot(),
+        pos, move->src_slot(),
         GetLiveRange(phi->ssa_temp_index())->assigned_location_slot());
     move->set_src(Location::PrefersRegister());
 
     if (val->definition()->HasPairRepresentation()) {
       move = parallel_move->MoveOperandsAt(move_index++);
       vreg = ToSecondPairVreg(vreg);
       range = GetLiveRange(vreg);
       if (interfere_at_backedge != NULL) {
         interfere_at_backedge->Add(vreg);
       }
       range->AddUseInterval(block->start_pos(), pos);
-      range->AddHintedUse(
-          pos,
-          move->src_slot(),
-          GetLiveRange(ToSecondPairVreg(
-              phi->ssa_temp_index()))->assigned_location_slot());
+      range->AddHintedUse(pos, move->src_slot(),
+                          GetLiveRange(ToSecondPairVreg(phi->ssa_temp_index()))
+                              ->assigned_location_slot());
       move->set_src(Location::PrefersRegister());
     }
   }
 
   // Begin backward iteration with the instruction before the parallel
   // move.
   return goto_instr->previous();
 }
 
 
@@ skipping 117 matching lines @@
         PairLocation* location_pair = locations[i].AsPairLocation();
         {
           // First live range.
           LiveRange* range = GetLiveRange(def->ssa_temp_index());
           range->AddUseInterval(block_start_pos, use_pos);
           range->AddUse(use_pos, location_pair->SlotAt(0));
         }
         {
           // Second live range.
           LiveRange* range =
-            GetLiveRange(ToSecondPairVreg(def->ssa_temp_index()));
+              GetLiveRange(ToSecondPairVreg(def->ssa_temp_index()));
           range->AddUseInterval(block_start_pos, use_pos);
           range->AddUse(use_pos, location_pair->SlotAt(1));
         }
       } else {
         LiveRange* range = GetLiveRange(def->ssa_temp_index());
         range->AddUseInterval(block_start_pos, use_pos);
         range->AddUse(use_pos, &locations[i]);
       }
     }
 
@@ skipping 38 matching lines @@
       }
       {
         // Second live range.
         LiveRange* range =
             GetLiveRange(ToSecondPairVreg(def->ssa_temp_index()));
         range->AddUseInterval(block_start_pos, use_pos);
         range->AddUse(use_pos, location_pair->SlotAt(1));
       }
     } else if (def->IsMaterializeObject()) {
       locations[i] = Location::NoLocation();
-      ProcessMaterializationUses(
-          block, block_start_pos, use_pos, def->AsMaterializeObject());
+      ProcessMaterializationUses(block, block_start_pos, use_pos,
+                                 def->AsMaterializeObject());
     } else {
       locations[i] = Location::Any();
       LiveRange* range = GetLiveRange(def->ssa_temp_index());
       range->AddUseInterval(block_start_pos, use_pos);
       range->AddUse(use_pos, &locations[i]);
     }
   }
 }
 
 
@@ skipping 12 matching lines @@
     // Input is expected in a fixed register. Expected shape of
     // live ranges:
     //
     //                 j' i  i'
     //      value    --*
     //      register   [-----)
     //
     if (live_registers != NULL) {
       live_registers->Add(*in_ref, range->representation());
     }
-    MoveOperands* move =
-        AddMoveAt(pos - 1, *in_ref, Location::Any());
+    MoveOperands* move = AddMoveAt(pos - 1, *in_ref, Location::Any());
     BlockLocation(*in_ref, pos - 1, pos + 1);
     range->AddUseInterval(block->start_pos(), pos - 1);
     range->AddHintedUse(pos - 1, move->src_slot(), in_ref);
   } else if (in_ref->IsUnallocated()) {
     if (in_ref->policy() == Location::kWritableRegister) {
       // Writable unallocated input. Expected shape of
       // live ranges:
       //
       //                 i  i'
       //      value    --*
       //      temp       [--)
-      MoveOperands* move = AddMoveAt(pos,
-                                     Location::RequiresRegister(),
+      MoveOperands* move = AddMoveAt(pos, Location::RequiresRegister(),
                                      Location::PrefersRegister());
 
       // Add uses to the live range of the input.
       range->AddUseInterval(block->start_pos(), pos);
       range->AddUse(pos, move->src_slot());
 
       // Create live range for the temporary.
       LiveRange* temp = MakeLiveRangeForTemporary();
       temp->AddUseInterval(pos, pos + 1);
       temp->AddHintedUse(pos, in_ref, move->src_slot());
@@ skipping 24 matching lines @@
                                           bool output_same_as_first_input,
                                           Location* in_ref,
                                           Definition* input,
                                           intptr_t input_vreg,
                                           BitVector* interference_set) {
   ASSERT(out != NULL);
   ASSERT(!out->IsPairLocation());
   ASSERT(def != NULL);
   ASSERT(block != NULL);
 
-  LiveRange* range = vreg >= 0 ?
-      GetLiveRange(vreg) : MakeLiveRangeForTemporary();
+  LiveRange* range =
+      vreg >= 0 ? GetLiveRange(vreg) : MakeLiveRangeForTemporary();
 
   // Process output and finalize its liverange.
   if (out->IsMachineRegister()) {
     // Fixed output location. Expected shape of live range:
     //
     //                    i  i' j  j'
     //    register        [--)
     //    output             [-------
     //
     BlockLocation(*out, pos, pos + 1);
@@ skipping 31 matching lines @@
     // start. Expected shape of live ranges:
     //
     //                 i  i'
     //    input #0   --*
     //    output       [----
     //
     ASSERT(in_ref->Equals(Location::RequiresRegister()) ||
            in_ref->Equals(Location::RequiresFpuRegister()));
     *out = *in_ref;
     // Create move that will copy value between input and output.
-    MoveOperands* move = AddMoveAt(pos,
-                                   Location::RequiresRegister(),
-                                   Location::Any());
+    MoveOperands* move =
+        AddMoveAt(pos, Location::RequiresRegister(), Location::Any());
 
     // Add uses to the live range of the input.
     LiveRange* input_range = GetLiveRange(input_vreg);
     input_range->AddUseInterval(block->start_pos(), pos);
     input_range->AddUse(pos, move->src_slot());
 
     // Shorten output live range to the point of definition and add both input
     // and output uses slots to be filled by allocator.
     range->DefineAt(pos);
     range->AddHintedUse(pos, out, move->src_slot());
     range->AddUse(pos, move->dest_slot());
     range->AddUse(pos, in_ref);
 
-    if ((interference_set != NULL) &&
-        (range->vreg() >= 0) &&
+    if ((interference_set != NULL) && (range->vreg() >= 0) &&
         interference_set->Contains(range->vreg())) {
       interference_set->Add(input->ssa_temp_index());
     }
   } else {
     // Normal unallocated location that requires a register. Expected shape of
     // live range:
     //
     //                    i  i'
     //    output          [-------
     //
@@ skipping 14 matching lines @@
 // Create and update live ranges corresponding to instruction's inputs,
 // temporaries and output.
 void FlowGraphAllocator::ProcessOneInstruction(BlockEntryInstr* block,
                                                Instruction* current,
                                                BitVector* interference_set) {
   LocationSummary* locs = current->locs();
 
   Definition* def = current->AsDefinition();
   if ((def != NULL) && (def->AsConstant() != NULL)) {
     ASSERT(!def->HasPairRepresentation());
-    LiveRange* range = (def->ssa_temp_index() != -1) ?
-        GetLiveRange(def->ssa_temp_index()) : NULL;
+    LiveRange* range = (def->ssa_temp_index() != -1)
+                           ? GetLiveRange(def->ssa_temp_index())
+                           : NULL;
 
     // Drop definitions of constants that have no uses.
     if ((range == NULL) || (range->first_use() == NULL)) {
       locs->set_out(0, Location::NoLocation());
       return;
     }
 
     // If this constant has only unconstrained uses convert them all
     // to use the constant directly and drop this definition.
     // TODO(vegorov): improve allocation when we have enough registers to keep
@@ skipping 45 matching lines @@
                                     Location::RequiresRegister()));
   }
   // Add uses from the deoptimization environment.
   if (current->env() != NULL) ProcessEnvironmentUses(block, current);
 
   // Process inputs.
   // Skip the first input if output is specified with kSameAsFirstInput policy,
   // they will be processed together at the very end.
   {
     for (intptr_t j = output_same_as_first_input ? 1 : 0;
-         j < locs->input_count();
-         j++) {
+         j < locs->input_count(); j++) {
       // Determine if we are dealing with a value pair, and if so, whether
       // the location is the first register or second register.
       Value* input = current->InputAt(j);
       Location* in_ref = locs->in_slot(j);
       RegisterSet* live_registers = NULL;
       if (locs->HasCallOnSlowPath()) {
         live_registers = locs->live_registers();
       }
       if (in_ref->IsPairLocation()) {
         ASSERT(input->definition()->HasPairRepresentation());
         PairLocation* pair = in_ref->AsPairLocation();
         const intptr_t vreg = input->definition()->ssa_temp_index();
         // Each element of the pair is assigned it's own virtual register number
         // and is allocated its own LiveRange.
-        ProcessOneInput(block, pos, pair->SlotAt(0),
-                        input, vreg, live_registers);
+        ProcessOneInput(block, pos, pair->SlotAt(0), input, vreg,
+                        live_registers);
         ProcessOneInput(block, pos, pair->SlotAt(1), input,
                         ToSecondPairVreg(vreg), live_registers);
       } else {
         ProcessOneInput(block, pos, in_ref, input,
                         input->definition()->ssa_temp_index(), live_registers);
       }
     }
   }
 
   // Process temps.
@@ skipping 12 matching lines @@
     } else if (temp.IsUnallocated()) {
       LiveRange* range = MakeLiveRangeForTemporary();
       range->AddUseInterval(pos, pos + 1);
       range->AddUse(pos, locs->temp_slot(j));
       CompleteRange(range, RegisterKindFromPolicy(temp));
     } else {
       UNREACHABLE();
     }
   }
 
-  // Block all allocatable registers for calls.
-  // Note that on DBC registers are always essentially spilled so
-  // we don't need to block anything.
+// Block all allocatable registers for calls.
+// Note that on DBC registers are always essentially spilled so
+// we don't need to block anything.
 #if !defined(TARGET_ARCH_DBC)
   if (locs->always_calls()) {
     // Expected shape of live range:
     //
     //              i  i'
     //              [--)
     //
     // The stack bitmap describes the position i.
     for (intptr_t reg = 0; reg < kNumberOfCpuRegisters; reg++) {
-      BlockLocation(Location::RegisterLocation(static_cast<Register>(reg)),
-                    pos,
+      BlockLocation(Location::RegisterLocation(static_cast<Register>(reg)), pos,
                     pos + 1);
     }
 
     for (intptr_t reg = 0; reg < kNumberOfFpuRegisters; reg++) {
       BlockLocation(
-          Location::FpuRegisterLocation(static_cast<FpuRegister>(reg)),
-          pos,
+          Location::FpuRegisterLocation(static_cast<FpuRegister>(reg)), pos,
           pos + 1);
     }
 
 
 #if defined(DEBUG)
     // Verify that temps, inputs and output were specified as fixed
     // locations.  Every register is blocked now so attempt to
     // allocate will not succeed.
     for (intptr_t j = 0; j < locs->temp_count(); j++) {
       ASSERT(!locs->temp(j).IsPairLocation());
@@ skipping 40 matching lines @@
   if (out->IsPairLocation()) {
     ASSERT(def->HasPairRepresentation());
     PairLocation* pair = out->AsPairLocation();
     if (output_same_as_first_input) {
       ASSERT(locs->in_slot(0)->IsPairLocation());
       PairLocation* in_pair = locs->in_slot(0)->AsPairLocation();
       Definition* input = current->InputAt(0)->definition();
       ASSERT(input->HasPairRepresentation());
       // Each element of the pair is assigned it's own virtual register number
       // and is allocated its own LiveRange.
-      ProcessOneOutput(block, pos,  // BlockEntry, seq.
-                       pair->SlotAt(0), def,  // (output) Location, Definition.
+      ProcessOneOutput(block, pos,             // BlockEntry, seq.
+                       pair->SlotAt(0), def,   // (output) Location, Definition.
                        def->ssa_temp_index(),  // (output) virtual register.
-                       true,  // output mapped to first input.
+                       true,                   // output mapped to first input.
                        in_pair->SlotAt(0), input,  // (input) Location, Def.
-                       input->ssa_temp_index(),  // (input) virtual register.
+                       input->ssa_temp_index(),    // (input) virtual register.
                        interference_set);
-      ProcessOneOutput(block, pos,
-                       pair->SlotAt(1), def,
-                       ToSecondPairVreg(def->ssa_temp_index()),
-                       true,
-                       in_pair->SlotAt(1), input,
-                       ToSecondPairVreg(input->ssa_temp_index()),
-                       interference_set);
+      ProcessOneOutput(
+          block, pos, pair->SlotAt(1), def,
+          ToSecondPairVreg(def->ssa_temp_index()), true, in_pair->SlotAt(1),
+          input, ToSecondPairVreg(input->ssa_temp_index()), interference_set);
     } else {
       // Each element of the pair is assigned it's own virtual register number
       // and is allocated its own LiveRange.
-      ProcessOneOutput(block, pos,
-                       pair->SlotAt(0), def,
-                       def->ssa_temp_index(),
-                       false,            // output is not mapped to first input.
-                       NULL, NULL, -1,   // First input not needed.
+      ProcessOneOutput(block, pos, pair->SlotAt(0), def, def->ssa_temp_index(),
+                       false,           // output is not mapped to first input.
+                       NULL, NULL, -1,  // First input not needed.
                        interference_set);
-      ProcessOneOutput(block, pos,
-                       pair->SlotAt(1), def,
-                       ToSecondPairVreg(def->ssa_temp_index()),
-                       false,
-                       NULL, NULL, -1,
-                       interference_set);
+      ProcessOneOutput(block, pos, pair->SlotAt(1), def,
+                       ToSecondPairVreg(def->ssa_temp_index()), false, NULL,
+                       NULL, -1, interference_set);
     }
   } else {
     if (output_same_as_first_input) {
       Location* in_ref = locs->in_slot(0);
       Definition* input = current->InputAt(0)->definition();
       ASSERT(!in_ref->IsPairLocation());
-      ProcessOneOutput(block, pos,  // BlockEntry, Instruction, seq.
-                       out, def,  // (output) Location, Definition.
+      ProcessOneOutput(block, pos,             // BlockEntry, Instruction, seq.
+                       out, def,               // (output) Location, Definition.
                        def->ssa_temp_index(),  // (output) virtual register.
-                       true,  // output mapped to first input.
-                       in_ref, input,  // (input) Location, Def.
+                       true,                   // output mapped to first input.
+                       in_ref, input,          // (input) Location, Def.
                        input->ssa_temp_index(),  // (input) virtual register.
                        interference_set);
     } else {
-      ProcessOneOutput(block, pos,
-                       out, def,
-                       def->ssa_temp_index(),
-                       false,            // output is not mapped to first input.
-                       NULL, NULL, -1,   // First input not needed.
+      ProcessOneOutput(block, pos, out, def, def->ssa_temp_index(),
+                       false,           // output is not mapped to first input.
+                       NULL, NULL, -1,  // First input not needed.
                        interference_set);
     }
   }
 }
 
 
 static ParallelMoveInstr* CreateParallelMoveBefore(Instruction* instr,
                                                    intptr_t pos) {
   ASSERT(pos > 0);
   Instruction* prev = instr->previous();
@@ skipping 100 matching lines @@
     GotoInstr* goto_instr = block->last_instruction()->AsGoto();
     if (goto_instr != NULL) {
       JoinEntryInstr* successor = goto_instr->successor();
       if (successor->postorder_number() > i) {
         // This is back-edge.
         BlockInfo* successor_info = BlockInfoAt(successor->lifetime_position());
         ASSERT(successor_info->entry() == successor);
         if (!successor_info->is_loop_header() &&
             ((current_loop == NULL) ||
              (current_loop->entry()->postorder_number() >
-                  successor_info->entry()->postorder_number()))) {
+              successor_info->entry()->postorder_number()))) {
           ASSERT(successor_info != current_loop);
 
           successor_info->mark_loop_header();
           successor_info->set_loop_id(loop_id++);
           successor_info->set_last_block(block);
           // For loop header loop information points to the outer loop.
           successor_info->set_loop(current_loop);
           current_loop = successor_info;
         }
       }
@@ skipping 30 matching lines @@
 void AllocationFinger::Initialize(LiveRange* range) {
   first_pending_use_interval_ = range->first_use_interval();
   first_register_use_ = range->first_use();
   first_register_beneficial_use_ = range->first_use();
   first_hinted_use_ = range->first_use();
 }
 
 
 bool AllocationFinger::Advance(const intptr_t start) {
   UseInterval* a = first_pending_use_interval_;
-  while (a != NULL && a->end() <= start) a = a->next();
+  while (a != NULL && a->end() <= start)
+    a = a->next();
   first_pending_use_interval_ = a;
   return (first_pending_use_interval_ == NULL);
 }
 
 
 Location AllocationFinger::FirstHint() {
   UsePosition* use = first_hinted_use_;
 
   while (use != NULL) {
     if (use->HasHint()) return use->hint();
     use = use->next();
   }
 
   return Location::NoLocation();
 }
 
 
 static UsePosition* FirstUseAfter(UsePosition* use, intptr_t after) {
   while ((use != NULL) && (use->pos() < after)) {
     use = use->next();
   }
   return use;
 }
 
 
 UsePosition* AllocationFinger::FirstRegisterUse(intptr_t after) {
   for (UsePosition* use = FirstUseAfter(first_register_use_, after);
-       use != NULL;
-       use = use->next()) {
+       use != NULL; use = use->next()) {
     Location* loc = use->location_slot();
     if (loc->IsUnallocated() &&
         ((loc->policy() == Location::kRequiresRegister) ||
-        (loc->policy() == Location::kRequiresFpuRegister))) {
+         (loc->policy() == Location::kRequiresFpuRegister))) {
       first_register_use_ = use;
       return use;
     }
   }
   return NULL;
 }
 
 
 UsePosition* AllocationFinger::FirstRegisterBeneficialUse(intptr_t after) {
   for (UsePosition* use = FirstUseAfter(first_register_beneficial_use_, after);
-       use != NULL;
-       use = use->next()) {
+       use != NULL; use = use->next()) {
     Location* loc = use->location_slot();
     if (loc->IsUnallocated() && loc->IsRegisterBeneficial()) {
       first_register_beneficial_use_ = use;
       return use;
     }
   }
   return NULL;
 }
 
 
@@ skipping 39 matching lines @@
       a = a->next();
     } else {
       u = u->next();
     }
   }
 
   return kMaxPosition;
 }
 
 
-template<typename PositionType>
+template <typename PositionType>
 PositionType* SplitListOfPositions(PositionType** head,
                                    intptr_t split_pos,
                                    bool split_at_start) {
   PositionType* last_before_split = NULL;
   PositionType* pos = *head;
   if (split_at_start) {
     while ((pos != NULL) && (pos->pos() < split_pos)) {
       last_before_split = pos;
       pos = pos->next();
     }
@@ skipping 32 matching lines @@
   UseInterval* last_before_split = NULL;
   while (interval->end() <= split_pos) {
     last_before_split = interval;
     interval = interval->next();
   }
 
   const bool split_at_start = (interval->start() == split_pos);
 
   UseInterval* first_after_split = interval;
   if (!split_at_start && interval->Contains(split_pos)) {
-    first_after_split = new UseInterval(split_pos,
-                                        interval->end(),
-                                        interval->next());
+    first_after_split =
+        new UseInterval(split_pos, interval->end(), interval->next());
     interval->end_ = split_pos;
     interval->next_ = first_after_split;
     last_before_split = interval;
   }
 
   ASSERT(last_before_split != NULL);
   ASSERT(last_before_split->next() == first_after_split);
   ASSERT(last_before_split->end() <= split_pos);
   ASSERT(split_pos <= first_after_split->start());
 
   UsePosition* first_use_after_split =
       SplitListOfPositions(&uses_, split_pos, split_at_start);
 
   SafepointPosition* first_safepoint_after_split =
       SplitListOfPositions(&first_safepoint_, split_pos, split_at_start);
 
-  UseInterval* last_use_interval = (last_before_split == last_use_interval_) ?
-    first_after_split : last_use_interval_;
-  next_sibling_ = new LiveRange(vreg(),
-                                representation(),
-                                first_use_after_split,
-                                first_after_split,
-                                last_use_interval,
-                                first_safepoint_after_split,
-                                next_sibling_);
+  UseInterval* last_use_interval = (last_before_split == last_use_interval_)
+                                       ? first_after_split
+                                       : last_use_interval_;
+  next_sibling_ = new LiveRange(vreg(), representation(), first_use_after_split,
+                                first_after_split, last_use_interval,
+                                first_safepoint_after_split, next_sibling_);
 
   TRACE_ALLOC(THR_Print("  split sibling [%" Pd ", %" Pd ")\n",
                         next_sibling_->Start(), next_sibling_->End()));
 
   last_use_interval_ = last_before_split;
   last_use_interval_->next_ = NULL;
 
   if (first_use_after_split != NULL) {
     finger_.UpdateAfterSplit(first_use_after_split->pos());
   }
 
   return next_sibling_;
 }
 
 
 LiveRange* FlowGraphAllocator::SplitBetween(LiveRange* range,
                                             intptr_t from,
                                             intptr_t to) {
-  TRACE_ALLOC(THR_Print("split v%" Pd " [%" Pd ", %" Pd
-                        ") between [%" Pd ", %" Pd ")\n",
+  TRACE_ALLOC(THR_Print("split v%" Pd " [%" Pd ", %" Pd ") between [%" Pd
+                        ", %" Pd ")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
 
   intptr_t split_pos = kIllegalPosition;
 
   BlockInfo* split_block = BlockInfoAt(to);
   if (from < split_block->entry()->lifetime_position()) {
     // Interval [from, to) spans multiple blocks.
 
     // If last block is inside a loop prefer splitting at outermost loop's
     // header.
@@ skipping 50 matching lines @@
   // be moved outside.
   BlockInfo* block_info = BlockInfoAt(from);
   if (block_info->is_loop_header() || (block_info->loop() != NULL)) {
     BlockInfo* loop_header =
         block_info->is_loop_header() ? block_info : block_info->loop();
 
     if ((range->Start() <= loop_header->entry()->start_pos()) &&
         RangeHasOnlyUnconstrainedUsesInLoop(range, loop_header->loop_id())) {
       ASSERT(loop_header->entry()->start_pos() <= from);
       from = loop_header->entry()->start_pos();
-      TRACE_ALLOC(THR_Print("  moved spill position to loop header %" Pd "\n",
-                            from));
+      TRACE_ALLOC(
+          THR_Print("  moved spill position to loop header %" Pd "\n", from));
     }
   }
 
   LiveRange* tail = range->SplitAt(from);
   Spill(tail);
 }
 
 
 void FlowGraphAllocator::AllocateSpillSlotFor(LiveRange* range) {
 #if defined(TARGET_ARCH_DBC)
@@ skipping 15 matching lines @@
   const intptr_t start = range->Start();
   const intptr_t end = last_sibling->End();
 
   // During fpu register allocation spill slot indices are computed in terms of
   // double (64bit) stack slots. We treat quad stack slot (128bit) as a
   // consecutive pair of two double spill slots.
   // Special care is taken to never allocate the same index to both
   // double and quad spill slots as it complicates disambiguation during
   // parallel move resolution.
   const bool need_quad = (register_kind_ == Location::kFpuRegister) &&
-      ((range->representation() == kUnboxedFloat32x4) ||
-       (range->representation() == kUnboxedInt32x4)   ||
-       (range->representation() == kUnboxedFloat64x2));
+                         ((range->representation() == kUnboxedFloat32x4) ||
+                          (range->representation() == kUnboxedInt32x4) ||
+                          (range->representation() == kUnboxedFloat64x2));
   const bool need_untagged = (register_kind_ == Location::kRegister) &&
-      ((range->representation() == kUntagged));
+                             ((range->representation() == kUntagged));
 
   // Search for a free spill slot among allocated: the value in it should be
   // dead and its type should match (e.g. it should not be a part of the quad if
   // we are allocating normal double slot).
   // For CPU registers we need to take reserved slots for try-catch into
   // account.
   intptr_t idx = register_kind_ == Location::kRegister
-      ? flow_graph_.graph_entry()->fixed_slot_count()
-      : 0;
+                     ? flow_graph_.graph_entry()->fixed_slot_count()
+                     : 0;
   for (; idx < spill_slots_.length(); idx++) {
     if ((need_quad == quad_spill_slots_[idx]) &&
         (need_untagged == untagged_spill_slots_[idx]) &&
         (spill_slots_[idx] <= start)) {
       break;
     }
   }
 
   if (idx == spill_slots_.length()) {
     // No free spill slot found. Allocate a new one.
@@ skipping 17 matching lines @@
     ASSERT(!quad_spill_slots_[idx]);
   }
 
   // Assign spill slot to the range.
   if (register_kind_ == Location::kRegister) {
     range->set_spill_slot(Location::StackSlot(idx));
   } else {
     // We use the index of the slot with the lowest address as an index for the
     // FPU register spill slot. In terms of indexes this relation is inverted:
     // so we have to take the highest index.
-    const intptr_t slot_idx = cpu_spill_slot_count_ +
-        idx * kDoubleSpillFactor + (kDoubleSpillFactor - 1);
+    const intptr_t slot_idx = cpu_spill_slot_count_ + idx * kDoubleSpillFactor +
+                              (kDoubleSpillFactor - 1);
 
     Location location;
     if ((range->representation() == kUnboxedFloat32x4) ||
         (range->representation() == kUnboxedInt32x4) ||
         (range->representation() == kUnboxedFloat64x2)) {
       ASSERT(need_quad);
       location = Location::QuadStackSlot(slot_idx);
     } else {
       ASSERT((range->representation() == kUnboxedDouble));
       location = Location::DoubleStackSlot(slot_idx);
     }
     range->set_spill_slot(location);
   }
 
   spilled_.Add(range);
 }
 
 
 void FlowGraphAllocator::MarkAsObjectAtSafepoints(LiveRange* range) {
   intptr_t stack_index = range->spill_slot().stack_index();
   ASSERT(stack_index >= 0);
 
   while (range != NULL) {
     for (SafepointPosition* safepoint = range->first_safepoint();
-         safepoint != NULL;
-         safepoint = safepoint->next()) {
+         safepoint != NULL; safepoint = safepoint->next()) {
       // Mark the stack slot as having an object.
       safepoint->locs()->SetStackBit(stack_index);
     }
     range = range->next_sibling();
   }
 }
 
 
 void FlowGraphAllocator::Spill(LiveRange* range) {
   LiveRange* parent = GetLiveRange(range->vreg());
   if (parent->spill_slot().IsInvalid()) {
     AllocateSpillSlotFor(parent);
     if (range->representation() == kTagged) {
       MarkAsObjectAtSafepoints(parent);
     }
   }
   range->set_assigned_location(parent->spill_slot());
   ConvertAllUses(range);
 }
 
 
 intptr_t FlowGraphAllocator::FirstIntersectionWithAllocated(
-    intptr_t reg, LiveRange* unallocated) {
+    intptr_t reg,
+    LiveRange* unallocated) {
   intptr_t intersection = kMaxPosition;
   for (intptr_t i = 0; i < registers_[reg]->length(); i++) {
     LiveRange* allocated = (*registers_[reg])[i];
     if (allocated == NULL) continue;
 
     UseInterval* allocated_head =
         allocated->finger()->first_pending_use_interval();
     if (allocated_head->start() >= intersection) continue;
 
     const intptr_t pos = FirstIntersection(
-        unallocated->finger()->first_pending_use_interval(),
-        allocated_head);
+        unallocated->finger()->first_pending_use_interval(), allocated_head);
     if (pos < intersection) intersection = pos;
   }
   return intersection;
 }
 
 
 void ReachingDefs::AddPhi(PhiInstr* phi) {
   if (phi->reaching_defs() == NULL) {
     Zone* zone = flow_graph_.zone();
-    phi->set_reaching_defs(new(zone) BitVector(
-        zone, flow_graph_.max_virtual_register_number()));
+    phi->set_reaching_defs(
+        new (zone) BitVector(zone, flow_graph_.max_virtual_register_number()));
 
     // Compute initial set reaching defs set.
     bool depends_on_phi = false;
     for (intptr_t i = 0; i < phi->InputCount(); i++) {
       Definition* input = phi->InputAt(i)->definition();
       if (input->IsPhi()) {
         depends_on_phi = true;
       }
       phi->reaching_defs()->Add(input->ssa_temp_index());
       if (phi->HasPairRepresentation()) {
@@ skipping 54 matching lines @@
 
 bool FlowGraphAllocator::AllocateFreeRegister(LiveRange* unallocated) {
   intptr_t candidate = kNoRegister;
   intptr_t free_until = 0;
 
   // If hint is available try hint first.
   // TODO(vegorov): ensure that phis are hinted on the back edge.
   Location hint = unallocated->finger()->FirstHint();
   if (hint.IsMachineRegister()) {
     if (!blocked_registers_[hint.register_code()]) {
-      free_until = FirstIntersectionWithAllocated(hint.register_code(),
-                                                  unallocated);
+      free_until =
+          FirstIntersectionWithAllocated(hint.register_code(), unallocated);
       candidate = hint.register_code();
     }
 
     TRACE_ALLOC(THR_Print("found hint %s for v%" Pd ": free until %" Pd "\n",
-                          hint.Name(),
-                          unallocated->vreg(),
-                          free_until));
+                          hint.Name(), unallocated->vreg(), free_until));
   } else {
     for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
       if (!blocked_registers_[reg] && (registers_[reg]->length() == 0)) {
         candidate = reg;
         free_until = kMaxPosition;
         break;
       }
     }
   }
 
@@ skipping 12 matching lines @@
   }
 
   // All registers are blocked by active ranges.
   if (free_until <= unallocated->Start()) return false;
 
   // We have a very good candidate (either hinted to us or completely free).
   // If we are in a loop try to reduce number of moves on the back edge by
   // searching for a candidate that does not interfere with phis on the back
   // edge.
   BlockInfo* loop_header = BlockInfoAt(unallocated->Start())->loop_header();
-  if ((unallocated->vreg() >= 0) &&
-      (loop_header != NULL) &&
+  if ((unallocated->vreg() >= 0) && (loop_header != NULL) &&
       (free_until >= loop_header->last_block()->end_pos()) &&
       loop_header->backedge_interference()->Contains(unallocated->vreg())) {
     GrowableArray<bool> used_on_backedge(number_of_registers_);
     for (intptr_t i = 0; i < number_of_registers_; i++) {
       used_on_backedge.Add(false);
     }
 
-    for (PhiIterator it(loop_header->entry()->AsJoinEntry());
-         !it.Done();
+    for (PhiIterator it(loop_header->entry()->AsJoinEntry()); !it.Done();
          it.Advance()) {
       PhiInstr* phi = it.Current();
       ASSERT(phi->is_alive());
       const intptr_t phi_vreg = phi->ssa_temp_index();
       LiveRange* range = GetLiveRange(phi_vreg);
       if (range->assigned_location().kind() == register_kind_) {
         const intptr_t reg = range->assigned_location().register_code();
         if (!reaching_defs_.Get(phi)->Contains(unallocated->vreg())) {
           used_on_backedge[reg] = true;
         }
       }
       if (phi->HasPairRepresentation()) {
         const intptr_t second_phi_vreg = ToSecondPairVreg(phi_vreg);
         LiveRange* second_range = GetLiveRange(second_phi_vreg);
         if (second_range->assigned_location().kind() == register_kind_) {
           const intptr_t reg =
               second_range->assigned_location().register_code();
           if (!reaching_defs_.Get(phi)->Contains(unallocated->vreg())) {
             used_on_backedge[reg] = true;
           }
         }
       }
     }
 
     if (used_on_backedge[candidate]) {
-      TRACE_ALLOC(THR_Print(
-          "considering %s for v%" Pd ": has interference on the back edge"
-          " {loop [%" Pd ", %" Pd ")}\n",
-          MakeRegisterLocation(candidate).Name(),
-          unallocated->vreg(),
-          loop_header->entry()->start_pos(),
-          loop_header->last_block()->end_pos()));
+      TRACE_ALLOC(THR_Print("considering %s for v%" Pd
+                            ": has interference on the back edge"
+                            " {loop [%" Pd ", %" Pd ")}\n",
+                            MakeRegisterLocation(candidate).Name(),
+                            unallocated->vreg(),
+                            loop_header->entry()->start_pos(),
+                            loop_header->last_block()->end_pos()));
       for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
-        if (blocked_registers_[reg] ||
-            (reg == candidate) ||
+        if (blocked_registers_[reg] || (reg == candidate) ||
             used_on_backedge[reg]) {
           continue;
         }
 
         const intptr_t intersection =
             FirstIntersectionWithAllocated(reg, unallocated);
         if (intersection >= free_until) {
           candidate = reg;
           free_until = intersection;
           TRACE_ALLOC(THR_Print(
               "found %s for v%" Pd " with no interference on the back edge\n",
-              MakeRegisterLocation(candidate).Name(),
-              candidate));
+              MakeRegisterLocation(candidate).Name(), candidate));
           break;
         }
       }
     }
   }
 
   TRACE_ALLOC(THR_Print("assigning free register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate).Print());
   TRACE_ALLOC(THR_Print(" to v%" Pd "\n", unallocated->vreg()));
 
@@ skipping 83 matching lines @@
   intptr_t blocked_at = kMaxPosition;
 
   for (int reg = 0; reg < NumberOfRegisters(); ++reg) {
     if (blocked_registers_[reg]) continue;
     if (UpdateFreeUntil(reg, unallocated, &free_until, &blocked_at)) {
       candidate = reg;
     }
   }
 
   const intptr_t register_use_pos =
-      (register_use != NULL) ? register_use->pos()
-                             : unallocated->Start();
+      (register_use != NULL) ? register_use->pos() : unallocated->Start();
   if (free_until < register_use_pos) {
     // Can't acquire free register. Spill until we really need one.
     ASSERT(unallocated->Start() < ToInstructionStart(register_use_pos));
     SpillBetween(unallocated, unallocated->Start(), register_use->pos());
     return;
   }
 
   ASSERT(candidate != kNoRegister);
 
   TRACE_ALLOC(THR_Print("assigning blocked register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate).Print());
   TRACE_ALLOC(THR_Print(" to live range v%" Pd " until %" Pd "\n",
                         unallocated->vreg(), blocked_at));
 
   if (blocked_at < unallocated->End()) {
     // Register is blocked before the end of the live range.  Split the range
     // at latest at blocked_at position.
-    LiveRange* tail = SplitBetween(unallocated,
-                                   unallocated->Start(),
-                                   blocked_at + 1);
+    LiveRange* tail =
+        SplitBetween(unallocated, unallocated->Start(), blocked_at + 1);
     AddToUnallocated(tail);
   }
 
   AssignNonFreeRegister(unallocated, candidate);
 }
 
 
 bool FlowGraphAllocator::UpdateFreeUntil(intptr_t reg,
                                          LiveRange* unallocated,
                                          intptr_t* cur_free_until,
                                          intptr_t* cur_blocked_at) {
   intptr_t free_until = kMaxPosition;
   intptr_t blocked_at = kMaxPosition;
   const intptr_t start = unallocated->Start();
 
   for (intptr_t i = 0; i < registers_[reg]->length(); i++) {
     LiveRange* allocated = (*registers_[reg])[i];
 
     UseInterval* first_pending_use_interval =
         allocated->finger()->first_pending_use_interval();
     if (first_pending_use_interval->Contains(start)) {
       // This is an active interval.
       if (allocated->vreg() < 0) {
         // This register blocked by an interval that
         // can't be spilled.
         return false;
       }
 
-      UsePosition* use =
-          allocated->finger()->FirstInterferingUse(start);
+      UsePosition* use = allocated->finger()->FirstInterferingUse(start);
       if ((use != NULL) && ((ToInstructionStart(use->pos()) - start) <= 1)) {
         // This register is blocked by interval that is used
         // as register in the current instruction and can't
         // be spilled.
         return false;
       }
 
-      const intptr_t use_pos = (use != NULL) ? use->pos()
-                                             : allocated->End();
+      const intptr_t use_pos = (use != NULL) ? use->pos() : allocated->End();
 
       if (use_pos < free_until) free_until = use_pos;
     } else {
       // This is inactive interval.
       const intptr_t intersection = FirstIntersection(
           first_pending_use_interval, unallocated->first_use_interval());
       if (intersection != kMaxPosition) {
         if (intersection < free_until) free_until = intersection;
         if (allocated->vreg() == kNoVirtualRegister) blocked_at = intersection;
       }
@@ skipping 48 matching lines @@
   last_used_register_ = Utils::Maximum(last_used_register_, reg);
 #endif
 }
 
 
 bool FlowGraphAllocator::EvictIntersection(LiveRange* allocated,
                                            LiveRange* unallocated) {
   UseInterval* first_unallocated =
       unallocated->finger()->first_pending_use_interval();
   const intptr_t intersection = FirstIntersection(
-      allocated->finger()->first_pending_use_interval(),
-      first_unallocated);
+      allocated->finger()->first_pending_use_interval(), first_unallocated);
   if (intersection == kMaxPosition) return false;
 
   const intptr_t spill_position = first_unallocated->start();
   UsePosition* use = allocated->finger()->FirstInterferingUse(spill_position);
   if (use == NULL) {
     // No register uses after this point.
     SpillAfter(allocated, spill_position);
   } else {
     const intptr_t restore_position =
         (spill_position < intersection) ? MinPosition(intersection, use->pos())
@@ skipping 57 matching lines @@
   TRACE_ALLOC(THR_Print(":\n"));
 
   for (UsePosition* use = range->first_use(); use != NULL; use = use->next()) {
     ConvertUseTo(use, loc);
   }
 
   // Add live registers at all safepoints for instructions with slow-path
   // code.
   if (loc.IsMachineRegister()) {
     for (SafepointPosition* safepoint = range->first_safepoint();
-         safepoint != NULL;
-         safepoint = safepoint->next()) {
+         safepoint != NULL; safepoint = safepoint->next()) {
 #if !defined(TARGET_ARCH_DBC)
       if (!safepoint->locs()->always_calls()) {
         ASSERT(safepoint->locs()->can_call());
         safepoint->locs()->live_registers()->Add(loc, range->representation());
       }
 #else
       if (range->representation() == kTagged) {
         safepoint->locs()->SetStackBit(loc.reg());
       }
 #endif  // !defined(TARGET_ARCH_DBC)
@@ skipping 17 matching lines @@
     }
 
     if (first_evicted != -1) RemoveEvicted(reg, first_evicted);
   }
 }
 
 
 bool LiveRange::Contains(intptr_t pos) const {
   if (!CanCover(pos)) return false;
 
-  for (UseInterval* interval = first_use_interval_;
-       interval != NULL;
+  for (UseInterval* interval = first_use_interval_; interval != NULL;
        interval = interval->next()) {
     if (interval->Contains(pos)) {
       return true;
     }
   }
 
   return false;
 }
 
 
-void FlowGraphAllocator::AssignSafepoints(Definition* defn,
-                                          LiveRange* range) {
+void FlowGraphAllocator::AssignSafepoints(Definition* defn, LiveRange* range) {
   for (intptr_t i = safepoints_.length() - 1; i >= 0; i--) {
     Instruction* safepoint_instr = safepoints_[i];
     if (safepoint_instr == defn) {
       // The value is not live until after the definition is fully executed,
       // don't assign the safepoint inside the definition itself to
       // definition's liverange.
       continue;
     }
 
     const intptr_t pos = safepoint_instr->lifetime_position();
@@ skipping 101 matching lines @@
 void FlowGraphAllocator::AllocateUnallocatedRanges() {
 #if defined(DEBUG)
   ASSERT(UnallocatedIsSorted());
 #endif
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.RemoveLast();
     const intptr_t start = range->Start();
     TRACE_ALLOC(THR_Print("Processing live range for v%" Pd " "
                           "starting at %" Pd "\n",
-                          range->vreg(),
-                          start));
+                          range->vreg(), start));
 
     // TODO(vegorov): eagerly spill liveranges without register uses.
     AdvanceActiveIntervals(start);
 
     if (!AllocateFreeRegister(range)) {
       if (intrinsic_mode_) {
         // No spilling when compiling intrinsics.
         // TODO(fschneider): Handle spilling in intrinsics. For now, the
         // IR has to be built so that there are enough free registers.
         UNREACHABLE();
       }
       AllocateAnyRegister(range);
     }
   }
 
   // All allocation decisions were done.
   ASSERT(unallocated_.is_empty());
 
   // Finish allocation.
   AdvanceActiveIntervals(kMaxPosition);
   TRACE_ALLOC(THR_Print("Allocation completed\n"));
 }
 
 
 bool FlowGraphAllocator::TargetLocationIsSpillSlot(LiveRange* range,
                                                    Location target) {
-  if (target.IsStackSlot() ||
-      target.IsDoubleStackSlot() ||
+  if (target.IsStackSlot() || target.IsDoubleStackSlot() ||
       target.IsConstant()) {
     ASSERT(GetLiveRange(range->vreg())->spill_slot().Equals(target));
     return true;
   }
   return false;
 }
 
 
 void FlowGraphAllocator::ConnectSplitSiblings(LiveRange* parent,
                                               BlockEntryInstr* source_block,
                                               BlockEntryInstr* target_block) {
   TRACE_ALLOC(THR_Print("Connect v%" Pd " on the edge B%" Pd " -> B%" Pd "\n",
-                        parent->vreg(),
-                        source_block->block_id(),
+                        parent->vreg(), source_block->block_id(),
                         target_block->block_id()));
   if (parent->next_sibling() == NULL) {
     // Nothing to connect. The whole range was allocated to the same location.
     TRACE_ALLOC(THR_Print("range v%" Pd " has no siblings\n", parent->vreg()));
     return;
   }
 
   const intptr_t source_pos = source_block->end_pos() - 1;
   ASSERT(IsInstructionEndPosition(source_pos));
 
@@ skipping 22 matching lines @@
 #if defined(DEBUG)
       target_cover = range;
 #endif
     }
 
     range = range->next_sibling();
   }
 
   TRACE_ALLOC(THR_Print("connecting v%" Pd " between [%" Pd ", %" Pd ") {%s} "
                         "to [%" Pd ", %" Pd ") {%s}\n",
-                        parent->vreg(),
-                        source_cover->Start(),
-                        source_cover->End(),
-                        source.Name(),
-                        target_cover->Start(),
-                        target_cover->End(),
+                        parent->vreg(), source_cover->Start(),
+                        source_cover->End(), source.Name(),
+                        target_cover->Start(), target_cover->End(),
                         target.Name()));
 
   // Siblings were allocated to the same register.
   if (source.Equals(target)) return;
 
   // Values are eagerly spilled. Spill slot already contains appropriate value.
   if (TargetLocationIsSpillSlot(parent, target)) {
     return;
   }
 
   Instruction* last = source_block->last_instruction();
   if ((last->SuccessorCount() == 1) && !source_block->IsGraphEntry()) {
     ASSERT(last->IsGoto());
     last->AsGoto()->GetParallelMove()->AddMove(target, source);
   } else {
     target_block->GetParallelMove()->AddMove(target, source);
   }
 }
 
 
 void FlowGraphAllocator::ResolveControlFlow() {
   // Resolve linear control flow between touching split siblings
   // inside basic blocks.
   for (intptr_t vreg = 0; vreg < live_ranges_.length(); vreg++) {
     LiveRange* range = live_ranges_[vreg];
     if (range == NULL) continue;
 
     while (range->next_sibling() != NULL) {
       LiveRange* sibling = range->next_sibling();
-      TRACE_ALLOC(THR_Print("connecting [%" Pd ", %" Pd ") [",
-                            range->Start(), range->End()));
+      TRACE_ALLOC(THR_Print("connecting [%" Pd ", %" Pd ") [", range->Start(),
+                            range->End()));
       TRACE_ALLOC(range->assigned_location().Print());
-      TRACE_ALLOC(THR_Print("] to [%" Pd ", %" Pd ") [",
-                            sibling->Start(), sibling->End()));
+      TRACE_ALLOC(THR_Print("] to [%" Pd ", %" Pd ") [", sibling->Start(),
+                            sibling->End()));
       TRACE_ALLOC(sibling->assigned_location().Print());
       TRACE_ALLOC(THR_Print("]\n"));
       if ((range->End() == sibling->Start()) &&
           !TargetLocationIsSpillSlot(range, sibling->assigned_location()) &&
           !range->assigned_location().Equals(sibling->assigned_location()) &&
           !IsBlockEntry(range->End())) {
-        AddMoveAt(sibling->Start(),
-                  sibling->assigned_location(),
+        AddMoveAt(sibling->Start(), sibling->assigned_location(),
                   range->assigned_location());
       }
       range = sibling;
     }
   }
 
   // Resolve non-linear control flow across branches.
   for (intptr_t i = 1; i < block_order_.length(); i++) {
     BlockEntryInstr* block = block_order_[i];
     BitVector* live = liveness_.GetLiveInSet(block);
     for (BitVector::Iterator it(live); !it.Done(); it.Advance()) {
       LiveRange* range = GetLiveRange(it.Current());
       for (intptr_t j = 0; j < block->PredecessorCount(); j++) {
         ConnectSplitSiblings(range, block->PredecessorAt(j), block);
       }
     }
   }
 
   // Eagerly spill values.
   // TODO(vegorov): if value is spilled on the cold path (e.g. by the call)
   // this will cause spilling to occur on the fast path (at the definition).
   for (intptr_t i = 0; i < spilled_.length(); i++) {
     LiveRange* range = spilled_[i];
     if (range->assigned_location().IsStackSlot() ||
         range->assigned_location().IsDoubleStackSlot() ||
         range->assigned_location().IsConstant()) {
       ASSERT(range->assigned_location().Equals(range->spill_slot()));
     } else {
-      AddMoveAt(range->Start() + 1,
-                range->spill_slot(),
+      AddMoveAt(range->Start() + 1, range->spill_slot(),
                 range->assigned_location());
     }
   }
 }
 
 
 static Representation RepresentationForRange(Representation definition_rep) {
   if (definition_rep == kUnboxedMint) {
     // kUnboxedMint is split into two ranges, each of which are kUntagged.
     return kUntagged;
   } else if (definition_rep == kUnboxedUint32) {
     // kUnboxedUint32 is untagged.
     return kUntagged;
   }
   return definition_rep;
 }
 
 
 void FlowGraphAllocator::CollectRepresentations() {
   // Parameters.
   GraphEntryInstr* graph_entry = flow_graph_.graph_entry();
   for (intptr_t i = 0; i < graph_entry->initial_definitions()->length(); ++i) {
     Definition* def = (*graph_entry->initial_definitions())[i];
     value_representations_[def->ssa_temp_index()] =
         RepresentationForRange(def->representation());
     ASSERT(!def->HasPairRepresentation());
   }
 
-  for (BlockIterator it = flow_graph_.reverse_postorder_iterator();
-       !it.Done();
+  for (BlockIterator it = flow_graph_.reverse_postorder_iterator(); !it.Done();
        it.Advance()) {
     BlockEntryInstr* block = it.Current();
 
     // Catch entry.
     if (block->IsCatchBlockEntry()) {
       CatchBlockEntryInstr* catch_entry = block->AsCatchBlockEntry();
-      for (intptr_t i = 0;
-           i < catch_entry->initial_definitions()->length();
+      for (intptr_t i = 0; i < catch_entry->initial_definitions()->length();
            ++i) {
         Definition* def = (*catch_entry->initial_definitions())[i];
         ASSERT(!def->HasPairRepresentation());
         value_representations_[def->ssa_temp_index()] =
             RepresentationForRange(def->representation());
       }
     }
     // Phis.
     if (block->IsJoinEntry()) {
       JoinEntryInstr* join = block->AsJoinEntry();
       for (PhiIterator it(join); !it.Done(); it.Advance()) {
         PhiInstr* phi = it.Current();
         ASSERT(phi != NULL && phi->ssa_temp_index() >= 0);
         value_representations_[phi->ssa_temp_index()] =
             RepresentationForRange(phi->representation());
         if (phi->HasPairRepresentation()) {
           value_representations_[ToSecondPairVreg(phi->ssa_temp_index())] =
               RepresentationForRange(phi->representation());
         }
       }
     }
     // Normal instructions.
-    for (ForwardInstructionIterator instr_it(block);
-         !instr_it.Done();
+    for (ForwardInstructionIterator instr_it(block); !instr_it.Done();
          instr_it.Advance()) {
       Definition* def = instr_it.Current()->AsDefinition();
       if ((def != NULL) && (def->ssa_temp_index() >= 0)) {
         const intptr_t vreg = def->ssa_temp_index();
         value_representations_[vreg] =
             RepresentationForRange(def->representation());
         if (def->HasPairRepresentation()) {
-         value_representations_[ToSecondPairVreg(vreg)] =
-            RepresentationForRange(def->representation());
+          value_representations_[ToSecondPairVreg(vreg)] =
+              RepresentationForRange(def->representation());
         }
       }
     }
   }
 }
 
 
 void FlowGraphAllocator::AllocateRegisters() {
   CollectRepresentations();
 
@@ skipping 20 matching lines @@
               function.ToFullyQualifiedCString());
     if (FLAG_support_il_printer) {
 #ifndef PRODUCT
       FlowGraphPrinter printer(flow_graph_, true);
       printer.PrintBlocks();
 #endif
     }
     THR_Print("----------------------------------------------\n");
   }
 
-  PrepareForAllocation(Location::kRegister,
-                       kNumberOfCpuRegisters,
-                       unallocated_cpu_,
-                       cpu_regs_,
-                       blocked_cpu_registers_);
+  PrepareForAllocation(Location::kRegister, kNumberOfCpuRegisters,
+                       unallocated_cpu_, cpu_regs_, blocked_cpu_registers_);
   AllocateUnallocatedRanges();
 #if defined(TARGET_ARCH_DBC)
   const intptr_t last_used_cpu_register = last_used_register_;
   last_used_register_ = -1;
 #endif
 
   cpu_spill_slot_count_ = spill_slots_.length();
   spill_slots_.Clear();
   quad_spill_slots_.Clear();
   untagged_spill_slots_.Clear();
 
-  PrepareForAllocation(Location::kFpuRegister,
-                       kNumberOfFpuRegisters,
-                       unallocated_xmm_,
-                       fpu_regs_,
-                       blocked_fpu_registers_);
+  PrepareForAllocation(Location::kFpuRegister, kNumberOfFpuRegisters,
+                       unallocated_xmm_, fpu_regs_, blocked_fpu_registers_);
 #if defined(TARGET_ARCH_DBC)
   // For DBC all registers should have been allocated in the first pass.
   ASSERT(unallocated_.is_empty());
 #endif
 
   AllocateUnallocatedRanges();
 #if defined(TARGET_ARCH_DBC)
   const intptr_t last_used_fpu_register = last_used_register_;
   ASSERT(last_used_fpu_register == -1);  // Not supported right now.
 #endif
 
   ResolveControlFlow();
 
   GraphEntryInstr* entry = block_order_[0]->AsGraphEntry();
   ASSERT(entry != NULL);
   intptr_t double_spill_slot_count = spill_slots_.length() * kDoubleSpillFactor;
   entry->set_spill_slot_count(cpu_spill_slot_count_ + double_spill_slot_count);
 
 #if defined(TARGET_ARCH_DBC)
   // Spilling is unsupported on DBC.
   if (entry->spill_slot_count() != 0) {
     UNREACHABLE();
   }
 
   // We store number of used DBC registers in the spill slot count to avoid
   // introducing a separate field. It has roughly the same meaning:
   // number of used registers determines how big of a frame to reserve for
   // this function on DBC stack.
-  entry->set_spill_slot_count(Utils::Maximum((last_used_cpu_register + 1) +
-                                             (last_used_fpu_register + 1),
-                                             flow_graph_.num_copied_params()));
+  entry->set_spill_slot_count(Utils::Maximum(
+      (last_used_cpu_register + 1) + (last_used_fpu_register + 1),
+      flow_graph_.num_copied_params()));
 #endif
 
   if (FLAG_print_ssa_liveranges) {
     const Function& function = flow_graph_.function();
 
     THR_Print("-- [after ssa allocator] ranges [%s] ---------\n",
               function.ToFullyQualifiedCString());
     PrintLiveRanges();
     THR_Print("----------------------------------------------\n");
 
     THR_Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     if (FLAG_support_il_printer) {
 #ifndef PRODUCT
       FlowGraphPrinter printer(flow_graph_, true);
       printer.PrintBlocks();
 #endif
     }
     THR_Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart