clang-format runtime/vm

runtime/vm/disassembler_x64.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_IA32.
 #if defined(TARGET_ARCH_X64)
 #include "platform/utils.h"
 #include "vm/allocation.h"
@@ skipping 22 matching lines @@
 // Tables
 //------------------------------------------------------------------
 struct ByteMnemonic {
   int b;  // -1 terminates, otherwise must be in range (0..255)
   OperandType op_order_;
   const char* mnem;
 };
 
 
 static const ByteMnemonic two_operands_instr[] = {
-  { 0x00, BYTE_OPER_REG_OP_ORDER, "add" },
-  { 0x01, OPER_REG_OP_ORDER,      "add" },
-  { 0x02, BYTE_REG_OPER_OP_ORDER, "add" },
-  { 0x03, REG_OPER_OP_ORDER,      "add" },
-  { 0x08, BYTE_OPER_REG_OP_ORDER, "or" },
-  { 0x09, OPER_REG_OP_ORDER,      "or" },
-  { 0x0A, BYTE_REG_OPER_OP_ORDER, "or" },
-  { 0x0B, REG_OPER_OP_ORDER,      "or" },
-  { 0x10, BYTE_OPER_REG_OP_ORDER, "adc" },
-  { 0x11, OPER_REG_OP_ORDER,      "adc" },
-  { 0x12, BYTE_REG_OPER_OP_ORDER, "adc" },
-  { 0x13, REG_OPER_OP_ORDER,      "adc" },
-  { 0x18, BYTE_OPER_REG_OP_ORDER, "sbb" },
-  { 0x19, OPER_REG_OP_ORDER,      "sbb" },
-  { 0x1A, BYTE_REG_OPER_OP_ORDER, "sbb" },
-  { 0x1B, REG_OPER_OP_ORDER,      "sbb" },
-  { 0x20, BYTE_OPER_REG_OP_ORDER, "and" },
-  { 0x21, OPER_REG_OP_ORDER,      "and" },
-  { 0x22, BYTE_REG_OPER_OP_ORDER, "and" },
-  { 0x23, REG_OPER_OP_ORDER,      "and" },
-  { 0x28, BYTE_OPER_REG_OP_ORDER, "sub" },
-  { 0x29, OPER_REG_OP_ORDER,      "sub" },
-  { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" },
-  { 0x2B, REG_OPER_OP_ORDER,      "sub" },
-  { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" },
-  { 0x31, OPER_REG_OP_ORDER,      "xor" },
-  { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" },
-  { 0x33, REG_OPER_OP_ORDER,      "xor" },
-  { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" },
-  { 0x39, OPER_REG_OP_ORDER,      "cmp" },
-  { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" },
-  { 0x3B, REG_OPER_OP_ORDER,      "cmp" },
-  { 0x63, REG_OPER_OP_ORDER,      "movsxd" },
-  { 0x84, BYTE_REG_OPER_OP_ORDER, "test" },
-  { 0x85, REG_OPER_OP_ORDER,      "test" },
-  { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" },
-  { 0x87, REG_OPER_OP_ORDER,      "xchg" },
-  { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" },
-  { 0x89, OPER_REG_OP_ORDER,      "mov" },
-  { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" },
-  { 0x8B, REG_OPER_OP_ORDER,      "mov" },
-  { 0x8D, REG_OPER_OP_ORDER,      "lea" },
-  { -1, UNSET_OP_ORDER, "" }
-};
+    {0x00, BYTE_OPER_REG_OP_ORDER, "add"},
+    {0x01, OPER_REG_OP_ORDER, "add"},
+    {0x02, BYTE_REG_OPER_OP_ORDER, "add"},
+    {0x03, REG_OPER_OP_ORDER, "add"},
+    {0x08, BYTE_OPER_REG_OP_ORDER, "or"},
+    {0x09, OPER_REG_OP_ORDER, "or"},
+    {0x0A, BYTE_REG_OPER_OP_ORDER, "or"},
+    {0x0B, REG_OPER_OP_ORDER, "or"},
+    {0x10, BYTE_OPER_REG_OP_ORDER, "adc"},
+    {0x11, OPER_REG_OP_ORDER, "adc"},
+    {0x12, BYTE_REG_OPER_OP_ORDER, "adc"},
+    {0x13, REG_OPER_OP_ORDER, "adc"},
+    {0x18, BYTE_OPER_REG_OP_ORDER, "sbb"},
+    {0x19, OPER_REG_OP_ORDER, "sbb"},
+    {0x1A, BYTE_REG_OPER_OP_ORDER, "sbb"},
+    {0x1B, REG_OPER_OP_ORDER, "sbb"},
+    {0x20, BYTE_OPER_REG_OP_ORDER, "and"},
+    {0x21, OPER_REG_OP_ORDER, "and"},
+    {0x22, BYTE_REG_OPER_OP_ORDER, "and"},
+    {0x23, REG_OPER_OP_ORDER, "and"},
+    {0x28, BYTE_OPER_REG_OP_ORDER, "sub"},
+    {0x29, OPER_REG_OP_ORDER, "sub"},
+    {0x2A, BYTE_REG_OPER_OP_ORDER, "sub"},
+    {0x2B, REG_OPER_OP_ORDER, "sub"},
+    {0x30, BYTE_OPER_REG_OP_ORDER, "xor"},
+    {0x31, OPER_REG_OP_ORDER, "xor"},
+    {0x32, BYTE_REG_OPER_OP_ORDER, "xor"},
+    {0x33, REG_OPER_OP_ORDER, "xor"},
+    {0x38, BYTE_OPER_REG_OP_ORDER, "cmp"},
+    {0x39, OPER_REG_OP_ORDER, "cmp"},
+    {0x3A, BYTE_REG_OPER_OP_ORDER, "cmp"},
+    {0x3B, REG_OPER_OP_ORDER, "cmp"},
+    {0x63, REG_OPER_OP_ORDER, "movsxd"},
+    {0x84, BYTE_REG_OPER_OP_ORDER, "test"},
+    {0x85, REG_OPER_OP_ORDER, "test"},
+    {0x86, BYTE_REG_OPER_OP_ORDER, "xchg"},
+    {0x87, REG_OPER_OP_ORDER, "xchg"},
+    {0x88, BYTE_OPER_REG_OP_ORDER, "mov"},
+    {0x89, OPER_REG_OP_ORDER, "mov"},
+    {0x8A, BYTE_REG_OPER_OP_ORDER, "mov"},
+    {0x8B, REG_OPER_OP_ORDER, "mov"},
+    {0x8D, REG_OPER_OP_ORDER, "lea"},
+    {-1, UNSET_OP_ORDER, ""}};
 
 
 static const ByteMnemonic zero_operands_instr[] = {
-  { 0xC3, UNSET_OP_ORDER, "ret" },
-  { 0xC9, UNSET_OP_ORDER, "leave" },
-  { 0xF4, UNSET_OP_ORDER, "hlt" },
-  { 0xFC, UNSET_OP_ORDER, "cld" },
-  { 0xCC, UNSET_OP_ORDER, "int3" },
-  { 0x60, UNSET_OP_ORDER, "pushad" },
-  { 0x61, UNSET_OP_ORDER, "popad" },
-  { 0x9C, UNSET_OP_ORDER, "pushfd" },
-  { 0x9D, UNSET_OP_ORDER, "popfd" },
-  { 0x9E, UNSET_OP_ORDER, "sahf" },
-  { 0x99, UNSET_OP_ORDER, "cdq" },
-  { 0x9B, UNSET_OP_ORDER, "fwait" },
-  { 0xA4, UNSET_OP_ORDER, "movs" },
-  { 0xA5, UNSET_OP_ORDER, "movs" },
-  { 0xA6, UNSET_OP_ORDER, "cmps" },
-  { 0xA7, UNSET_OP_ORDER, "cmps" },
-  { -1, UNSET_OP_ORDER, "" }
-};
+    {0xC3, UNSET_OP_ORDER, "ret"},   {0xC9, UNSET_OP_ORDER, "leave"},
+    {0xF4, UNSET_OP_ORDER, "hlt"},   {0xFC, UNSET_OP_ORDER, "cld"},
+    {0xCC, UNSET_OP_ORDER, "int3"},  {0x60, UNSET_OP_ORDER, "pushad"},
+    {0x61, UNSET_OP_ORDER, "popad"}, {0x9C, UNSET_OP_ORDER, "pushfd"},
+    {0x9D, UNSET_OP_ORDER, "popfd"}, {0x9E, UNSET_OP_ORDER, "sahf"},
+    {0x99, UNSET_OP_ORDER, "cdq"},   {0x9B, UNSET_OP_ORDER, "fwait"},
+    {0xA4, UNSET_OP_ORDER, "movs"},  {0xA5, UNSET_OP_ORDER, "movs"},
+    {0xA6, UNSET_OP_ORDER, "cmps"},  {0xA7, UNSET_OP_ORDER, "cmps"},
+    {-1, UNSET_OP_ORDER, ""}};
 
 
-static const ByteMnemonic call_jump_instr[] = {
-  { 0xE8, UNSET_OP_ORDER, "call" },
-  { 0xE9, UNSET_OP_ORDER, "jmp" },
-  { -1, UNSET_OP_ORDER, "" }
-};
+static const ByteMnemonic call_jump_instr[] = {{0xE8, UNSET_OP_ORDER, "call"},
+                                               {0xE9, UNSET_OP_ORDER, "jmp"},
+                                               {-1, UNSET_OP_ORDER, ""}};
 
 
 static const ByteMnemonic short_immediate_instr[] = {
-  { 0x05, UNSET_OP_ORDER, "add" },
-  { 0x0D, UNSET_OP_ORDER, "or" },
-  { 0x15, UNSET_OP_ORDER, "adc" },
-  { 0x1D, UNSET_OP_ORDER, "sbb" },
-  { 0x25, UNSET_OP_ORDER, "and" },
-  { 0x2D, UNSET_OP_ORDER, "sub" },
-  { 0x35, UNSET_OP_ORDER, "xor" },
-  { 0x3D, UNSET_OP_ORDER, "cmp" },
-  { -1, UNSET_OP_ORDER, "" }
-};
+    {0x05, UNSET_OP_ORDER, "add"}, {0x0D, UNSET_OP_ORDER, "or"},
+    {0x15, UNSET_OP_ORDER, "adc"}, {0x1D, UNSET_OP_ORDER, "sbb"},
+    {0x25, UNSET_OP_ORDER, "and"}, {0x2D, UNSET_OP_ORDER, "sub"},
+    {0x35, UNSET_OP_ORDER, "xor"}, {0x3D, UNSET_OP_ORDER, "cmp"},
+    {-1, UNSET_OP_ORDER, ""}};
 
 
 static const char* const conditional_code_suffix[] = {
-  "o", "no", "c", "nc", "z", "nz", "na", "a",
-  "s", "ns", "pe", "po", "l", "ge", "le", "g"
-};
+    "o", "no", "c",  "nc", "z", "nz", "na", "a",
+    "s", "ns", "pe", "po", "l", "ge", "le", "g"};
 
 
 enum InstructionType {
   NO_INSTR,
   ZERO_OPERANDS_INSTR,
   TWO_OPERANDS_INSTR,
   JUMP_CONDITIONAL_SHORT_INSTR,
   REGISTER_INSTR,
   PUSHPOP_INSTR,  // Has implicit 64-bit operand size.
   MOVE_REG_INSTR,
@@ skipping 16 matching lines @@
   const char* mnem;
   InstructionType type;
   OperandType op_order_;
   bool byte_size_operation;  // Fixed 8-bit operation.
 };
 
 
 class InstructionTable : public ValueObject {
  public:
   InstructionTable();
-  const InstructionDesc& Get(uint8_t x) const {
-    return instructions_[x];
-  }
+  const InstructionDesc& Get(uint8_t x) const { return instructions_[x]; }
 
  private:
   InstructionDesc instructions_[256];
   void Clear();
   void Init();
   void CopyTable(const ByteMnemonic bm[], InstructionType type);
   void SetTableRange(InstructionType type,
                      uint8_t start,
                      uint8_t end,
                      bool byte_size,
@@ skipping 59 matching lines @@
     id->type = type;
     id->byte_size_operation = byte_size;
   }
 }
 
 
 void InstructionTable::AddJumpConditionalShort() {
   for (uint8_t b = 0x70; b <= 0x7F; b++) {
     InstructionDesc* id = &instructions_[b];
     ASSERT(NO_INSTR == id->type);  // Information not already entered
-    id->mnem = NULL;  // Computed depending on condition code.
+    id->mnem = NULL;               // Computed depending on condition code.
     id->type = JUMP_CONDITIONAL_SHORT_INSTR;
   }
 }
 
 
 static InstructionTable instruction_table;
 
 
 static InstructionDesc cmov_instructions[16] = {
-  {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
-  {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
-};
+    {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+    {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}};
 
 
 //-------------------------------------------------
 // DisassemblerX64 implementation.
 
 
 static const int kMaxXmmRegisters = 16;
 static const char* xmm_regs[kMaxXmmRegisters] = {
-  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
-  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
-};
+    "xmm0", "xmm1", "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",  "xmm7",
+    "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"};
 
 class DisassemblerX64 : public ValueObject {
  public:
   DisassemblerX64(char* buffer, intptr_t buffer_size)
       : buffer_(buffer),
         buffer_size_(buffer_size),
         buffer_pos_(0),
         rex_(0),
         operand_size_(0),
         group_1_prefix_(0),
         byte_size_operand_(false) {
     buffer_[buffer_pos_] = '\0';
   }
 
-  virtual ~DisassemblerX64() {
-  }
+  virtual ~DisassemblerX64() {}
 
   int InstructionDecode(uword pc);
 
  private:
   enum OperandSize {
     BYTE_SIZE = 0,
     WORD_SIZE = 1,
     DOUBLEWORD_SIZE = 2,
     QUADWORD_SIZE = 3
   };
@@ skipping 16 matching lines @@
 
   bool rex_w() { return (rex_ & 0x08) != 0; }
 
   OperandSize operand_size() {
     if (byte_size_operand_) return BYTE_SIZE;
     if (rex_w()) return QUADWORD_SIZE;
     if (operand_size_ != 0) return WORD_SIZE;
     return DOUBLEWORD_SIZE;
   }
 
-  char operand_size_code() {
-    return "bwlq"[operand_size()];
-  }
+  char operand_size_code() { return "bwlq"[operand_size()]; }
 
   // Disassembler helper functions.
-  void get_modrm(uint8_t data,
-                 int* mod,
-                 int* regop,
-                 int* rm) {
+  void get_modrm(uint8_t data, int* mod, int* regop, int* rm) {
     *mod = (data >> 6) & 3;
     *regop = ((data & 0x38) >> 3) | (rex_r() ? 8 : 0);
     *rm = (data & 7) | (rex_b() ? 8 : 0);
   }
 
-  void get_sib(uint8_t data,
-               int* scale,
-               int* index,
-               int* base) {
+  void get_sib(uint8_t data, int* scale, int* index, int* base) {
     *scale = (data >> 6) & 3;
     *index = ((data >> 3) & 7) | (rex_x() ? 8 : 0);
     *base = (data & 7) | (rex_b() ? 8 : 0);
   }
 
   const char* NameOfCPURegister(int reg) const {
     return Assembler::RegisterName(static_cast<Register>(reg));
   }
 
   const char* NameOfByteCPURegister(int reg) const {
     return NameOfCPURegister(reg);
   }
 
   const char* NameOfXMMRegister(int reg) const {
     ASSERT((0 <= reg) && (reg < kMaxXmmRegisters));
     return xmm_regs[reg];
   }
 
   void Print(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
   void PrintAddress(uint8_t* addr);
 
-  int PrintOperands(const char* mnem,
-                    OperandType op_order,
-                    uint8_t* data);
+  int PrintOperands(const char* mnem, OperandType op_order, uint8_t* data);
 
   typedef const char* (DisassemblerX64::*RegisterNameMapping)(int reg) const;
 
   int PrintRightOperandHelper(uint8_t* modrmp,
                               RegisterNameMapping register_name);
   int PrintRightOperand(uint8_t* modrmp);
   int PrintRightByteOperand(uint8_t* modrmp);
   int PrintRightXMMOperand(uint8_t* modrmp);
   void PrintDisp(int disp, const char* after);
   int PrintImmediate(uint8_t* data, OperandSize size);
   void PrintImmediateValue(int64_t value);
   int PrintImmediateOp(uint8_t* data);
   const char* TwoByteMnemonic(uint8_t opcode);
   int TwoByteOpcodeInstruction(uint8_t* data);
 
   int F6F7Instruction(uint8_t* data);
   int ShiftInstruction(uint8_t* data);
   int JumpShort(uint8_t* data);
   int JumpConditional(uint8_t* data);
   int JumpConditionalShort(uint8_t* data);
   int SetCC(uint8_t* data);
   int FPUInstruction(uint8_t* data);
   int MemoryFPUInstruction(int escape_opcode, int regop, uint8_t* modrm_start);
   int RegisterFPUInstruction(int escape_opcode, uint8_t modrm_byte);
 
   bool DecodeInstructionType(uint8_t** data);
 
-  void UnimplementedInstruction() {
-    Print("'Unimplemented Instruction'");
-  }
+  void UnimplementedInstruction() { Print("'Unimplemented Instruction'"); }
 
-  char* buffer_;  // Decode instructions into this buffer.
+  char* buffer_;          // Decode instructions into this buffer.
   intptr_t buffer_size_;  // The size of the buffer_.
-  intptr_t buffer_pos_;  // Current character position in the buffer_.
+  intptr_t buffer_pos_;   // Current character position in the buffer_.
 
   // Prefixes parsed
   uint8_t rex_;
   uint8_t operand_size_;  // 0x66 or (if no group 3 prefix is present) 0x0.
   // 0xF2, 0xF3, or (if no group 1 prefix is present) 0.
   uint8_t group_1_prefix_;
   // Byte size operand override.
   bool byte_size_operand_;
 
   DISALLOW_COPY_AND_ASSIGN(DisassemblerX64);
@@ skipping 16 matching lines @@
       (length >= available) ? (buffer_size_ - 1) : (buffer_pos_ + length);
   ASSERT(buffer_pos_ < buffer_size_);
 }
 
 
 int DisassemblerX64::PrintRightOperandHelper(
     uint8_t* modrmp,
     RegisterNameMapping direct_register_name) {
   int mod, regop, rm;
   get_modrm(*modrmp, &mod, &regop, &rm);
-  RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
-      &DisassemblerX64::NameOfCPURegister;
+  RegisterNameMapping register_name =
+      (mod == 3) ? direct_register_name : &DisassemblerX64::NameOfCPURegister;
   switch (mod) {
     case 0:
       if ((rm & 7) == 5) {
         int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 1);
         Print("[rip");
         PrintDisp(disp, "]");
         return 5;
       } else if ((rm & 7) == 4) {
         // Codes for SIB byte.
         uint8_t sib = *(modrmp + 1);
         int scale, index, base;
         get_sib(sib, &scale, &index, &base);
         if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
           // index == rsp means no index. Only use sib byte with no index for
           // rsp and r12 base.
           Print("[%s]", NameOfCPURegister(base));
           return 2;
         } else if (base == 5) {
           // base == rbp means no base register (when mod == 0).
           int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
           Print("[%s*%d", NameOfCPURegister(index), 1 << scale);
           PrintDisp(disp, "]");
           return 6;
         } else if (index != 4 && base != 5) {
           // [base+index*scale]
-          Print("[%s+%s*%d]",
-                NameOfCPURegister(base),
-                NameOfCPURegister(index),
+          Print("[%s+%s*%d]", NameOfCPURegister(base), NameOfCPURegister(index),
                 1 << scale);
           return 2;
         } else {
           UnimplementedInstruction();
           return 1;
         }
       } else {
         Print("[%s]", NameOfCPURegister(rm));
         return 1;
       }
       break;
     case 1:  // fall through
     case 2:
       if ((rm & 7) == 4) {
         uint8_t sib = *(modrmp + 1);
         int scale, index, base;
         get_sib(sib, &scale, &index, &base);
         int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 2)
                               : *reinterpret_cast<char*>(modrmp + 2);
         if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
           Print("[%s", NameOfCPURegister(base));
           PrintDisp(disp, "]");
         } else {
-          Print("[%s+%s*%d",
-                NameOfCPURegister(base),
-                NameOfCPURegister(index),
+          Print("[%s+%s*%d", NameOfCPURegister(base), NameOfCPURegister(index),
                 1 << scale);
           PrintDisp(disp, "]");
         }
         return mod == 2 ? 6 : 3;
       } else {
         // No sib.
         int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 1)
                               : *reinterpret_cast<char*>(modrmp + 1);
         Print("[%s", NameOfCPURegister(rm));
         PrintDisp(disp, "]");
@@ skipping 51 matching lines @@
 void DisassemblerX64::PrintDisp(int disp, const char* after) {
   if (-disp > 0) {
     Print("-%#x", -disp);
   } else {
     Print("+%#x", disp);
   }
   if (after != NULL) Print("%s", after);
 }
 
 
-
-
 // Returns number of bytes used by machine instruction, including *data byte.
 // Writes immediate instructions to 'tmp_buffer_'.
 int DisassemblerX64::PrintImmediateOp(uint8_t* data) {
   bool byte_size_immediate = (*data & 0x02) != 0;
   uint8_t modrm = *(data + 1);
   int mod, regop, rm;
   get_modrm(modrm, &mod, &regop, &rm);
   const char* mnem = "Imm???";
   switch (regop) {
     case 0:
@@ skipping 52 matching lines @@
         break;
       case 6:
         mnem = "div";
         break;
       case 7:
         mnem = "idiv";
         break;
       default:
         UnimplementedInstruction();
     }
-    Print("%s%c %s",
-          mnem,
-          operand_size_code(),
-          NameOfCPURegister(rm));
+    Print("%s%c %s", mnem, operand_size_code(), NameOfCPURegister(rm));
     return 2;
   } else if (regop == 0) {
     Print("test%c ", operand_size_code());
     int count = PrintRightOperand(data + 1);  // Use name of 64-bit register.
     Print(",");
     count += PrintImmediate(data + 1 + count, operand_size());
     return 1 + count;
   } else {
     UnimplementedInstruction();
     return 2;
@@ skipping 44 matching lines @@
       UnimplementedInstruction();
       return num_bytes;
   }
   ASSERT(NULL != mnem);
   if (op == 0xD0) {
     imm8 = 1;
   } else if (op == 0xC0) {
     imm8 = *(data + 2);
     num_bytes = 3;
   }
-  Print("%s%c %s,",
-        mnem,
-        operand_size_code(),
-        byte_size_operand_ ? NameOfByteCPURegister(rm)
-                           : NameOfCPURegister(rm));
+  Print("%s%c %s,", mnem, operand_size_code(),
+        byte_size_operand_ ? NameOfByteCPURegister(rm) : NameOfCPURegister(rm));
   if (op == 0xD2) {
     Print("cl");
   } else {
     Print("%d", imm8);
   }
   return num_bytes;
 }
 
 
 int DisassemblerX64::PrintRightOperand(uint8_t* modrmp) {
-  return PrintRightOperandHelper(modrmp,
-                                 &DisassemblerX64::NameOfCPURegister);
+  return PrintRightOperandHelper(modrmp, &DisassemblerX64::NameOfCPURegister);
 }
 
 
 int DisassemblerX64::PrintRightByteOperand(uint8_t* modrmp) {
   return PrintRightOperandHelper(modrmp,
                                  &DisassemblerX64::NameOfByteCPURegister);
 }
 
 
 int DisassemblerX64::PrintRightXMMOperand(uint8_t* modrmp) {
-  return PrintRightOperandHelper(modrmp,
-                                 &DisassemblerX64::NameOfXMMRegister);
+  return PrintRightOperandHelper(modrmp, &DisassemblerX64::NameOfXMMRegister);
 }
 
 
 // Returns number of bytes used including the current *data.
 // Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
 int DisassemblerX64::PrintOperands(const char* mnem,
                                    OperandType op_order,
                                    uint8_t* data) {
   uint8_t modrm = *data;
   int mod, regop, rm;
   get_modrm(modrm, &mod, &regop, &rm);
   int advance = 0;
-  const char* register_name =
-      byte_size_operand_ ? NameOfByteCPURegister(regop)
-                         : NameOfCPURegister(regop);
+  const char* register_name = byte_size_operand_ ? NameOfByteCPURegister(regop)
+                                                 : NameOfCPURegister(regop);
   switch (op_order) {
     case REG_OPER_OP_ORDER: {
       Print("%s%c %s,", mnem, operand_size_code(), register_name);
       advance = byte_size_operand_ ? PrintRightByteOperand(data)
                                    : PrintRightOperand(data);
       break;
     }
     case OPER_REG_OP_ORDER: {
       Print("%s%c ", mnem, operand_size_code());
       advance = byte_size_operand_ ? PrintRightByteOperand(data)
@@ skipping 58 matching lines @@
   Print("set%s%c ", mnem, operand_size_code());
   PrintRightByteOperand(data + 2);
   return 3;  // includes 0x0F
 }
 
 
 // Returns number of bytes used, including *data.
 int DisassemblerX64::FPUInstruction(uint8_t* data) {
   uint8_t escape_opcode = *data;
   ASSERT(0xD8 == (escape_opcode & 0xF8));
-  uint8_t modrm_byte = *(data+1);
+  uint8_t modrm_byte = *(data + 1);
 
   if (modrm_byte >= 0xC0) {
     return RegisterFPUInstruction(escape_opcode, modrm_byte);
   } else {
-    return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
+    return MemoryFPUInstruction(escape_opcode, modrm_byte, data + 1);
   }
 }
 
 
 int DisassemblerX64::MemoryFPUInstruction(int escape_opcode,
                                           int modrm_byte,
                                           uint8_t* modrm_start) {
   const char* mnem = "?";
   int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
   switch (escape_opcode) {
-    case 0xD9: switch (regop) {
-        case 0: mnem = "fld_s"; break;
-        case 3: mnem = "fstp_s"; break;
-        case 7: mnem = "fstcw"; break;
-        default: UnimplementedInstruction();
+    case 0xD9:
+      switch (regop) {
+        case 0:
+          mnem = "fld_s";
+          break;
+        case 3:
+          mnem = "fstp_s";
+          break;
+        case 7:
+          mnem = "fstcw";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
-    case 0xDB: switch (regop) {
-        case 0: mnem = "fild_s"; break;
-        case 1: mnem = "fisttp_s"; break;
-        case 2: mnem = "fist_s"; break;
-        case 3: mnem = "fistp_s"; break;
-        default: UnimplementedInstruction();
+    case 0xDB:
+      switch (regop) {
+        case 0:
+          mnem = "fild_s";
+          break;
+        case 1:
+          mnem = "fisttp_s";
+          break;
+        case 2:
+          mnem = "fist_s";
+          break;
+        case 3:
+          mnem = "fistp_s";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
-    case 0xDD: switch (regop) {
-        case 0: mnem = "fld_d"; break;
-        case 3: mnem = "fstp_d"; break;
-        default: UnimplementedInstruction();
+    case 0xDD:
+      switch (regop) {
+        case 0:
+          mnem = "fld_d";
+          break;
+        case 3:
+          mnem = "fstp_d";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
-    case 0xDF: switch (regop) {
-        case 5: mnem = "fild_d"; break;
-        case 7: mnem = "fistp_d"; break;
-        default: UnimplementedInstruction();
+    case 0xDF:
+      switch (regop) {
+        case 5:
+          mnem = "fild_d";
+          break;
+        case 7:
+          mnem = "fistp_d";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
-    default: UnimplementedInstruction();
+    default:
+      UnimplementedInstruction();
   }
   Print("%s ", mnem);
   int count = PrintRightOperand(modrm_start);
   return count + 1;
 }
 
 int DisassemblerX64::RegisterFPUInstruction(int escape_opcode,
                                             uint8_t modrm_byte) {
   bool has_register = false;  // Is the FPU register encoded in modrm_byte?
   const char* mnem = "?";
 
   switch (escape_opcode) {
     case 0xD8:
       UnimplementedInstruction();
       break;
 
     case 0xD9:
       switch (modrm_byte & 0xF8) {
         case 0xC0:
           mnem = "fld";
           has_register = true;
           break;
         case 0xC8:
           mnem = "fxch";
           has_register = true;
           break;
         default:
           switch (modrm_byte) {
-            case 0xE0: mnem = "fchs"; break;
-            case 0xE1: mnem = "fabs"; break;
-            case 0xE3: mnem = "fninit"; break;
-            case 0xE4: mnem = "ftst"; break;
-            case 0xE8: mnem = "fld1"; break;
-            case 0xEB: mnem = "fldpi"; break;
-            case 0xED: mnem = "fldln2"; break;
-            case 0xEE: mnem = "fldz"; break;
-            case 0xF0: mnem = "f2xm1"; break;
-            case 0xF1: mnem = "fyl2x"; break;
-            case 0xF2: mnem = "fptan"; break;
-            case 0xF5: mnem = "fprem1"; break;
-            case 0xF7: mnem = "fincstp"; break;
-            case 0xF8: mnem = "fprem"; break;
-            case 0xFD: mnem = "fscale"; break;
-            case 0xFE: mnem = "fsin"; break;
-            case 0xFF: mnem = "fcos"; break;
-            default: UnimplementedInstruction();
+            case 0xE0:
+              mnem = "fchs";
+              break;
+            case 0xE1:
+              mnem = "fabs";
+              break;
+            case 0xE3:
+              mnem = "fninit";
+              break;
+            case 0xE4:
+              mnem = "ftst";
+              break;
+            case 0xE8:
+              mnem = "fld1";
+              break;
+            case 0xEB:
+              mnem = "fldpi";
+              break;
+            case 0xED:
+              mnem = "fldln2";
+              break;
+            case 0xEE:
+              mnem = "fldz";
+              break;
+            case 0xF0:
+              mnem = "f2xm1";
+              break;
+            case 0xF1:
+              mnem = "fyl2x";
+              break;
+            case 0xF2:
+              mnem = "fptan";
+              break;
+            case 0xF5:
+              mnem = "fprem1";
+              break;
+            case 0xF7:
+              mnem = "fincstp";
+              break;
+            case 0xF8:
+              mnem = "fprem";
+              break;
+            case 0xFD:
+              mnem = "fscale";
+              break;
+            case 0xFE:
+              mnem = "fsin";
+              break;
+            case 0xFF:
+              mnem = "fcos";
+              break;
+            default:
+              UnimplementedInstruction();
           }
       }
       break;
 
     case 0xDA:
       if (modrm_byte == 0xE9) {
         mnem = "fucompp";
       } else {
         UnimplementedInstruction();
       }
       break;
 
     case 0xDB:
       if ((modrm_byte & 0xF8) == 0xE8) {
         mnem = "fucomi";
         has_register = true;
-      } else if (modrm_byte  == 0xE2) {
+      } else if (modrm_byte == 0xE2) {
         mnem = "fclex";
       } else {
         UnimplementedInstruction();
       }
       break;
 
     case 0xDC:
       has_register = true;
       switch (modrm_byte & 0xF8) {
-        case 0xC0: mnem = "fadd"; break;
-        case 0xE8: mnem = "fsub"; break;
-        case 0xC8: mnem = "fmul"; break;
-        case 0xF8: mnem = "fdiv"; break;
-        default: UnimplementedInstruction();
+        case 0xC0:
+          mnem = "fadd";
+          break;
+        case 0xE8:
+          mnem = "fsub";
+          break;
+        case 0xC8:
+          mnem = "fmul";
+          break;
+        case 0xF8:
+          mnem = "fdiv";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
     case 0xDD:
       has_register = true;
       switch (modrm_byte & 0xF8) {
-        case 0xC0: mnem = "ffree"; break;
-        case 0xD8: mnem = "fstp"; break;
-        default: UnimplementedInstruction();
+        case 0xC0:
+          mnem = "ffree";
+          break;
+        case 0xD8:
+          mnem = "fstp";
+          break;
+        default:
+          UnimplementedInstruction();
       }
       break;
 
     case 0xDE:
-      if (modrm_byte  == 0xD9) {
+      if (modrm_byte == 0xD9) {
         mnem = "fcompp";
       } else {
         has_register = true;
         switch (modrm_byte & 0xF8) {
-          case 0xC0: mnem = "faddp"; break;
-          case 0xE8: mnem = "fsubp"; break;
-          case 0xC8: mnem = "fmulp"; break;
-          case 0xF8: mnem = "fdivp"; break;
-          default: UnimplementedInstruction();
+          case 0xC0:
+            mnem = "faddp";
+            break;
+          case 0xE8:
+            mnem = "fsubp";
+            break;
+          case 0xC8:
+            mnem = "fmulp";
+            break;
+          case 0xF8:
+            mnem = "fdivp";
+            break;
+          default:
+            UnimplementedInstruction();
         }
       }
       break;
 
     case 0xDF:
       if (modrm_byte == 0xE0) {
         mnem = "fnstsw_ax";
       } else if ((modrm_byte & 0xF8) == 0xE8) {
         mnem = "fucomip";
         has_register = true;
       }
       break;
 
-    default: UnimplementedInstruction();
+    default:
+      UnimplementedInstruction();
   }
 
   if (has_register) {
     Print("%s st%d", mnem, modrm_byte & 0x7);
   } else {
     Print("%s", mnem);
   }
   return 2;
 }
 
@@ skipping 44 matching lines @@
     case TWO_OPERANDS_INSTR:
       (*data)++;
       (*data) += PrintOperands(idesc.mnem, idesc.op_order_, *data);
       break;
 
     case JUMP_CONDITIONAL_SHORT_INSTR:
       (*data) += JumpConditionalShort(*data);
       break;
 
     case REGISTER_INSTR:
-      Print("%s%c %s",
-            idesc.mnem,
-            operand_size_code(),
+      Print("%s%c %s", idesc.mnem, operand_size_code(),
             NameOfCPURegister(base_reg(current & 0x07)));
       (*data)++;
       break;
     case PUSHPOP_INSTR:
-      Print("%s %s",
-            idesc.mnem,
-            NameOfCPURegister(base_reg(current & 0x07)));
+      Print("%s %s", idesc.mnem, NameOfCPURegister(base_reg(current & 0x07)));
       (*data)++;
       break;
     case MOVE_REG_INSTR: {
       uint8_t* addr = NULL;
       switch (operand_size()) {
         case WORD_SIZE:
           addr = reinterpret_cast<uint8_t*>(
               *reinterpret_cast<int16_t*>(*data + 1));
           (*data) += 3;
           break;
         case DOUBLEWORD_SIZE:
           addr = reinterpret_cast<uint8_t*>(
               *reinterpret_cast<int32_t*>(*data + 1));
           (*data) += 5;
           break;
         case QUADWORD_SIZE:
           addr = reinterpret_cast<uint8_t*>(
               *reinterpret_cast<int64_t*>(*data + 1));
           (*data) += 9;
           break;
         default:
           UNREACHABLE();
       }
-      Print("mov%c %s,",
-            operand_size_code(),
+      Print("mov%c %s,", operand_size_code(),
             NameOfCPURegister(base_reg(current & 0x07)));
       PrintAddress(addr);
       break;
     }
 
     case CALL_JUMP_INSTR: {
       uint8_t* addr = *data + *reinterpret_cast<int32_t*>(*data + 1) + 5;
       Print("%s ", idesc.mnem);
       PrintAddress(addr);
       (*data) += 5;
@@ skipping 41 matching lines @@
       uint8_t third_byte = *current;
       current = data + 3;
       if (third_byte == 0x17) {
         get_modrm(*current, &mod, &regop, &rm);
         Print("extractps ");  // reg/m32, xmm, imm8
         current += PrintRightOperand(current);
         Print(", %s, %d", NameOfCPURegister(regop), (*current) & 3);
         current += 1;
       } else if (third_byte == 0x0b) {
         get_modrm(*current, &mod, &regop, &rm);
-         // roundsd xmm, xmm/m64, imm8
+        // roundsd xmm, xmm/m64, imm8
         Print("roundsd %s, ", NameOfCPURegister(regop));
         current += PrintRightOperand(current);
         Print(", %d", (*current) & 3);
         current += 1;
       } else {
         UnimplementedInstruction();
       }
     } else {
       get_modrm(*current, &mod, &regop, &rm);
       if (opcode == 0x1f) {
         current++;
         if (rm == 4) {  // SIB byte present.
           current++;
         }
         if (mod == 1) {  // Byte displacement.
           current += 1;
         } else if (mod == 2) {  // 32-bit displacement.
           current += 4;
         }  // else no immediate displacement.
         Print("nop");
       } else if (opcode == 0x28) {
         Print("movapd %s, ", NameOfXMMRegister(regop));
         current += PrintRightXMMOperand(current);
       } else if (opcode == 0x29) {
         Print("movapd ");
         current += PrintRightXMMOperand(current);
         Print(", %s", NameOfXMMRegister(regop));
       } else if (opcode == 0x6E) {
-        Print("mov%c %s,",
-              rex_w() ? 'q' : 'd',
-              NameOfXMMRegister(regop));
+        Print("mov%c %s,", rex_w() ? 'q' : 'd', NameOfXMMRegister(regop));
         current += PrintRightOperand(current);
       } else if (opcode == 0x6F) {
-        Print("movdqa %s,",
-              NameOfXMMRegister(regop));
+        Print("movdqa %s,", NameOfXMMRegister(regop));
         current += PrintRightXMMOperand(current);
       } else if (opcode == 0x7E) {
-        Print("mov%c ",
-              rex_w() ? 'q' : 'd');
+        Print("mov%c ", rex_w() ? 'q' : 'd');
         current += PrintRightOperand(current);
         Print(", %s", NameOfXMMRegister(regop));
       } else if (opcode == 0x7F) {
         Print("movdqa ");
         current += PrintRightXMMOperand(current);
         Print(", %s", NameOfXMMRegister(regop));
       } else if (opcode == 0xD6) {
         Print("movq ");
         current += PrintRightXMMOperand(current);
         Print(", %s", NameOfXMMRegister(regop));
       } else if (opcode == 0x50) {
         Print("movmskpd %s,", NameOfCPURegister(regop));
         current += PrintRightXMMOperand(current);
       } else {
         const char* mnemonic = "?";
         if (opcode == 0x14) {
           mnemonic = "unpcklpd";
         } else if (opcode == 0x15) {
           mnemonic = "unpckhpd";
         } else if (opcode == 0x54) {
           mnemonic = "andpd";
-        } else  if (opcode == 0x56) {
+        } else if (opcode == 0x56) {
           mnemonic = "orpd";
-        } else  if (opcode == 0x57) {
+        } else if (opcode == 0x57) {
           mnemonic = "xorpd";
         } else if (opcode == 0x2E) {
           mnemonic = "ucomisd";
         } else if (opcode == 0x2F) {
           mnemonic = "comisd";
         } else if (opcode == 0xFE) {
           mnemonic = "paddd";
         } else if (opcode == 0xFA) {
           mnemonic = "psubd";
         } else if (opcode == 0x58) {
@@ skipping 38 matching lines @@
       // CVTSI2SD: integer to XMM double conversion.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
       Print("%sd %s,", mnemonic, NameOfXMMRegister(regop));
       current += PrintRightOperand(current);
     } else if (opcode == 0x2C) {
       // CVTTSD2SI:
       // Convert with truncation scalar double-precision FP to integer.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
-      Print("cvttsd2si%c %s,",
-          operand_size_code(), NameOfCPURegister(regop));
+      Print("cvttsd2si%c %s,", operand_size_code(), NameOfCPURegister(regop));
       current += PrintRightXMMOperand(current);
     } else if (opcode == 0x2D) {
       // CVTSD2SI: Convert scalar double-precision FP to integer.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
-      Print("cvtsd2si%c %s,",
-          operand_size_code(), NameOfCPURegister(regop));
+      Print("cvtsd2si%c %s,", operand_size_code(), NameOfCPURegister(regop));
       current += PrintRightXMMOperand(current);
     } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
       // XMM arithmetic. Mnemonic was retrieved at the start of this function.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
       Print("%s %s,", mnemonic, NameOfXMMRegister(regop));
       current += PrintRightXMMOperand(current);
     } else {
       UnimplementedInstruction();
     }
@@ skipping 15 matching lines @@
       // CVTSI2SS: integer to XMM single conversion.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
       Print("%ss %s,", mnemonic, NameOfXMMRegister(regop));
       current += PrintRightOperand(current);
     } else if (opcode == 0x2C) {
       // CVTTSS2SI:
       // Convert with truncation scalar single-precision FP to dword integer.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
-      Print("cvttss2si%c %s,",
-            operand_size_code(), NameOfCPURegister(regop));
+      Print("cvttss2si%c %s,", operand_size_code(), NameOfCPURegister(regop));
       current += PrintRightXMMOperand(current);
     } else if (opcode == 0x5A) {
       // CVTSS2SD:
       // Convert scalar single-precision FP to scalar double-precision FP.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
       Print("cvtss2sd %s,", NameOfXMMRegister(regop));
       current += PrintRightXMMOperand(current);
     } else if (opcode == 0x7E) {
       int mod, regop, rm;
@@ skipping 66 matching lines @@
     current += PrintOperands(idesc.mnem, idesc.op_order_, current);
 
   } else if (opcode == 0x12 || opcode == 0x14 || opcode == 0x15 ||
              opcode == 0x16 || opcode == 0x51 || opcode == 0x52 ||
              opcode == 0x53 || opcode == 0x54 || opcode == 0x56 ||
              opcode == 0x57 || opcode == 0x58 || opcode == 0x59 ||
              opcode == 0x5A || opcode == 0x5C || opcode == 0x5D ||
              opcode == 0x5E || opcode == 0x5F) {
     const char* mnemonic = NULL;
     switch (opcode) {
-      case 0x12: mnemonic = "movhlps"; break;
-      case 0x14: mnemonic = "unpcklps"; break;
-      case 0x15: mnemonic = "unpckhps"; break;
-      case 0x16: mnemonic = "movlhps"; break;
-      case 0x51: mnemonic = "sqrtps"; break;
-      case 0x52: mnemonic = "rsqrtps"; break;
-      case 0x53: mnemonic = "rcpps"; break;
-      case 0x54: mnemonic = "andps"; break;
-      case 0x56: mnemonic = "orps"; break;
-      case 0x57: mnemonic = "xorps"; break;
-      case 0x58: mnemonic = "addps"; break;
-      case 0x59: mnemonic = "mulps"; break;
-      case 0x5A: mnemonic = "cvtsd2ss"; break;
-      case 0x5C: mnemonic = "subps"; break;
-      case 0x5D: mnemonic = "minps"; break;
-      case 0x5E: mnemonic = "divps"; break;
-      case 0x5F: mnemonic = "maxps"; break;
-      default: UNREACHABLE();
+      case 0x12:
+        mnemonic = "movhlps";
+        break;
+      case 0x14:
+        mnemonic = "unpcklps";
+        break;
+      case 0x15:
+        mnemonic = "unpckhps";
+        break;
+      case 0x16:
+        mnemonic = "movlhps";
+        break;
+      case 0x51:
+        mnemonic = "sqrtps";
+        break;
+      case 0x52:
+        mnemonic = "rsqrtps";
+        break;
+      case 0x53:
+        mnemonic = "rcpps";
+        break;
+      case 0x54:
+        mnemonic = "andps";
+        break;
+      case 0x56:
+        mnemonic = "orps";
+        break;
+      case 0x57:
+        mnemonic = "xorps";
+        break;
+      case 0x58:
+        mnemonic = "addps";
+        break;
+      case 0x59:
+        mnemonic = "mulps";
+        break;
+      case 0x5A:
+        mnemonic = "cvtsd2ss";
+        break;
+      case 0x5C:
+        mnemonic = "subps";
+        break;
+      case 0x5D:
+        mnemonic = "minps";
+        break;
+      case 0x5E:
+        mnemonic = "divps";
+        break;
+      case 0x5F:
+        mnemonic = "maxps";
+        break;
+      default:
+        UNREACHABLE();
     }
     int mod, regop, rm;
     get_modrm(*current, &mod, &regop, &rm);
     Print("%s %s, ", mnemonic, NameOfXMMRegister(regop));
     current += PrintRightXMMOperand(current);
   } else if (opcode == 0xC2 || opcode == 0xC6) {
     int mod, regop, rm;
     get_modrm(*current, &mod, &regop, &rm);
     if (opcode == 0xC2) {
       Print("cmpps %s, ", NameOfXMMRegister(regop));
@@ skipping 106 matching lines @@
 
   if (!processed) {
     switch (*data) {
       case 0xC2:
         Print("ret ");
         PrintImmediateValue(*reinterpret_cast<uint16_t*>(data + 1));
         data += 3;
         break;
 
       case 0xC8:
-        Print("enter %d, %d",
-              *reinterpret_cast<uint16_t*>(data + 1),
-              data[3]);
+        Print("enter %d, %d", *reinterpret_cast<uint16_t*>(data + 1), data[3]);
         data += 4;
         break;
 
       case 0x69:  // fall through
       case 0x6B: {
         int mod, regop, rm;
         get_modrm(*(data + 1), &mod, &regop, &rm);
-        int32_t imm = *data == 0x6B ? *(data + 2)
-            : *reinterpret_cast<int32_t*>(data + 2);
-        Print("imul%c %s,%s,",
-              operand_size_code(),
-              NameOfCPURegister(regop),
+        int32_t imm =
+            *data == 0x6B ? *(data + 2) : *reinterpret_cast<int32_t*>(data + 2);
+        Print("imul%c %s,%s,", operand_size_code(), NameOfCPURegister(regop),
               NameOfCPURegister(rm));
         PrintImmediateValue(imm);
         data += 2 + (*data == 0x6B ? 1 : 4);
         break;
       }
 
       case 0x81:  // fall through
       case 0x83:  // 0x81 with sign extension bit set
         data += PrintImmediateOp(data);
         break;
 
       case 0x0F:
         data += TwoByteOpcodeInstruction(data);
         break;
 
       case 0x8F: {
         data++;
         int mod, regop, rm;
         get_modrm(*data, &mod, &regop, &rm);
         if (regop == 0) {
           Print("pop ");
           data += PrintRightOperand(data);
         }
-      }
-        break;
+      } break;
 
       case 0xFF: {
         data++;
         int mod, regop, rm;
         get_modrm(*data, &mod, &regop, &rm);
         const char* mnem = NULL;
         switch (regop) {
           case 0:
             mnem = "inc";
             break;
@@ skipping 11 matching lines @@
             break;
           default:
             mnem = "???";
         }
         if (regop <= 1) {
           Print("%s%c ", mnem, operand_size_code());
         } else {
           Print("%s ", mnem);
         }
         data += PrintRightOperand(data);
-      }
-        break;
+      } break;
 
       case 0xC7:  // imm32, fall through
       case 0xC6:  // imm8
       {
         bool is_byte = *data == 0xC6;
         data++;
         if (is_byte) {
           Print("movb ");
           data += PrintRightByteOperand(data);
           int32_t imm = *data;
           Print(",");
           PrintImmediateValue(imm);
           data++;
         } else {
           Print("mov%c ", operand_size_code());
           data += PrintRightOperand(data);
           int32_t imm = *reinterpret_cast<int32_t*>(data);
           Print(",");
           PrintImmediateValue(imm);
           data += 4;
         }
-      }
-        break;
+      } break;
 
       case 0x80: {
         data++;
         Print("cmpb ");
         data += PrintRightByteOperand(data);
         int32_t imm = *data;
         Print(",");
         PrintImmediateValue(imm);
         data++;
-      }
-        break;
+      } break;
 
       case 0x88:  // 8bit, fall through
       case 0x89:  // 32bit
       {
         bool is_byte = *data == 0x88;
         int mod, regop, rm;
         data++;
         get_modrm(*data, &mod, &regop, &rm);
         if (is_byte) {
           Print("movb ");
           data += PrintRightByteOperand(data);
           Print(",%s", NameOfByteCPURegister(regop));
         } else {
           Print("mov%c ", operand_size_code());
           data += PrintRightOperand(data);
           Print(",%s", NameOfCPURegister(regop));
         }
-      }
-        break;
+      } break;
 
       case 0x90:
       case 0x91:
       case 0x92:
       case 0x93:
       case 0x94:
       case 0x95:
       case 0x96:
       case 0x97: {
         int reg = (*data & 0x7) | (rex_b() ? 8 : 0);
         if (reg == 0) {
           Print("nop");  // Common name for xchg rax,rax.
         } else {
           Print("xchg%c rax, %s", operand_size_code(), NameOfCPURegister(reg));
         }
         data++;
-      }
-        break;
+      } break;
       case 0xB0:
       case 0xB1:
       case 0xB2:
       case 0xB3:
       case 0xB4:
       case 0xB5:
       case 0xB6:
       case 0xB7:
       case 0xB8:
       case 0xB9:
@@ skipping 38 matching lines @@
       case 0x6A:
         Print("push ");
         PrintImmediateValue(*reinterpret_cast<int8_t*>(data + 1));
         data += 2;
         break;
 
       case 0xA1:  // Fall through.
       case 0xA3:
         switch (operand_size()) {
           case DOUBLEWORD_SIZE: {
-            PrintAddress(
-                reinterpret_cast<uint8_t*>(
-                    *reinterpret_cast<int32_t*>(data + 1)));
+            PrintAddress(reinterpret_cast<uint8_t*>(
+                *reinterpret_cast<int32_t*>(data + 1)));
             if (*data == 0xA1) {  // Opcode 0xA1
               Print("movzxlq rax,(");
-              PrintAddress(
-                  reinterpret_cast<uint8_t*>(
-                      *reinterpret_cast<int32_t*>(data + 1)));
+              PrintAddress(reinterpret_cast<uint8_t*>(
+                  *reinterpret_cast<int32_t*>(data + 1)));
               Print(")");
             } else {  // Opcode 0xA3
               Print("movzxlq (");
-              PrintAddress(
-                  reinterpret_cast<uint8_t*>(
-                      *reinterpret_cast<int32_t*>(data + 1)));
+              PrintAddress(reinterpret_cast<uint8_t*>(
+                  *reinterpret_cast<int32_t*>(data + 1)));
               Print("),rax");
-           }
+            }
             data += 5;
             break;
           }
           case QUADWORD_SIZE: {
             // New x64 instruction mov rax,(imm_64).
             if (*data == 0xA1) {  // Opcode 0xA1
               Print("movq rax,(");
               PrintAddress(*reinterpret_cast<uint8_t**>(data + 1));
               Print(")");
             } else {  // Opcode 0xA3
@@ skipping 78 matching lines @@
 
   ASSERT(buffer_[buffer_pos_] == '\0');
 
   int instr_len = data - reinterpret_cast<uint8_t*>(pc);
   ASSERT(instr_len > 0);  // Ensure progress.
 
   return instr_len;
 }
 
 
-void Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
-                                     char* human_buffer, intptr_t human_size,
-                                     int* out_instr_len, const Code& code,
-                                     Object** object, uword pc) {
+void Disassembler::DecodeInstruction(char* hex_buffer,
+                                     intptr_t hex_size,
+                                     char* human_buffer,
+                                     intptr_t human_size,
+                                     int* out_instr_len,
+                                     const Code& code,
+                                     Object** object,
+                                     uword pc) {
   ASSERT(hex_size > 0);
   ASSERT(human_size > 0);
   DisassemblerX64 decoder(human_buffer, human_size);
   int instruction_length = decoder.InstructionDecode(pc);
   uint8_t* pc_ptr = reinterpret_cast<uint8_t*>(pc);
   int hex_index = 0;
   int remaining_size = hex_size - hex_index;
   for (int i = 0; (i < instruction_length) && (remaining_size > 2); ++i) {
     OS::SNPrint(&hex_buffer[hex_index], remaining_size, "%02x", pc_ptr[i]);
     hex_index += 2;
@@ skipping 11 matching lines @@
       *object = NULL;
     }
   }
 }
 
 #endif  // !PRODUCT
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64