clang-format runtime/vm

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 #include "vm/instructions.h"
 
 namespace dart {
 
 #ifndef PRODUCT
 
 class ARM64Decoder : public ValueObject {
  public:
   ARM64Decoder(char* buffer, size_t buffer_size)
-      : buffer_(buffer),
-        buffer_size_(buffer_size),
-        buffer_pos_(0) {
+      : buffer_(buffer), buffer_size_(buffer_size), buffer_pos_(0) {
     buffer_[buffer_pos_] = '\0';
   }
 
   ~ARM64Decoder() {}
 
   // Writes one disassembled instruction into 'buffer' (0-terminated).
   // Returns true if the instruction was successfully decoded, false otherwise.
   void InstructionDecode(uword pc);
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg, R31Type r31t);
   void PrintVRegister(int reg);
   void PrintShiftExtendRm(Instr* instr);
   void PrintMemOperand(Instr* instr);
   void PrintPairMemOperand(Instr* instr);
   void PrintS(Instr* instr);
   void PrintCondition(Instr* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
-  int FormatVRegister(Instr*instr, const char* option);
+  int FormatVRegister(Instr* instr, const char* option);
   int FormatOption(Instr* instr, const char* format);
   void Format(Instr* instr, const char* format);
   void Unknown(Instr* instr);
 
-  // Decode instructions.
-  #define DECODE_OP(op)                                                        \
-    void Decode##op(Instr* instr);
+// Decode instructions.
+#define DECODE_OP(op) void Decode##op(Instr* instr);
   APPLY_OP_LIST(DECODE_OP)
-  #undef DECODE_OP
+#undef DECODE_OP
 
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
   char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
-  char* buffer_;  // Decode instructions into this buffer.
+  char* buffer_;        // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
-  size_t buffer_pos_;  // Current character position in buffer.
+  size_t buffer_pos_;   // Current character position in buffer.
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(ARM64Decoder);
 };
 
 
 // Support for assertions in the ARM64Decoder formatting functions.
-#define STRING_STARTS_WITH(string, compare_string) \
+#define STRING_STARTS_WITH(string, compare_string)                             \
   (strncmp(string, compare_string, strlen(compare_string)) == 0)
 
 
 // Append the str to the output buffer.
 void ARM64Decoder::Print(const char* str) {
   char cur = *str++;
   while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) {
     buffer_[buffer_pos_++] = cur;
     cur = *str++;
   }
   buffer_[buffer_pos_] = '\0';
 }
 
 
 // These register names are defined in a way to match the native disassembler
 // formatting, except for register aliases ctx (r9), pp (r10) and sp (r19).
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
-  "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
-  "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
-  "ip0", "ip1", "r18", "sp",  "r20", "r21", "r22", "r23",
-  "r24", "r25", "thr", "pp",  "ctx", "fp",  "lr",  "r31",
+    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8", "r9",  "r10",
+    "r11", "r12", "r13", "r14", "r15", "ip0", "ip1", "r18", "sp", "r20", "r21",
+    "r22", "r23", "r24", "r25", "thr", "pp",  "ctx", "fp",  "lr", "r31",
 };
 
 
 // Print the register name according to the active name converter.
 void ARM64Decoder::PrintRegister(int reg, R31Type r31t) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfCpuRegisters);
   if (reg == 31) {
     const char* rstr = (r31t == R31IsZR) ? "zr" : "csp";
     Print(rstr);
   } else {
     Print(reg_names[reg]);
   }
 }
 
 
 void ARM64Decoder::PrintVRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfVRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                             remaining_size_in_buffer(),
-                             "v%d", reg);
+                             remaining_size_in_buffer(), "v%d", reg);
 }
 
 
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
-static const char* shift_names[kMaxShift] = {
-  "lsl", "lsr", "asr", "ror"
-};
+static const char* shift_names[kMaxShift] = {"lsl", "lsr", "asr", "ror"};
 
 
 static const char* extend_names[kMaxExtend] = {
-  "uxtb", "uxth", "uxtw", "uxtx",
-  "sxtb", "sxth", "sxtw", "sxtx",
+    "uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx",
 };
 
 
 // These condition names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* cond_names[kMaxCondition] = {
-  "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
-  "hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
+    "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
+    "hi", "ls", "ge", "lt", "gt", "le", "",   "invalid",
 };
 
 
 // Print the condition guarding the instruction.
 void ARM64Decoder::PrintCondition(Instr* instr) {
   if (instr->IsConditionalSelectOp()) {
     Print(cond_names[instr->SelectConditionField()]);
   } else {
     Print(cond_names[instr->ConditionField()]);
   }
@@ skipping 16 matching lines @@
     return;
   }
   if (instr->IsShift()) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
       Print(" RRX");
       return;
     } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
       shift_amount = 32;
     }
-    buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                               remaining_size_in_buffer(),
-                               " %s #%d",
-                               shift_names[shift],
-                               shift_amount);
+    buffer_pos_ +=
+        OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                    " %s #%d", shift_names[shift], shift_amount);
   } else {
     ASSERT(instr->IsExtend());
     // by register
-    buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                               remaining_size_in_buffer(),
-                               " %s",
-                               extend_names[extend]);
+    buffer_pos_ +=
+        OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                    " %s", extend_names[extend]);
     if (((instr->SFField() == 1) && (extend == UXTX)) ||
         ((instr->SFField() == 0) && (extend == UXTW))) {
       // Shift amount.
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 " %d",
-                                 extend_shift_amount);
+      buffer_pos_ +=
+          OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                      " %d", extend_shift_amount);
     }
   }
 }
 
 
 void ARM64Decoder::PrintMemOperand(Instr* instr) {
   const Register rn = instr->RnField();
   if (instr->Bit(24) == 1) {
     // rn + scaled unsigned 12-bit immediate offset.
     const uint32_t scale = instr->SzField();
     const uint32_t imm12 = instr->Imm12Field();
     const uint32_t off = imm12 << scale;
     Print("[");
     PrintRegister(rn, R31IsSP);
     if (off != 0) {
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 ", #%d",
-                                 off);
+                                 remaining_size_in_buffer(), ", #%d", off);
     }
     Print("]");
   } else {
     switch (instr->Bits(10, 2)) {
       case 0: {
         // rn + signed 9-bit immediate, pre-index, no writeback.
         const int32_t imm9 = instr->SImm9Field();
         Print("[");
         PrintRegister(rn, R31IsSP);
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   ", #%d",
-                                   imm9);
+                                   remaining_size_in_buffer(), ", #%d", imm9);
         Print("]");
         break;
       }
       case 1: {
         const int32_t imm9 = instr->SImm9Field();
         // rn + signed 9-bit immediate, post-index, writeback.
         Print("[");
         PrintRegister(rn, R31IsSP);
         Print("]");
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   ", #%d !",
-                                   imm9);
+                                   remaining_size_in_buffer(), ", #%d !", imm9);
         break;
       }
       case 2: {
         const Register rm = instr->RmField();
         const Extend ext = instr->ExtendTypeField();
         const int s = instr->Bit(12);
         Print("[");
         PrintRegister(rn, R31IsSP);
         Print(", ");
         PrintRegister(rm, R31IsZR);
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   " %s",
-                                   extend_names[ext]);
+        buffer_pos_ +=
+            OS::SNPrint(current_position_in_buffer(),
+                        remaining_size_in_buffer(), " %s", extend_names[ext]);
         if (s == 1) {
           Print(" scaled");
         }
         Print("]");
         break;
       }
       case 3: {
         const int32_t imm9 = instr->SImm9Field();
         // rn + signed 9-bit immediate, pre-index, writeback.
         Print("[");
         PrintRegister(rn, R31IsSP);
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   ", #%d",
-                                   imm9);
+                                   remaining_size_in_buffer(), ", #%d", imm9);
         Print("] !");
         break;
       }
-      default: {
-        Print("???");
-      }
+      default: { Print("???"); }
     }
   }
 }
 
 
 void ARM64Decoder::PrintPairMemOperand(Instr* instr) {
   const Register rn = instr->RnField();
   const int32_t simm7 = instr->SImm7Field();
   const int32_t offset = simm7 << (2 + instr->Bit(31));
   Print("[");
   PrintRegister(rn, R31IsSP);
   switch (instr->Bits(23, 3)) {
     case 1:
       // rn + (imm7 << (2 + B31)), post-index, writeback.
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "], #%d !",
-                                 offset);
+      buffer_pos_ +=
+          OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                      "], #%d !", offset);
       break;
     case 2:
       // rn + (imm7 << (2 + B31)), pre-index, no writeback.
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 ", #%d ]",
-                                 offset);
+                                 remaining_size_in_buffer(), ", #%d ]", offset);
       break;
     case 3:
       // rn + (imm7 << (2 + B31)), pre-index, writeback.
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 ", #%d ]!",
-                                 offset);
+      buffer_pos_ +=
+          OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                      ", #%d ]!", offset);
       break;
     default:
       Print(", ???]");
       break;
   }
 }
 
 
 // Handle all register based formatting in these functions to reduce the
 // complexity of FormatOption.
@@ skipping 58 matching lines @@
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
 // characters that were consumed from the formatting string.
 int ARM64Decoder::FormatOption(Instr* instr, const char* format) {
   switch (format[0]) {
     case 'b': {
       if (format[3] == 'i') {
         ASSERT(STRING_STARTS_WITH(format, "bitimm"));
         const uint64_t imm = instr->ImmLogical();
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "0x%" Px64,
-                                   imm);
+                                   remaining_size_in_buffer(), "0x%" Px64, imm);
         return 6;
       } else {
         ASSERT(STRING_STARTS_WITH(format, "bitpos"));
         int bitpos = instr->Bits(19, 4) | (instr->Bit(31) << 5);
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "#%d",
-                                   bitpos);
+                                   remaining_size_in_buffer(), "#%d", bitpos);
         return 6;
       }
     }
     case 'c': {
       if (format[1] == 's') {
         ASSERT(STRING_STARTS_WITH(format, "csz"));
         const int32_t imm5 = instr->Bits(16, 5);
         char const* typ = "??";
         if (imm5 & 0x1) {
           typ = "b";
         } else if (imm5 & 0x2) {
           typ = "h";
         } else if (imm5 & 0x4) {
           typ = "s";
         } else if (imm5 & 0x8) {
           typ = "d";
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%s",
-                                   typ);
+                                   remaining_size_in_buffer(), "%s", typ);
         return 3;
       } else {
         ASSERT(STRING_STARTS_WITH(format, "cond"));
         PrintCondition(instr);
         return 4;
       }
     }
     case 'd': {
       if (format[4] == '2') {
         ASSERT(STRING_STARTS_WITH(format, "dest26"));
         int64_t off = instr->SImm26Field() << 2;
         uword destination = reinterpret_cast<uword>(instr) + off;
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%#" Px "",
-                                   destination);
+        buffer_pos_ +=
+            OS::SNPrint(current_position_in_buffer(),
+                        remaining_size_in_buffer(), "%#" Px "", destination);
       } else {
         if (format[5] == '4') {
           ASSERT(STRING_STARTS_WITH(format, "dest14"));
           int64_t off = instr->SImm14Field() << 2;
           uword destination = reinterpret_cast<uword>(instr) + off;
-          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "%#" Px "",
-                                     destination);
+          buffer_pos_ +=
+              OS::SNPrint(current_position_in_buffer(),
+                          remaining_size_in_buffer(), "%#" Px "", destination);
         } else {
           ASSERT(STRING_STARTS_WITH(format, "dest19"));
           int64_t off = instr->SImm19Field() << 2;
           uword destination = reinterpret_cast<uword>(instr) + off;
-          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "%#" Px "",
-                                     destination);
+          buffer_pos_ +=
+              OS::SNPrint(current_position_in_buffer(),
+                          remaining_size_in_buffer(), "%#" Px "", destination);
         }
       }
       return 6;
     }
     case 'f': {
       ASSERT(STRING_STARTS_WITH(format, "fsz"));
-        const int sz = instr->SzField();
-        char const* sz_str;
-        switch (sz) {
-          case 0:
-            if (instr->Bit(23) == 1) {
-              sz_str = "q";
-            } else {
-              sz_str = "b";
-            }
-            break;
-          case 1: sz_str = "h"; break;
-          case 2: sz_str = "s"; break;
-          case 3: sz_str = "d"; break;
-          default: sz_str = "?"; break;
-        }
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%s",
-                                   sz_str);
+      const int sz = instr->SzField();
+      char const* sz_str;
+      switch (sz) {
+        case 0:
+          if (instr->Bit(23) == 1) {
+            sz_str = "q";
+          } else {
+            sz_str = "b";
+          }
+          break;
+        case 1:
+          sz_str = "h";
+          break;
+        case 2:
+          sz_str = "s";
+          break;
+        case 3:
+          sz_str = "d";
+          break;
+        default:
+          sz_str = "?";
+          break;
+      }
+      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                 remaining_size_in_buffer(), "%s", sz_str);
       return 3;
     }
     case 'h': {
       ASSERT(STRING_STARTS_WITH(format, "hw"));
       const int shift = instr->HWField() << 4;
       if (shift != 0) {
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "lsl %d",
-                                   shift);
+                                   remaining_size_in_buffer(), "lsl %d", shift);
       }
       return 2;
     }
     case 'i': {  // 'imm12, 'imm16, 'immd
       if (format[1] == 'd') {
         // Element index for a SIMD copy instruction.
         ASSERT(STRING_STARTS_WITH(format, "idx"));
         const int32_t imm4 = instr->Bits(11, 4);
         const int32_t imm5 = instr->Bits(16, 5);
         int32_t shift = 0;
         int32_t imm = -1;
         if (format[3] == '4') {
           imm = imm4;
         } else if (format[3] == '5') {
           imm = imm5;
           shift = 1;
         }
         int32_t idx = -1;
         if (imm5 & 0x1) {
           idx = imm >> shift;
         } else if (imm5 & 0x2) {
           idx = imm >> (shift + 1);
         } else if (imm5 & 0x4) {
           idx = imm >> (shift + 2);
         } else if (imm5 & 0x8) {
           idx = imm >> (shift + 3);
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "[%d]",
-                                   idx);
+                                   remaining_size_in_buffer(), "[%d]", idx);
         return 4;
       } else if (format[3] == '1') {
         uint64_t imm;
         int ret = 5;
         if (format[4] == '2') {
           ASSERT(STRING_STARTS_WITH(format, "imm12"));
           imm = instr->Imm12Field();
           if (format[5] == 's') {
             // shifted immediate.
             if (instr->Imm12ShiftField() == 1) {
               imm = imm << 12;
             } else if ((instr->Imm12ShiftField() & 0x2) != 0) {
               Print("Unknown Shift");
             }
             ret = 6;
           }
         } else {
           ASSERT(STRING_STARTS_WITH(format, "imm16"));
           imm = instr->Imm16Field();
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "0x%" Px64,
-                                   imm);
+                                   remaining_size_in_buffer(), "0x%" Px64, imm);
         return ret;
       } else {
         ASSERT(STRING_STARTS_WITH(format, "immd"));
-        double dimm = bit_cast<double, int64_t>(
-            Instr::VFPExpandImm(instr->Imm8Field()));
+        double dimm =
+            bit_cast<double, int64_t>(Instr::VFPExpandImm(instr->Imm8Field()));
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%f",
-                                   dimm);
+                                   remaining_size_in_buffer(), "%f", dimm);
         return 4;
       }
     }
     case 'm': {
       ASSERT(STRING_STARTS_WITH(format, "memop"));
       PrintMemOperand(instr);
       return 5;
     }
     case 'p': {
       if (format[1] == 'c') {
         if (format[2] == 'a') {
           ASSERT(STRING_STARTS_WITH(format, "pcadr"));
           const int64_t immhi = instr->SImm19Field();
           const int64_t immlo = instr->Bits(29, 2);
           const int64_t off = (immhi << 2) | immlo;
           const int64_t pc = reinterpret_cast<int64_t>(instr);
           const int64_t dest = pc + off;
-          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "0x%" Px64,
-                                     dest);
+          buffer_pos_ +=
+              OS::SNPrint(current_position_in_buffer(),
+                          remaining_size_in_buffer(), "0x%" Px64, dest);
         } else {
           ASSERT(STRING_STARTS_WITH(format, "pcldr"));
           const int64_t off = instr->SImm19Field() << 2;
           const int64_t pc = reinterpret_cast<int64_t>(instr);
           const int64_t dest = pc + off;
-          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "0x%" Px64,
-                                     dest);
+          buffer_pos_ +=
+              OS::SNPrint(current_position_in_buffer(),
+                          remaining_size_in_buffer(), "0x%" Px64, dest);
         }
         return 5;
       } else {
         ASSERT(STRING_STARTS_WITH(format, "pmemop"));
         PrintPairMemOperand(instr);
         return 6;
       }
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
     case 'v': {
       if (format[1] == 's') {
         ASSERT(STRING_STARTS_WITH(format, "vsz"));
         char const* sz_str = NULL;
         if (instr->Bits(14, 2) == 3) {
           switch (instr->Bit(22)) {
-            case 0: sz_str = "s"; break;
-            case 1: sz_str = "d"; break;
-            default: UNREACHABLE(); break;
+            case 0:
+              sz_str = "s";
+              break;
+            case 1:
+              sz_str = "d";
+              break;
+            default:
+              UNREACHABLE();
+              break;
           }
         } else {
           switch (instr->Bit(22)) {
-            case 0: sz_str = "w"; break;
-            case 1: sz_str = "x"; break;
-            default: UNREACHABLE(); break;
+            case 0:
+              sz_str = "w";
+              break;
+            case 1:
+              sz_str = "x";
+              break;
+            default:
+              UNREACHABLE();
+              break;
           }
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%s",
-                                   sz_str);
+                                   remaining_size_in_buffer(), "%s", sz_str);
         return 3;
       } else {
         return FormatVRegister(instr, format);
       }
     }
     case 's': {  // 's: S flag.
       if (format[1] == 'h') {
         ASSERT(STRING_STARTS_WITH(format, "shift_op"));
         PrintShiftExtendRm(instr);
         return 8;
       } else if (format[1] == 'f') {
         ASSERT(STRING_STARTS_WITH(format, "sf"));
         if (instr->SFField() == 1) {
           // TODO(zra): If we don't use the w form much, we can omit printing
           // this x.
           Print("x");
         } else {
           Print("w");
         }
         return 2;
       } else if (format[1] == 'z') {
         ASSERT(STRING_STARTS_WITH(format, "sz"));
         const int sz = instr->SzField();
         char const* sz_str;
         switch (sz) {
-          case 0: sz_str = "b"; break;
-          case 1: sz_str = "h"; break;
-          case 2: sz_str = "w"; break;
-          case 3: sz_str = "x"; break;
-          default: sz_str = "?"; break;
+          case 0:
+            sz_str = "b";
+            break;
+          case 1:
+            sz_str = "h";
+            break;
+          case 2:
+            sz_str = "w";
+            break;
+          case 3:
+            sz_str = "x";
+            break;
+          default:
+            sz_str = "?";
+            break;
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%s",
-                                   sz_str);
+                                   remaining_size_in_buffer(), "%s", sz_str);
         return 2;
       } else if (format[1] == ' ') {
         if (instr->HasS()) {
           Print("s");
         }
         return 1;
       } else {
         UNREACHABLE();
       }
     }
@@ skipping 13 matching lines @@
 void ARM64Decoder::Format(Instr* instr, const char* format) {
   char cur = *format++;
   while ((cur != 0) && (buffer_pos_ < (buffer_size_ - 1))) {
     if (cur == '\'') {  // Single quote is used as the formatting escape.
       format += FormatOption(instr, format);
     } else {
       buffer_[buffer_pos_++] = cur;
     }
     cur = *format++;
   }
-  buffer_[buffer_pos_]  = '\0';
+  buffer_[buffer_pos_] = '\0';
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARM64Decoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
 
@@ skipping 52 matching lines @@
   }
   if (instr->Bit(30)) {
     Format(instr, "ldrx 'rt, 'pcldr");
   } else {
     Format(instr, "ldrw 'rt, 'pcldr");
   }
 }
 
 
 void ARM64Decoder::DecodeLoadStoreExclusive(Instr* instr) {
-  if ((instr->Bit(23) != 0) ||
-      (instr->Bit(21) != 0) ||
-      (instr->Bit(15) != 0)) {
+  if ((instr->Bit(23) != 0) || (instr->Bit(21) != 0) || (instr->Bit(15) != 0)) {
     Unknown(instr);
   }
   const int32_t size = instr->Bits(30, 2);
   if (size != 3) {
     Unknown(instr);
   }
 
   const bool is_load = instr->Bit(22) == 1;
   if (is_load) {
     Format(instr, "ldxr 'rt, 'rn");
@@ skipping 88 matching lines @@
 void ARM64Decoder::DecodeExceptionGen(Instr* instr) {
   if ((instr->Bits(0, 2) == 1) && (instr->Bits(2, 3) == 0) &&
       (instr->Bits(21, 3) == 0)) {
     Format(instr, "svc 'imm16");
   } else if ((instr->Bits(0, 2) == 0) && (instr->Bits(2, 3) == 0) &&
              (instr->Bits(21, 3) == 1)) {
     Format(instr, "brk 'imm16");
     if (instr->Imm16Field() == Instr::kStopMessageCode) {
       const char* message = *reinterpret_cast<const char**>(
           reinterpret_cast<intptr_t>(instr) - 2 * Instr::kInstrSize);
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 " ; \"%s\"",
-                                 message);
+      buffer_pos_ +=
+          OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                      " ; \"%s\"", message);
     }
   } else if ((instr->Bits(0, 2) == 0) && (instr->Bits(2, 3) == 0) &&
              (instr->Bits(21, 3) == 2)) {
     Format(instr, "hlt 'imm16");
   } else {
     Unknown(instr);
   }
 }
 
 
@@ skipping 304 matching lines @@
   const int32_t Q = instr->Bit(30);
   const int32_t op = instr->Bit(29);
   const int32_t imm4 = instr->Bits(11, 4);
 
   if ((op == 0) && (imm4 == 7)) {
     if (Q == 0) {
       Format(instr, "vmovrs 'rd, 'vn'idx5");
     } else {
       Format(instr, "vmovrd 'rd, 'vn'idx5");
     }
-  } else if ((Q == 1)  && (op == 0) && (imm4 == 0)) {
+  } else if ((Q == 1) && (op == 0) && (imm4 == 0)) {
     Format(instr, "vdup'csz 'vd, 'vn'idx5");
   } else if ((Q == 1) && (op == 0) && (imm4 == 3)) {
     Format(instr, "vins'csz 'vd'idx5, 'rn");
   } else if ((Q == 1) && (op == 0) && (imm4 == 1)) {
     Format(instr, "vdup'csz 'vd, 'rn");
   } else if ((Q == 1) && (op == 1)) {
     Format(instr, "vins'csz 'vd'idx5, 'vn'idx4");
   } else {
     Unknown(instr);
   }
@@ skipping 279 matching lines @@
   } else if (instr->IsDPSimd1Op()) {
     DecodeDPSimd1(instr);
   } else if (instr->IsDPSimd2Op()) {
     DecodeDPSimd2(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
-void Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
-                                     char* human_buffer, intptr_t human_size,
-                                     int* out_instr_size, const Code& code,
-                                     Object** object, uword pc) {
+void Disassembler::DecodeInstruction(char* hex_buffer,
+                                     intptr_t hex_size,
+                                     char* human_buffer,
+                                     intptr_t human_size,
+                                     int* out_instr_size,
+                                     const Code& code,
+                                     Object** object,
+                                     uword pc) {
   ARM64Decoder decoder(human_buffer, human_size);
   decoder.InstructionDecode(pc);
   int32_t instruction_bits = Instr::At(pc)->InstructionBits();
   OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
   if (out_instr_size) {
     *out_instr_size = Instr::kInstrSize;
   }
 
   *object = NULL;
   if (!code.IsNull()) {
     *object = &Object::Handle();
     if (!DecodeLoadObjectFromPoolOrThread(pc, code, *object)) {
       *object = NULL;
     }
   }
 }
 
 #endif  // !PRODUCT
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM