clang-format runtime/vm

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 #include "platform/assert.h"
 #include "vm/cpu.h"
 #include "vm/instructions.h"
 
 namespace dart {
 
 #ifndef PRODUCT
 
 class ARMDecoder : public ValueObject {
  public:
   ARMDecoder(char* buffer, size_t buffer_size)
-      : buffer_(buffer),
-        buffer_size_(buffer_size),
-        buffer_pos_(0) {
+      : buffer_(buffer), buffer_size_(buffer_size), buffer_pos_(0) {
     buffer_[buffer_pos_] = '\0';
   }
 
   ~ARMDecoder() {}
 
   // Writes one disassembled instruction into 'buffer' (0-terminated).
   // Returns true if the instruction was successfully decoded, false otherwise.
   void InstructionDecode(uword pc);
 
  private:
@@ skipping 31 matching lines @@
   void DecodeType5(Instr* instr);
   void DecodeType6(Instr* instr);
   void DecodeType7(Instr* instr);
   void DecodeSIMDDataProcessing(Instr* instr);
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
   char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
-  char* buffer_;  // Decode instructions into this buffer.
+  char* buffer_;        // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
-  size_t buffer_pos_;  // Current character position in buffer.
+  size_t buffer_pos_;   // Current character position in buffer.
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(ARMDecoder);
 };
 
 
 // Support for assertions in the ARMDecoder formatting functions.
-#define STRING_STARTS_WITH(string, compare_string) \
+#define STRING_STARTS_WITH(string, compare_string)                             \
   (strncmp(string, compare_string, strlen(compare_string)) == 0)
 
 
 // Append the str to the output buffer.
 void ARMDecoder::Print(const char* str) {
   char cur = *str++;
   while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) {
     buffer_[buffer_pos_++] = cur;
     cur = *str++;
   }
   buffer_[buffer_pos_] = '\0';
 }
 
 
 // These condition names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* cond_names[kMaxCondition] = {
-  "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
-  "hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
+    "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
+    "hi", "ls", "ge", "lt", "gt", "le", "",   "invalid",
 };
 
 
 // Print the condition guarding the instruction.
 void ARMDecoder::PrintCondition(Instr* instr) {
   Print(cond_names[instr->ConditionField()]);
 }
 
 
 // These register names are defined in a way to match the native disassembler
 // formatting, except for register alias pp (r5).
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
 #if defined(TARGET_ABI_IOS)
-  "r0", "r1", "r2", "r3", "r4", "pp", "r6", "fp",
-  "r8", "r9", "thr", "r11", "ip", "sp", "lr", "pc",
+    "r0", "r1", "r2",  "r3",  "r4", "pp", "r6", "fp",
+    "r8", "r9", "thr", "r11", "ip", "sp", "lr", "pc",
 #elif defined(TARGET_ABI_EABI)
-  "r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
-  "r8", "r9", "thr", "fp", "ip", "sp", "lr", "pc",
+    "r0", "r1", "r2",  "r3", "r4", "pp", "r6", "r7",
+    "r8", "r9", "thr", "fp", "ip", "sp", "lr", "pc",
 #else
 #error Unknown ABI
 #endif
 };
 
 
 // Print the register name according to the active name converter.
 void ARMDecoder::PrintRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfCpuRegisters);
   Print(reg_names[reg]);
 }
 
 
 void ARMDecoder::PrintSRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfSRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                             remaining_size_in_buffer(),
-                             "s%d", reg);
+                             remaining_size_in_buffer(), "s%d", reg);
 }
 
 
 void ARMDecoder::PrintDRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfDRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                             remaining_size_in_buffer(),
-                             "d%d", reg);
+                             remaining_size_in_buffer(), "d%d", reg);
 }
 
 
 void ARMDecoder::PrintQRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfQRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                             remaining_size_in_buffer(),
-                             "q%d", reg);
+                             remaining_size_in_buffer(), "q%d", reg);
 }
 
 
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
-static const char* shift_names[kMaxShift] = {
-  "lsl", "lsr", "asr", "ror"
-};
+static const char* shift_names[kMaxShift] = {"lsl", "lsr", "asr", "ror"};
 
 
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
 void ARMDecoder::PrintShiftRm(Instr* instr) {
   Shift shift = instr->ShiftField();
   int shift_amount = instr->ShiftAmountField();
   int rm = instr->RmField();
 
   PrintRegister(rm);
 
   if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
     // Special case for using rm only.
     return;
   }
   if (instr->RegShiftField() == 0) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
       Print(", RRX");
       return;
     } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
       shift_amount = 32;
     }
-    buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                               remaining_size_in_buffer(),
-                               ", %s #%d",
-                               shift_names[shift],
-                               shift_amount);
+    buffer_pos_ +=
+        OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                    ", %s #%d", shift_names[shift], shift_amount);
   } else {
     // by register
     int rs = instr->RsField();
-    buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                               remaining_size_in_buffer(),
-                              ", %s ",
-                              shift_names[shift]);
+    buffer_pos_ +=
+        OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
+                    ", %s ", shift_names[shift]);
     PrintRegister(rs);
   }
 }
 
 
 // Print the immediate operand for the instruction. Generally used for data
 // processing instructions.
 void ARMDecoder::PrintShiftImm(Instr* instr) {
   int rotate = instr->RotateField() * 2;
   int immed8 = instr->Immed8Field();
   int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                             remaining_size_in_buffer(),
-                             "#%d",
-                             imm);
+                             remaining_size_in_buffer(), "#%d", imm);
 }
 
 
 // Print PU formatting to reduce complexity of FormatOption.
 void ARMDecoder::PrintPU(Instr* instr) {
   switch (instr->PUField()) {
     case 0: {
       Print("da");
       break;
     }
@@ skipping 201 matching lines @@
     case 'c': {  // 'cond: conditional execution
       ASSERT(STRING_STARTS_WITH(format, "cond"));
       PrintCondition(instr);
       return 4;
     }
     case 'd': {
       if (format[1] == 'e') {  // 'dest: branch destination
         ASSERT(STRING_STARTS_WITH(format, "dest"));
         int off = (instr->SImmed24Field() << 2) + 8;
         uword destination = reinterpret_cast<uword>(instr) + off;
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%#" Px "",
-                                   destination);
+        buffer_pos_ +=
+            OS::SNPrint(current_position_in_buffer(),
+                        remaining_size_in_buffer(), "%#" Px "", destination);
         return 4;
       } else {
         return FormatDRegister(instr, format);
       }
     }
     case 'q': {
       return FormatQRegister(instr, format);
     }
     case 'i': {  // 'imm12_4, imm4_12, immf, or immd
       uint16_t immed16;
       if (format[3] == 'f') {
         ASSERT(STRING_STARTS_WITH(format, "immf"));
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%f",
+                                   remaining_size_in_buffer(), "%f",
                                    instr->ImmFloatField());
         return 4;
       } else if (format[3] == 'd') {
         ASSERT(STRING_STARTS_WITH(format, "immd"));
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%g",
+                                   remaining_size_in_buffer(), "%g",
                                    instr->ImmDoubleField());
         return 4;
       } else if (format[3] == '1') {
         ASSERT(STRING_STARTS_WITH(format, "imm12_4"));
         immed16 = instr->BkptField();
       } else {
         ASSERT(format[3] == '4');
         if (format[5] == 'v') {
           ASSERT(STRING_STARTS_WITH(format, "imm4_vdup"));
           int32_t idx = -1;
           int32_t imm4 = instr->Bits(16, 4);
-          if ((imm4 & 1) != 0) idx = imm4 >> 1;
-          else if ((imm4 & 2) != 0) idx = imm4 >> 2;
-          else if ((imm4 & 4) != 0) idx = imm4 >> 3;
+          if ((imm4 & 1) != 0)
+            idx = imm4 >> 1;
+          else if ((imm4 & 2) != 0)
+            idx = imm4 >> 2;
+          else if ((imm4 & 4) != 0)
+            idx = imm4 >> 3;
           buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "%d",
-                                     idx);
+                                     remaining_size_in_buffer(), "%d", idx);
           return 9;
         } else {
           ASSERT(STRING_STARTS_WITH(format, "imm4_12"));
           immed16 = instr->MovwField();
         }
       }
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "0x%x",
-                                 immed16);
+                                 remaining_size_in_buffer(), "0x%x", immed16);
       return 7;
     }
     case 'l': {  // 'l: branch and link
       if (instr->HasLink()) {
         Print("l");
       }
       return 1;
     }
     case 'm': {  // 'memop: load/store instructions
       ASSERT(STRING_STARTS_WITH(format, "memop"));
       if (instr->HasL() ||
           // Extra load/store instructions.
           ((instr->TypeField() == 0) && instr->HasSign() && !instr->HasH())) {
         Print("ldr");
       } else {
         Print("str");
       }
       return 5;
     }
     case 'o': {
       if (format[3] == '1') {
         if (format[4] == '0') {
           // 'off10: 10-bit offset for VFP load and store instructions
           buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "%d",
+                                     remaining_size_in_buffer(), "%d",
                                      instr->Bits(0, 8) << 2);
         } else {
           // 'off12: 12-bit offset for load and store instructions.
           ASSERT(STRING_STARTS_WITH(format, "off12"));
           buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                     remaining_size_in_buffer(),
-                                     "%d",
+                                     remaining_size_in_buffer(), "%d",
                                      instr->Offset12Field());
         }
         return 5;
       }
       // 'off8: 8-bit offset for extra load and store instructions.
       ASSERT(STRING_STARTS_WITH(format, "off8"));
       int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "%d",
-                                 offs8);
+                                 remaining_size_in_buffer(), "%d", offs8);
       return 4;
     }
     case 'p': {  // 'pu: P and U bits for load and store instructions.
       ASSERT(STRING_STARTS_WITH(format, "pu"));
       PrintPU(instr);
       return 2;
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
     case 's': {
-      if (format[1] == 'h') {  // 'shift_op or 'shift_rm
+      if (format[1] == 'h') {    // 'shift_op or 'shift_rm
         if (format[6] == 'o') {  // 'shift_op
           ASSERT(STRING_STARTS_WITH(format, "shift_op"));
           if (instr->TypeField() == 0) {
             PrintShiftRm(instr);
           } else {
             ASSERT(instr->TypeField() == 1);
             PrintShiftImm(instr);
           }
           return 8;
         } else {  // 'shift_rm
           ASSERT(STRING_STARTS_WITH(format, "shift_rm"));
           PrintShiftRm(instr);
           return 8;
         }
       } else if (format[1] == 'v') {  // 'svc
         ASSERT(STRING_STARTS_WITH(format, "svc"));
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "0x%x",
-                                   instr->SvcField());
+        buffer_pos_ +=
+            OS::SNPrint(current_position_in_buffer(),
+                        remaining_size_in_buffer(), "0x%x", instr->SvcField());
         return 3;
       } else if (format[1] == 'z') {
         // 'sz: Size field of SIMD instructions.
         int sz = instr->Bits(20, 2);
         char const* sz_str;
         switch (sz) {
-          case 0: sz_str = "b"; break;
-          case 1: sz_str = "h"; break;
-          case 2: sz_str = "w"; break;
-          case 3: sz_str = "l"; break;
-          default: sz_str = "?"; break;
+          case 0:
+            sz_str = "b";
+            break;
+          case 1:
+            sz_str = "h";
+            break;
+          case 2:
+            sz_str = "w";
+            break;
+          case 3:
+            sz_str = "l";
+            break;
+          default:
+            sz_str = "?";
+            break;
         }
         buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "%s",
-                                   sz_str);
+                                   remaining_size_in_buffer(), "%s", sz_str);
         return 2;
       } else if (format[1] == ' ') {
         // 's: S field of data processing instructions.
         if (instr->HasS()) {
           Print("s");
         }
         return 1;
       } else {
         return FormatSRegister(instr, format);
       }
     }
     case 't': {  // 'target: target of branch instructions.
       ASSERT(STRING_STARTS_WITH(format, "target"));
       int off = (instr->SImmed24Field() << 2) + 8;
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "%+d",
-                                 off);
+                                 remaining_size_in_buffer(), "%+d", off);
       return 6;
     }
     case 'u': {  // 'u: signed or unsigned multiplies.
       if (instr->Bit(22) == 0) {
         Print("u");
       } else {
         Print("s");
       }
       return 1;
     }
@@ skipping 33 matching lines @@
 void ARMDecoder::Format(Instr* instr, const char* format) {
   char cur = *format++;
   while ((cur != 0) && (buffer_pos_ < (buffer_size_ - 1))) {
     if (cur == '\'') {  // Single quote is used as the formatting escape.
       format += FormatOption(instr, format);
     } else {
       buffer_[buffer_pos_++] = cur;
     }
     cur = *format++;
   }
-  buffer_[buffer_pos_]  = '\0';
+  buffer_[buffer_pos_] = '\0';
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARMDecoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
 
@@ skipping 20 matching lines @@
             Unknown(instr);
           }
           break;
         }
         case 7: {
           if ((instr->Bits(21, 2) == 0x1) && (instr->ConditionField() == AL)) {
             Format(instr, "bkpt #'imm12_4");
             if (instr->BkptField() == Instr::kStopMessageCode) {
               const char* message = *reinterpret_cast<const char**>(
                   reinterpret_cast<intptr_t>(instr) - Instr::kInstrSize);
-              buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                         remaining_size_in_buffer(),
-                                         " ; \"%s\"",
-                                         message);
+              buffer_pos_ +=
+                  OS::SNPrint(current_position_in_buffer(),
+                              remaining_size_in_buffer(), " ; \"%s\"", message);
             }
           } else {
-             // Format(instr, "smc'cond");
+            // Format(instr, "smc'cond");
             Unknown(instr);  // Not used.
           }
           break;
         }
         default: {
           Unknown(instr);  // Not used.
           break;
         }
       }
     } else if (instr->IsMultiplyOrSyncPrimitive()) {
@@ skipping 342 matching lines @@
       } else {
         Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd, 'rn");
       }
     } else {
       if (instr->Bit(20) == 1) {
         Format(instr, "vmovrrd'cond 'rd, 'rn, 'dm");
       } else {
         Format(instr, "vmovdrr'cond 'dm, 'rd, 'rn");
       }
     }
-  } else if (instr-> IsVFPLoadStore()) {
+  } else if (instr->IsVFPLoadStore()) {
     if (instr->Bit(8) == 0) {
       if (instr->Bit(20) == 1) {  // vldrs
         if (instr->Bit(23) == 1) {
           Format(instr, "vldrs'cond 'sd, ['rn, #+'off10]");
         } else {
           Format(instr, "vldrs'cond 'sd, ['rn, #-'off10]");
         }
       } else {  // vstrs
         if (instr->Bit(23) == 1) {
           Format(instr, "vstrs'cond 'sd, ['rn, #+'off10]");
@@ skipping 10 matching lines @@
         }
       } else {  // vstrd
         if (instr->Bit(23) == 1) {
           Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]");
         } else {
           Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]");
         }
       }
     }
   } else if (instr->IsVFPMultipleLoadStore()) {
-    if (instr->HasL()) {  // vldm
+    if (instr->HasL()) {    // vldm
       if (instr->Bit(8)) {  // vldmd
         Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
       } else {  // vldms
         Format(instr, "vldms'cond'pu 'rn'w, 'slist");
       }
-    } else {  // vstm
+    } else {                // vstm
       if (instr->Bit(8)) {  // vstmd
         Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
       } else {  // vstms
         Format(instr, "vstms'cond'pu 'rn'w, 'slist");
       }
     }
   } else {
     Unknown(instr);
   }
 }
@@ skipping 52 matching lines @@
             }
           } else {
             if (instr->Bit(6) == 0) {
               Format(instr, "vaddd'cond 'dd, 'dn, 'dm");
             } else {
               Format(instr, "vsubd'cond 'dd, 'dn, 'dm");
             }
           }
           break;
         }
-        case 0xb: {  // Other VFP data-processing instructions
+        case 0xb: {                  // Other VFP data-processing instructions
           if (instr->Bit(6) == 0) {  // vmov immediate
             if (instr->Bit(8) == 0) {
               Format(instr, "vmovs'cond 'sd, #'immf");
             } else {
               Format(instr, "vmovd'cond 'dd, #'immd");
             }
             break;
           }
           switch (instr->Bits(16, 4)) {
             case 0: {  // vmov register, vabs
@@ skipping 39 matching lines @@
                   }
                   break;
                 }
                 default: {
                   Unknown(instr);
                   break;
                 }
               }
               break;
             }
-            case 4:  // vcmp, vcmpe
-            case 5: {  // vcmp #0.0, vcmpe #0.0
+            case 4:                      // vcmp, vcmpe
+            case 5: {                    // vcmp #0.0, vcmpe #0.0
               if (instr->Bit(7) == 1) {  // vcmpe
                 Unknown(instr);
               } else {
                 if (instr->Bit(8) == 0) {  // vcmps
                   if (instr->Bit(16) == 0) {
                     Format(instr, "vcmps'cond 'sd, 'sm");
                   } else {
                     Format(instr, "vcmps'cond 'sd, #0.0");
                   }
                 } else {  // vcmpd
@@ skipping 45 matching lines @@
                 }
               } else {
                 if (instr->Bit(16) == 0) {
                   Format(instr, "vcvtud'cond 'sd, 'dm");
                 } else {
                   Format(instr, "vcvtid'cond 'sd, 'dm");
                 }
               }
               break;
             }
-            case 2:  // vcvtb, vcvtt
-            case 3:  // vcvtb, vcvtt
-            case 9:  // undefined
+            case 2:   // vcvtb, vcvtt
+            case 3:   // vcvtb, vcvtt
+            case 9:   // undefined
             case 10:  // vcvt between floating-point and fixed-point
             case 11:  // vcvt between floating-point and fixed-point
             case 14:  // vcvt between floating-point and fixed-point
             case 15:  // vcvt between floating-point and fixed-point
             default: {
               Unknown(instr);
               break;
             }
           }
-        }
-        break;
+        } break;
       }
     } else {
       // 8, 16, or 32-bit Transfer between ARM Core and VFP
       if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
         if (instr->Bit(20) == 0) {
           Format(instr, "vmovs'cond 'sn, 'rd");
         } else {
           Format(instr, "vmovr'cond 'rd, 'sn");
         }
       } else if ((instr->Bits(22, 3) == 0) && (instr->Bit(20) == 0) &&
@@ skipping 197 matching lines @@
       default: {
         // The type field is 3-bits in the ARM encoding.
         UNREACHABLE();
         break;
       }
     }
   }
 }
 
 
-void Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
-                                     char* human_buffer, intptr_t human_size,
-                                     int* out_instr_size, const Code& code,
-                                     Object** object, uword pc) {
+void Disassembler::DecodeInstruction(char* hex_buffer,
+                                     intptr_t hex_size,
+                                     char* human_buffer,
+                                     intptr_t human_size,
+                                     int* out_instr_size,
+                                     const Code& code,
+                                     Object** object,
+                                     uword pc) {
   ARMDecoder decoder(human_buffer, human_size);
   decoder.InstructionDecode(pc);
   int32_t instruction_bits = Instr::At(pc)->InstructionBits();
   OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
   if (out_instr_size) {
     *out_instr_size = Instr::kInstrSize;
   }
 
   *object = NULL;
   if (!code.IsNull()) {
     *object = &Object::Handle();
     if (!DecodeLoadObjectFromPoolOrThread(pc, code, *object)) {
       *object = NULL;
     }
   }
 }
 
 #endif  // !PRODUCT
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM