clang-format runtime/vm

runtime/vm/constants_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef RUNTIME_VM_CONSTANTS_MIPS_H_
 #define RUNTIME_VM_CONSTANTS_MIPS_H_
 
 #include "platform/assert.h"
 
 namespace dart {
 
 enum Register {
-  R0  =  0,
-  R1  =  1,  // AT aka TMP
-  R2  =  2,
-  R3  =  3,
-  R4  =  4,
-  R5  =  5,
-  R6  =  6,
-  R7  =  7,
-  R8  =  8,
-  R9  =  9,
+  R0 = 0,
+  R1 = 1,  // AT aka TMP
+  R2 = 2,
+  R3 = 3,
+  R4 = 4,
+  R5 = 5,
+  R6 = 6,
+  R7 = 7,
+  R8 = 8,
+  R9 = 9,
   R10 = 10,
   R11 = 11,
   R12 = 12,
   R13 = 13,
   R14 = 14,
   R15 = 15,
   R16 = 16,
   R17 = 17,
   R18 = 18,
   R19 = 19,  // THR
@@ skipping 53 matching lines @@
   GP = R28,
   SP = R29,
   FP = R30,
   RA = R31,
 };
 
 
 // Values for floating point registers.
 // Double-precision values use register pairs.
 enum FRegister {
-  F0  =  0,
-  F1  =  1,
-  F2  =  2,
-  F3  =  3,
-  F4  =  4,
-  F5  =  5,
-  F6  =  6,
-  F7  =  7,
-  F8  =  8,
-  F9  =  9,
+  F0 = 0,
+  F1 = 1,
+  F2 = 2,
+  F3 = 3,
+  F4 = 4,
+  F5 = 5,
+  F6 = 6,
+  F7 = 7,
+  F8 = 8,
+  F9 = 9,
   F10 = 10,
   F11 = 11,
   F12 = 12,
   F13 = 13,
   F14 = 14,
   F15 = 15,
   F16 = 16,
   F17 = 17,
   F18 = 18,
   F19 = 19,
@@ skipping 12 matching lines @@
   kNumberOfFRegisters = 32,
   kNoFRegister = -1,
 };
 
 // The double precision floating point registers are concatenated pairs of the
 // single precision registers, e.g. D0 is F1:F0, D1 is F3:F2, etc.. We only
 // tell the architecture generic code about the double precision registers, then
 // convert to the single precision registers when needed in the mips-specific
 // code.
 enum DRegister {
-  D0  =  0,  // Function return value 1.
-  D1  =  1,  // Function return value 2.
-  D2  =  2,  // Not preserved.
-  D3  =  3,  // Not preserved.
-  D4  =  4,  // Not preserved.
-  D5  =  5,  // Not preserved.
-  D6  =  6,  // Argument 1.
-  D7  =  7,  // Argument 2.
-  D8  =  8,  // Not preserved.
-  D9  =  9,  // Not preserved.
+  D0 = 0,    // Function return value 1.
+  D1 = 1,    // Function return value 2.
+  D2 = 2,    // Not preserved.
+  D3 = 3,    // Not preserved.
+  D4 = 4,    // Not preserved.
+  D5 = 5,    // Not preserved.
+  D6 = 6,    // Argument 1.
+  D7 = 7,    // Argument 2.
+  D8 = 8,    // Not preserved.
+  D9 = 9,    // Not preserved.
   D10 = 10,  // Preserved.
   D11 = 11,  // Preserved.
   D12 = 12,  // Preserved.
   D13 = 13,  // Preserved.
   D14 = 14,  // Preserved.
   D15 = 15,  // Preserved.
   kNumberOfDRegisters = 16,
   kNoDRegister = -1,
 };
 
@@ skipping 10 matching lines @@
 const FRegister STMP2 = F19;
 
 // Architecture independent aliases.
 typedef DRegister FpuRegister;
 const FpuRegister FpuTMP = DTMP;
 const int kNumberOfFpuRegisters = kNumberOfDRegisters;
 const FpuRegister kNoFpuRegister = kNoDRegister;
 
 
 // Register aliases.
-const Register TMP = AT;  // Used as scratch register by assembler.
+const Register TMP = AT;            // Used as scratch register by assembler.
 const Register TMP2 = kNoRegister;  // No second assembler scratch register.
 const Register CTX = S6;  // Location of current context at method entry.
 const Register CODE_REG = S6;
-const Register PP = S7;  // Caches object pool pointer in generated code.
+const Register PP = S7;     // Caches object pool pointer in generated code.
 const Register SPREG = SP;  // Stack pointer register.
 const Register FPREG = FP;  // Frame pointer register.
 const Register LRREG = RA;  // Link register.
 const Register ICREG = S5;  // IC data register.
 const Register ARGS_DESC_REG = S4;
 const Register THR = S3;  // Caches current thread in generated code.
 const Register CALLEE_SAVED_TEMP = S5;
 
 // The code that generates a comparison can be far away from the code that
 // generates the branch that uses the result of that comparison. In this case,
 // CMPRES1 and CMPRES2 are used for the results of the comparison. We need two
 // since TMP is clobbered by a far branch.
 const Register CMPRES1 = T8;
 const Register CMPRES2 = T9;
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = V0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = V1;
 
 
 typedef uint32_t RegList;
 const RegList kAllCpuRegistersList = 0xFFFFFFFF;
 
 const RegList kAbiArgumentCpuRegs =
     (1 << A0) | (1 << A1) | (1 << A2) | (1 << A3);
-const RegList kAbiPreservedCpuRegs =
-    (1 << S0) | (1 << S1) | (1 << S2) | (1 << S3) |
-    (1 << S4) | (1 << S5) | (1 << S6) | (1 << S7);
+const RegList kAbiPreservedCpuRegs = (1 << S0) | (1 << S1) | (1 << S2) |
+                                     (1 << S3) | (1 << S4) | (1 << S5) |
+                                     (1 << S6) | (1 << S7);
 const int kAbiPreservedCpuRegCount = 8;
 
 // FPU registers 20 - 31 are preserved across calls.
 const FRegister kAbiFirstPreservedFpuReg = F20;
 const FRegister kAbiLastPreservedFpuReg =
     static_cast<FRegister>(kNumberOfFRegisters - 1);
 const int kAbiPreservedFpuRegCount = 12;
 
 const RegList kReservedCpuRegisters =
-    (1 << SPREG)   |
-    (1 << FPREG)   |
-    (1 << TMP)     |
-    (1 << PP)      |
-    (1 << THR)     |
-    (1 << CTX)     |
-    (1 << ZR)      |
-    (1 << CMPRES1) |
-    (1 << CMPRES2) |
-    (1 << K0)      |
-    (1 << K1)      |
-    (1 << GP)      |
-    (1 << RA);
+    (1 << SPREG) | (1 << FPREG) | (1 << TMP) | (1 << PP) | (1 << THR) |
+    (1 << CTX) | (1 << ZR) | (1 << CMPRES1) | (1 << CMPRES2) | (1 << K0) |
+    (1 << K1) | (1 << GP) | (1 << RA);
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     kAllCpuRegistersList & ~kReservedCpuRegisters;
 // Registers available to Dart that are not preserved by runtime calls.
 const RegList kDartVolatileCpuRegs =
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 const int kDartVolatileCpuRegCount = 14;
 const Register kDartFirstVolatileCpuReg = R2;
 const Register kDartLastVolatileCpuReg = R15;
 
 // FPU registers 0 - 19 are not preserved across calls.
 const FRegister kDartFirstVolatileFpuReg = F0;
 const FRegister kDartLastVolatileFpuReg = F19;
 const int kDartVolatileFpuRegCount = 20;
 
 
 // There is no status register on MIPS. Instead of representing a condition
 // code, type Condition (see assembler_mips.h) represents a pair of operands and
 // a relation operator between them.
 enum RelationOperator {
-  AL,  // always
-  NV,  // never
-  EQ,  // equal
-  NE,  // not equal
-  GT,  // greater than
-  GE,  // greater equal
-  LT,  // less than
-  LE,  // less equal
+  AL,   // always
+  NV,   // never
+  EQ,   // equal
+  NE,   // not equal
+  GT,   // greater than
+  GE,   // greater equal
+  LT,   // less than
+  LE,   // less equal
   UGT,  // unsigned greater than
   UGE,  // unsigned greater equal
   ULT,  // unsigned less than
   ULE,  // unsigned less equal
 };
 
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on the "Table 4.25 CPU Instruction Format Fields".
 enum InstructionFields {
@@ skipping 197 matching lines @@
 
 class Instr {
  public:
   enum {
     kInstrSize = 4,
   };
 
   static const int32_t kNopInstruction = 0;
 
   // Reserved break instruction codes.
-  static const int32_t kBreakPointCode = 0xdeb0;  // For breakpoint.
-  static const int32_t kStopMessageCode = 0xdeb1;  // For Stop(message).
+  static const int32_t kBreakPointCode = 0xdeb0;      // For breakpoint.
+  static const int32_t kStopMessageCode = 0xdeb1;     // For Stop(message).
   static const int32_t kSimulatorBreakCode = 0xdeb2;  // For breakpoint in sim.
   static const int32_t kSimulatorRedirectCode = 0xca11;  // For redirection.
 
   static const int32_t kBreakPointZeroInstruction =
       (SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift);
 
   // Breakpoint instruction filling assembler code buffers in debug mode.
   static const int32_t kBreakPointInstruction =
       kBreakPointZeroInstruction | (kBreakPointCode << kBreakCodeShift);
 
@@ skipping 10 matching lines @@
   // Get the raw instruction bits.
   inline int32_t InstructionBits() const {
     return *reinterpret_cast<const int32_t*>(this);
   }
 
   // Set the raw instruction bits to value.
   inline void SetInstructionBits(int32_t value) {
     *reinterpret_cast<int32_t*>(this) = value;
   }
 
-  inline void SetImmInstrBits(Opcode op, Register rs, Register rt,
+  inline void SetImmInstrBits(Opcode op,
+                              Register rs,
+                              Register rt,
                               uint16_t imm) {
-    SetInstructionBits(
-        op << kOpcodeShift |
-        rs << kRsShift |
-        rt << kRtShift |
-        imm << kImmShift);
+    SetInstructionBits(op << kOpcodeShift | rs << kRsShift | rt << kRtShift |
+                       imm << kImmShift);
   }
 
   inline void SetSpecialInstrBits(SpecialFunction f,
-                                  Register rs, Register rt, Register rd) {
-    SetInstructionBits(
-        SPECIAL << kOpcodeShift |
-        f << kFunctionShift |
-        rs << kRsShift |
-        rt << kRtShift |
-        rd << kRdShift);
+                                  Register rs,
+                                  Register rt,
+                                  Register rd) {
+    SetInstructionBits(SPECIAL << kOpcodeShift | f << kFunctionShift |
+                       rs << kRsShift | rt << kRtShift | rd << kRdShift);
   }
 
   // Read one particular bit out of the instruction bits.
-  inline int32_t Bit(int nr) const {
-    return (InstructionBits() >> nr) & 1;
-  }
+  inline int32_t Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
 
   // Read a bit field out of the instruction bits.
   inline int32_t Bits(int shift, int count) const {
     return (InstructionBits() >> shift) & ((1 << count) - 1);
   }
 
   // Accessors to the different named fields used in the MIPS encoding.
   inline Opcode OpcodeField() const {
     return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
   }
@@ skipping 21 matching lines @@
   }
 
   inline FRegister FtField() const {
     return static_cast<FRegister>(Bits(kFtShift, kFtBits));
   }
 
   inline FRegister FdField() const {
     return static_cast<FRegister>(Bits(kFdShift, kFdBits));
   }
 
-  inline int SaField() const {
-    return Bits(kSaShift, kSaBits);
-  }
+  inline int SaField() const { return Bits(kSaShift, kSaBits); }
 
-  inline int32_t UImmField() const {
-    return Bits(kImmShift, kImmBits);
-  }
+  inline int32_t UImmField() const { return Bits(kImmShift, kImmBits); }
 
   inline int32_t SImmField() const {
     // Sign-extend the imm field.
     return (Bits(kImmShift, kImmBits) << (32 - kImmBits)) >> (32 - kImmBits);
   }
 
   inline int32_t BreakCodeField() const {
     return Bits(kBreakCodeShift, kBreakCodeBits);
   }
 
@@ skipping 24 matching lines @@
   }
 
   inline bool HasFormat() const {
     return (OpcodeField() == COP1) && (Bit(25) == 1);
   }
 
   inline Format FormatField() const {
     return static_cast<Format>(Bits(kFmtShift, kFmtBits));
   }
 
-  inline int32_t FpuCCField() const {
-    return Bits(kFpuCCShift, kFpuCCBits);
-  }
+  inline int32_t FpuCCField() const { return Bits(kFpuCCShift, kFpuCCBits); }
 
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pc. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
 #if defined(DEBUG)
-  inline void AssertIsImmInstr(Opcode op, Register rs, Register rt,
-                              int32_t imm) {
+  inline void AssertIsImmInstr(Opcode op,
+                               Register rs,
+                               Register rt,
+                               int32_t imm) {
     ASSERT((OpcodeField() == op) && (RsField() == rs) && (RtField() == rt) &&
            (SImmField() == imm));
   }
 
-  inline void AssertIsSpecialInstr(SpecialFunction f, Register rs, Register rt,
+  inline void AssertIsSpecialInstr(SpecialFunction f,
+                                   Register rs,
+                                   Register rt,
                                    Register rd) {
     ASSERT((OpcodeField() == SPECIAL) && (FunctionField() == f) &&
-           (RsField() == rs) && (RtField() == rt) &&
-           (RdField() == rd));
+           (RsField() == rs) && (RtField() == rt) && (RdField() == rd));
   }
 #endif  // defined(DEBUG)
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // RUNTIME_VM_CONSTANTS_MIPS_H_