clang-format runtime/vm

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef RUNTIME_VM_CONSTANTS_ARM64_H_
 #define RUNTIME_VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
 
 enum Register {
-  R0  =  0,
-  R1  =  1,
-  R2  =  2,
-  R3  =  3,
-  R4  =  4,
-  R5  =  5,
-  R6  =  6,
-  R7  =  7,
-  R8  =  8,
-  R9  =  9,
+  R0 = 0,
+  R1 = 1,
+  R2 = 2,
+  R3 = 3,
+  R4 = 4,
+  R5 = 5,
+  R6 = 6,
+  R7 = 7,
+  R8 = 8,
+  R9 = 9,
   R10 = 10,
   R11 = 11,
   R12 = 12,
   R13 = 13,
   R14 = 14,
   R15 = 15,  // SP in Dart code.
   R16 = 16,  // IP0 aka TMP
   R17 = 17,  // IP1 aka TMP2
   R18 = 18,  // "platform register" on iOS.
   R19 = 19,
@@ skipping 20 matching lines @@
   // Aliases.
   IP0 = R16,
   IP1 = R17,
   SP = R15,
   FP = R29,
   LR = R30,
 };
 
 
 enum VRegister {
-  V0  =  0,
-  V1  =  1,
-  V2  =  2,
-  V3  =  3,
-  V4  =  4,
-  V5  =  5,
-  V6  =  6,
-  V7  =  7,
-  V8  =  8,
-  V9  =  9,
+  V0 = 0,
+  V1 = 1,
+  V2 = 2,
+  V3 = 3,
+  V4 = 4,
+  V5 = 5,
+  V6 = 6,
+  V7 = 7,
+  V8 = 8,
+  V9 = 9,
   V10 = 10,
   V11 = 11,
   V12 = 12,
   V13 = 13,
   V14 = 14,
   V15 = 15,
   V16 = 16,
   V17 = 17,
   V18 = 18,
   V19 = 19,
@@ skipping 19 matching lines @@
 // Architecture independent aliases.
 typedef VRegister FpuRegister;
 const FpuRegister FpuTMP = VTMP;
 const int kNumberOfFpuRegisters = kNumberOfVRegisters;
 const FpuRegister kNoFpuRegister = kNoVRegister;
 
 // Register aliases.
 const Register TMP = R16;  // Used as scratch register by assembler.
 const Register TMP2 = R17;
 const Register CTX = R28;  // Location of current context at method entry.
-const Register PP = R27;  // Caches object pool pointer in generated code.
+const Register PP = R27;   // Caches object pool pointer in generated code.
 const Register CODE_REG = R24;
-const Register FPREG = FP;  // Frame pointer register.
-const Register SPREG = R15;  // Stack pointer register.
-const Register LRREG = LR;  // Link register.
-const Register ICREG = R5;  // IC data register.
+const Register FPREG = FP;          // Frame pointer register.
+const Register SPREG = R15;         // Stack pointer register.
+const Register LRREG = LR;          // Link register.
+const Register ICREG = R5;          // IC data register.
 const Register ARGS_DESC_REG = R4;  // Arguments descriptor register.
-const Register THR = R26;  // Caches current thread in generated code.
+const Register THR = R26;           // Caches current thread in generated code.
 const Register CALLEE_SAVED_TEMP = R19;
 const Register CALLEE_SAVED_TEMP2 = R20;
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = R0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = R1;
 
 // Masks, sizes, etc.
 const int kXRegSizeInBits = 64;
 const int kWRegSizeInBits = 32;
 const int64_t kXRegMask = 0xffffffffffffffffL;
 const int64_t kWRegMask = 0x00000000ffffffffL;
 
 // List of registers used in load/store multiple.
 typedef uint32_t RegList;
 const RegList kAllCpuRegistersList = 0xFFFF;
 
 
 // C++ ABI call registers.
-const RegList kAbiArgumentCpuRegs =
-    (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3) |
-    (1 << R4) | (1 << R5) | (1 << R6) | (1 << R7);
+const RegList kAbiArgumentCpuRegs = (1 << R0) | (1 << R1) | (1 << R2) |
+                                    (1 << R3) | (1 << R4) | (1 << R5) |
+                                    (1 << R6) | (1 << R7);
 const RegList kAbiPreservedCpuRegs =
-    (1 << R19) | (1 << R20) | (1 << R21) | (1 << R22) |
-    (1 << R23) | (1 << R24) | (1 << R25) | (1 << R26) |
-    (1 << R27) | (1 << R28);
+    (1 << R19) | (1 << R20) | (1 << R21) | (1 << R22) | (1 << R23) |
+    (1 << R24) | (1 << R25) | (1 << R26) | (1 << R27) | (1 << R28);
 const Register kAbiFirstPreservedCpuReg = R19;
 const Register kAbiLastPreservedCpuReg = R28;
 const int kAbiPreservedCpuRegCount = 10;
 const VRegister kAbiFirstPreservedFpuReg = V8;
 const VRegister kAbiLastPreservedFpuReg = V15;
 const int kAbiPreservedFpuRegCount = 8;
 
 const intptr_t kReservedCpuRegisters =
     (1 << SPREG) |  // Dart SP
-    (1 << FPREG) |
-    (1 << TMP)   |
-    (1 << TMP2)  |
-    (1 << PP)    |
-    (1 << THR)   |
-    (1 << LR)    |
-    (1 << R31)   |  // C++ SP
-    (1 << CTX)   |
-    (1 << R18);     // iOS platform register.
-                    // TODO(rmacnak): Only reserve on Mac & iOS.
+    (1 << FPREG) | (1 << TMP) | (1 << TMP2) | (1 << PP) | (1 << THR) |
+    (1 << LR) | (1 << R31) |  // C++ SP
+    (1 << CTX) | (1 << R18);  // iOS platform register.
+                              // TODO(rmacnak): Only reserve on Mac & iOS.
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     kAllCpuRegistersList & ~kReservedCpuRegisters;
 // Registers available to Dart that are not preserved by runtime calls.
 const RegList kDartVolatileCpuRegs =
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 const Register kDartFirstVolatileCpuReg = R0;
 const Register kDartLastVolatileCpuReg = R14;
 const int kDartVolatileCpuRegCount = 15;
 const int kDartVolatileFpuRegCount = 24;
 
 static inline Register ConcreteRegister(Register r) {
   return ((r == ZR) || (r == CSP)) ? R31 : r;
 }
 
 // Values for the condition field as defined in section A3.2.
 enum Condition {
   kNoCondition = -1,
-  EQ =  0,  // equal
-  NE =  1,  // not equal
-  CS =  2,  // carry set/unsigned higher or same
-  CC =  3,  // carry clear/unsigned lower
-  MI =  4,  // minus/negative
-  PL =  5,  // plus/positive or zero
-  VS =  6,  // overflow
-  VC =  7,  // no overflow
-  HI =  8,  // unsigned higher
-  LS =  9,  // unsigned lower or same
+  EQ = 0,   // equal
+  NE = 1,   // not equal
+  CS = 2,   // carry set/unsigned higher or same
+  CC = 3,   // carry clear/unsigned lower
+  MI = 4,   // minus/negative
+  PL = 5,   // plus/positive or zero
+  VS = 6,   // overflow
+  VC = 7,   // no overflow
+  HI = 8,   // unsigned higher
+  LS = 9,   // unsigned lower or same
   GE = 10,  // signed greater than or equal
   LT = 11,  // signed less than
   GT = 12,  // signed greater than
   LE = 13,  // signed less than or equal
   AL = 14,  // always (unconditional)
   NV = 15,  // special condition (refer to section C1.2.3)
   kMaxCondition = 16,
 };
 
 static inline Condition InvertCondition(Condition c) {
   const int32_t i = static_cast<int32_t>(c) ^ 0x1;
   return static_cast<Condition>(i);
 }
 
 enum Bits {
-  B0  =  (1 << 0), B1  =  (1 << 1), B2  =  (1 << 2), B3  =  (1 << 3),
-  B4  =  (1 << 4), B5  =  (1 << 5), B6  =  (1 << 6), B7  =  (1 << 7),
-  B8  =  (1 << 8), B9  =  (1 << 9), B10 = (1 << 10), B11 = (1 << 11),
-  B12 = (1 << 12), B13 = (1 << 13), B14 = (1 << 14), B15 = (1 << 15),
-  B16 = (1 << 16), B17 = (1 << 17), B18 = (1 << 18), B19 = (1 << 19),
-  B20 = (1 << 20), B21 = (1 << 21), B22 = (1 << 22), B23 = (1 << 23),
-  B24 = (1 << 24), B25 = (1 << 25), B26 = (1 << 26), B27 = (1 << 27),
-  B28 = (1 << 28), B29 = (1 << 29), B30 = (1 << 30), B31 = (1 << 31),
+  B0 = (1 << 0),
+  B1 = (1 << 1),
+  B2 = (1 << 2),
+  B3 = (1 << 3),
+  B4 = (1 << 4),
+  B5 = (1 << 5),
+  B6 = (1 << 6),
+  B7 = (1 << 7),
+  B8 = (1 << 8),
+  B9 = (1 << 9),
+  B10 = (1 << 10),
+  B11 = (1 << 11),
+  B12 = (1 << 12),
+  B13 = (1 << 13),
+  B14 = (1 << 14),
+  B15 = (1 << 15),
+  B16 = (1 << 16),
+  B17 = (1 << 17),
+  B18 = (1 << 18),
+  B19 = (1 << 19),
+  B20 = (1 << 20),
+  B21 = (1 << 21),
+  B22 = (1 << 22),
+  B23 = (1 << 23),
+  B24 = (1 << 24),
+  B25 = (1 << 25),
+  B26 = (1 << 26),
+  B27 = (1 << 27),
+  B28 = (1 << 28),
+  B29 = (1 << 29),
+  B30 = (1 << 30),
+  B31 = (1 << 31),
 };
 
 enum OperandSize {
   kByte,
   kUnsignedByte,
   kHalfword,
   kUnsignedHalfword,
   kWord,
   kUnsignedWord,
   kDoubleWord,
@@ skipping 94 matching lines @@
   SVC = ExceptionGenFixed | B0,
   BRK = ExceptionGenFixed | B21,
   HLT = ExceptionGenFixed | B22,
 };
 
 // C3.2.4
 enum SystemOp {
   SystemMask = 0xffc00000,
   SystemFixed = CompareBranchFixed | B31 | B30 | B24,
   HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0,
-  CLREX = SystemFixed | B17 | B16 | B13 | B12 | B11 | B10 | B9 | B8 |
-      B6 | B4 | B3 | B2 | B1 | B0,
+  CLREX = SystemFixed | B17 | B16 | B13 | B12 | B11 | B10 | B9 | B8 | B6 | B4 |
+          B3 |
+          B2 |
+          B1 |
+          B0,
 };
 
 // C3.2.5
 enum TestAndBranchOp {
   TestAndBranchMask = 0x7e000000,
   TestAndBranchFixed = CompareBranchFixed | B29 | B25,
   TBZ = TestAndBranchFixed,
   TBNZ = TestAndBranchFixed | B24,
 };
 
@@ skipping 201 matching lines @@
 // C.3.6.17
 enum SIMDTwoRegOp {
   SIMDTwoRegMask = 0x9f3e0c00,
   SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11,
   VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12,
   VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12,
   VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12,
   VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12,
   VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12,
   VSQRTS = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B13 | B12,
-  VSQRTD = SIMDTwoRegFixed | B30 | B29 | B23 | B22
-                           | B16 | B15 | B14 | B13 | B12,
+  VSQRTD =
+      SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B16 | B15 | B14 | B13 | B12,
   VRECPES = SIMDTwoRegFixed | B30 | B23 | B16 | B15 | B14 | B12,
   VRSQRTES = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B12,
 };
 
 // C.3.6.22
 enum FPCompareOp {
   FPCompareMask = 0xffa0fc07,
   FPCompareFixed = FPFixed | B21 | B13,
   FCMPD = FPCompareFixed | B22,
   FCMPZD = FPCompareFixed | B22 | B3,
@@ skipping 29 matching lines @@
   FMOVDI = FPImmFixed | B22,
 };
 
 // C3.6.30
 enum FPIntCvtOp {
   FPIntCvtMask = 0x5f20fc00,
   FPIntCvtFixed = FPFixed | B21,
   FMOVRD = FPIntCvtFixed | B22 | B18 | B17,
   FMOVDR = FPIntCvtFixed | B22 | B18 | B17 | B16,
   FCVTZDS = FPIntCvtFixed | B22 | B20 | B19,
-  SCVTFD = FPIntCvtFixed |  B22 | B17,
+  SCVTFD = FPIntCvtFixed | B22 | B17,
 };
 
 
 #define APPLY_OP_LIST(_V)                                                      \
-_V(DPImmediate)                                                                \
-_V(CompareBranch)                                                              \
-_V(LoadStore)                                                                  \
-_V(DPRegister)                                                                 \
-_V(DPSimd1)                                                                    \
-_V(DPSimd2)                                                                    \
-_V(FP)                                                                         \
-_V(CompareAndBranch)                                                           \
-_V(ConditionalBranch)                                                          \
-_V(ExceptionGen)                                                               \
-_V(System)                                                                     \
-_V(TestAndBranch)                                                              \
-_V(UnconditionalBranch)                                                        \
-_V(UnconditionalBranchReg)                                                     \
-_V(LoadStoreReg)                                                               \
-_V(LoadStoreRegPair)                                                           \
-_V(LoadRegLiteral)                                                             \
-_V(LoadStoreExclusive)                                                         \
-_V(AddSubImm)                                                                  \
-_V(LogicalImm)                                                                 \
-_V(MoveWide)                                                                   \
-_V(PCRel)                                                                      \
-_V(AddSubShiftExt)                                                             \
-_V(AddSubWithCarry)                                                            \
-_V(ConditionalSelect)                                                          \
-_V(MiscDP1Source)                                                              \
-_V(MiscDP2Source)                                                              \
-_V(MiscDP3Source)                                                              \
-_V(LogicalShift)                                                               \
-_V(SIMDCopy)                                                                   \
-_V(SIMDThreeSame)                                                              \
-_V(SIMDTwoReg)                                                                 \
-_V(FPCompare)                                                                  \
-_V(FPOneSource)                                                                \
-_V(FPTwoSource)                                                                \
-_V(FPImm)                                                                      \
-_V(FPIntCvt)                                                                   \
+  _V(DPImmediate)                                                              \
+  _V(CompareBranch)                                                            \
+  _V(LoadStore)                                                                \
+  _V(DPRegister)                                                               \
+  _V(DPSimd1)                                                                  \
+  _V(DPSimd2)                                                                  \
+  _V(FP)                                                                       \
+  _V(CompareAndBranch)                                                         \
+  _V(ConditionalBranch)                                                        \
+  _V(ExceptionGen)                                                             \
+  _V(System)                                                                   \
+  _V(TestAndBranch)                                                            \
+  _V(UnconditionalBranch)                                                      \
+  _V(UnconditionalBranchReg)                                                   \
+  _V(LoadStoreReg)                                                             \
+  _V(LoadStoreRegPair)                                                         \
+  _V(LoadRegLiteral)                                                           \
+  _V(LoadStoreExclusive)                                                       \
+  _V(AddSubImm)                                                                \
+  _V(LogicalImm)                                                               \
+  _V(MoveWide)                                                                 \
+  _V(PCRel)                                                                    \
+  _V(AddSubShiftExt)                                                           \
+  _V(AddSubWithCarry)                                                          \
+  _V(ConditionalSelect)                                                        \
+  _V(MiscDP1Source)                                                            \
+  _V(MiscDP2Source)                                                            \
+  _V(MiscDP3Source)                                                            \
+  _V(LogicalShift)                                                             \
+  _V(SIMDCopy)                                                                 \
+  _V(SIMDThreeSame)                                                            \
+  _V(SIMDTwoReg)                                                               \
+  _V(FPCompare)                                                                \
+  _V(FPOneSource)                                                              \
+  _V(FPTwoSource)                                                              \
+  _V(FPImm)                                                                    \
+  _V(FPIntCvt)
 
 
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   kMaxShift = 4,
 };
@@ skipping 118 matching lines @@
 
   // Hint Fields.
   kHintCRmShift = 8,
   kHintCRmBits = 4,
   kHintOp2Shift = 5,
   kHintOp2Bits = 3,
 };
 
 
 // Helper functions for decoding logical immediates.
-static inline uint64_t RotateRight(
-    uint64_t value, uint8_t rotate, uint8_t width) {
+static inline uint64_t RotateRight(uint64_t value,
+                                   uint8_t rotate,
+                                   uint8_t width) {
   ASSERT(width <= 64);
   rotate &= 63;
   return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) |
          (value >> rotate);
 }
 
-static inline uint64_t RepeatBitsAcrossReg(
-    uint8_t reg_size, uint64_t value, uint8_t width) {
+static inline uint64_t RepeatBitsAcrossReg(uint8_t reg_size,
+                                           uint64_t value,
+                                           uint8_t width) {
   ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
          (width == 32));
   ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
   uint64_t result = value & ((1UL << width) - 1UL);
   for (unsigned i = width; i < reg_size; i *= 2) {
     result |= (result << i);
   }
   return result;
 }
 
 // The class Instr enables access to individual fields defined in the ARM
 // architecture instruction set encoding as described in figure A3-1.
 //
 // Example: Test whether the instruction at ptr sets the condition code bits.
 //
 // bool InstructionSetsConditionCodes(byte* ptr) {
 //   Instr* instr = Instr::At(ptr);
 //   int type = instr->TypeField();
 //   return ((type == 0) || (type == 1)) && instr->HasS();
 // }
 //
 class Instr {
  public:
-  enum {
-    kInstrSize = 4,
-    kInstrSizeLog2 = 2,
-    kPCReadOffset = 8
-  };
+  enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
 
   static const int32_t kNopInstruction = HINT;  // hint #0 === nop.
 
   // Reserved brk and hlt instruction codes.
-  static const int32_t kBreakPointCode = 0xdeb0;  // For breakpoint.
-  static const int32_t kStopMessageCode = 0xdeb1;  // For Stop(message).
+  static const int32_t kBreakPointCode = 0xdeb0;      // For breakpoint.
+  static const int32_t kStopMessageCode = 0xdeb1;     // For Stop(message).
   static const int32_t kSimulatorBreakCode = 0xdeb2;  // For breakpoint in sim.
   static const int32_t kSimulatorRedirectCode = 0xca11;  // For redirection.
 
   // Breakpoint instruction filling assembler code buffers in debug mode.
   static const int32_t kBreakPointInstruction =  // brk(0xdeb0).
       BRK | (kBreakPointCode << kImm16Shift);
 
   // Breakpoint instruction used by the simulator.
   // Should be distinct from kBreakPointInstruction and from a typical user
   // breakpoint inserted in generated code for debugging, e.g. brk(0).
   static const int32_t kSimulatorBreakpointInstruction =
       HLT | (kSimulatorBreakCode << kImm16Shift);
 
   // Runtime call redirection instruction used by the simulator.
   static const int32_t kSimulatorRedirectInstruction =
       HLT | (kSimulatorRedirectCode << kImm16Shift);
 
   // Read one particular bit out of the instruction bits.
-  inline int Bit(int nr) const {
-    return (InstructionBits() >> nr) & 1;
-  }
+  inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
 
   // Read a bit field out of the instruction bits.
   inline int Bits(int shift, int count) const {
     return (InstructionBits() >> shift) & ((1 << count) - 1);
   }
 
   // Get the raw instruction bits.
   inline int32_t InstructionBits() const {
     return *reinterpret_cast<const int32_t*>(this);
   }
 
   // Set the raw instruction bits to value.
   inline void SetInstructionBits(int32_t value) {
     *reinterpret_cast<int32_t*>(this) = value;
   }
 
-  inline void SetMoveWideBits(
-      MoveWideOp op, Register rd, uint16_t imm, int hw, OperandSize sz) {
+  inline void SetMoveWideBits(MoveWideOp op,
+                              Register rd,
+                              uint16_t imm,
+                              int hw,
+                              OperandSize sz) {
     ASSERT((hw >= 0) && (hw <= 3));
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
-    SetInstructionBits(
-        op | size |
-        (static_cast<int32_t>(rd) << kRdShift) |
-        (static_cast<int32_t>(hw) << kHWShift) |
-        (static_cast<int32_t>(imm) << kImm16Shift));
+    SetInstructionBits(op | size | (static_cast<int32_t>(rd) << kRdShift) |
+                       (static_cast<int32_t>(hw) << kHWShift) |
+                       (static_cast<int32_t>(imm) << kImm16Shift));
   }
 
-  inline void SetUnconditionalBranchRegBits(
-      UnconditionalBranchRegOp op, Register rn) {
-    SetInstructionBits(
-        op |
-        (static_cast<int32_t>(rn) << kRnShift));
+  inline void SetUnconditionalBranchRegBits(UnconditionalBranchRegOp op,
+                                            Register rn) {
+    SetInstructionBits(op | (static_cast<int32_t>(rn) << kRnShift));
   }
 
   inline void SetImm12Bits(int32_t orig, int32_t imm12) {
     ASSERT((imm12 & 0xfffff000) == 0);
     SetInstructionBits((orig & ~kImm12Mask) | (imm12 << kImm12Shift));
   }
 
   inline int NField() const { return Bit(22); }
   inline int SField() const { return Bit(kSShift); }
   inline int SFField() const { return Bit(kSFShift); }
   inline int SzField() const { return Bits(kSzShift, kSzBits); }
-  inline Register RdField() const { return static_cast<Register>(
-                                        Bits(kRdShift, kRdBits)); }
-  inline Register RnField() const { return static_cast<Register>(
-                                        Bits(kRnShift, kRnBits)); }
-  inline Register RaField() const { return static_cast<Register>(
-                                        Bits(kRaShift, kRaBits)); }
-  inline Register RmField() const { return static_cast<Register>(
-                                        Bits(kRmShift, kRmBits)); }
-  inline Register RtField() const { return static_cast<Register>(
-                                        Bits(kRtShift, kRtBits)); }
-  inline Register Rt2Field() const { return static_cast<Register>(
-                                        Bits(kRt2Shift, kRt2Bits)); }
-  inline Register RsField() const { return static_cast<Register>(
-                                        Bits(kRsShift, kRsBits)); }
+  inline Register RdField() const {
+    return static_cast<Register>(Bits(kRdShift, kRdBits));
+  }
+  inline Register RnField() const {
+    return static_cast<Register>(Bits(kRnShift, kRnBits));
+  }
+  inline Register RaField() const {
+    return static_cast<Register>(Bits(kRaShift, kRaBits));
+  }
+  inline Register RmField() const {
+    return static_cast<Register>(Bits(kRmShift, kRmBits));
+  }
+  inline Register RtField() const {
+    return static_cast<Register>(Bits(kRtShift, kRtBits));
+  }
+  inline Register Rt2Field() const {
+    return static_cast<Register>(Bits(kRt2Shift, kRt2Bits));
+  }
+  inline Register RsField() const {
+    return static_cast<Register>(Bits(kRsShift, kRsBits));
+  }
 
-  inline VRegister VdField() const { return static_cast<VRegister>(
-                                        Bits(kVdShift, kVdBits)); }
-  inline VRegister VnField() const { return static_cast<VRegister>(
-                                        Bits(kVnShift, kVnBits)); }
-  inline VRegister VmField() const { return static_cast<VRegister>(
-                                        Bits(kVmShift, kVmBits)); }
-  inline VRegister VtField() const { return static_cast<VRegister>(
-                                        Bits(kVtShift, kVtBits)); }
+  inline VRegister VdField() const {
+    return static_cast<VRegister>(Bits(kVdShift, kVdBits));
+  }
+  inline VRegister VnField() const {
+    return static_cast<VRegister>(Bits(kVnShift, kVnBits));
+  }
+  inline VRegister VmField() const {
+    return static_cast<VRegister>(Bits(kVmShift, kVmBits));
+  }
+  inline VRegister VtField() const {
+    return static_cast<VRegister>(Bits(kVtShift, kVtBits));
+  }
 
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
   inline int Imm7Field() const { return Bits(kImm7Shift, kImm7Bits); }
   // Sign-extended Imm7Field()
   inline int64_t SImm7Field() const {
-      return (static_cast<int32_t>(Imm7Field()) << 25) >> 25; }
+    return (static_cast<int32_t>(Imm7Field()) << 25) >> 25;
+  }
   inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()
   inline int64_t SImm9Field() const {
-      return (static_cast<int32_t>(Imm9Field()) << 23) >> 23; }
+    return (static_cast<int32_t>(Imm9Field()) << 23) >> 23;
+  }
 
   inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
   inline int Imm12ShiftField() const {
-    return Bits(kImm12ShiftShift, kImm12ShiftBits); }
+    return Bits(kImm12ShiftShift, kImm12ShiftBits);
+  }
 
   inline int Imm16Field() const { return Bits(kImm16Shift, kImm16Bits); }
   inline int HWField() const { return Bits(kHWShift, kHWBits); }
 
   inline int ImmRField() const { return Bits(kImmRShift, kImmRBits); }
   inline int ImmSField() const { return Bits(kImmSShift, kImmSBits); }
 
   inline int Imm14Field() const { return Bits(kImm14Shift, kImm14Bits); }
   inline int64_t SImm14Field() const {
-      return (static_cast<int32_t>(Imm14Field()) << 18) >> 18; }
+    return (static_cast<int32_t>(Imm14Field()) << 18) >> 18;
+  }
   inline int Imm19Field() const { return Bits(kImm19Shift, kImm19Bits); }
   inline int64_t SImm19Field() const {
-      return (static_cast<int32_t>(Imm19Field()) << 13) >> 13; }
+    return (static_cast<int32_t>(Imm19Field()) << 13) >> 13;
+  }
   inline int Imm26Field() const { return Bits(kImm26Shift, kImm26Bits); }
   inline int64_t SImm26Field() const {
-      return (static_cast<int32_t>(Imm26Field()) << 6) >> 6; }
+    return (static_cast<int32_t>(Imm26Field()) << 6) >> 6;
+  }
 
   inline Condition ConditionField() const {
     return static_cast<Condition>(Bits(kCondShift, kCondBits));
   }
   inline Condition SelectConditionField() const {
     return static_cast<Condition>(Bits(kSelCondShift, kSelCondBits));
   }
 
   // Shift and Extend.
   inline bool IsShift() const {
     return IsLogicalShiftOp() || (Bit(kAddShiftExtendShift) == 0);
   }
   inline bool IsExtend() const {
     return !IsLogicalShiftOp() && (Bit(kAddShiftExtendShift) == 1);
   }
   inline Shift ShiftTypeField() const {
-      return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits)); }
+    return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits));
+  }
   inline Extend ExtendTypeField() const {
-      return static_cast<Extend>(Bits(kExtendTypeShift, kExtendTypeBits)); }
+    return static_cast<Extend>(Bits(kExtendTypeShift, kExtendTypeBits));
+  }
   inline int ShiftAmountField() const { return Imm6Field(); }
   inline int ExtShiftAmountField() const { return Imm3Field(); }
 
-  // Instruction identification.
-  #define IS_OP(op)                                                            \
-    inline bool Is##op##Op() const {                                           \
-      return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask)); }
+// Instruction identification.
+#define IS_OP(op)                                                              \
+  inline bool Is##op##Op() const {                                             \
+    return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask));         \
+  }
   APPLY_OP_LIST(IS_OP)
-  #undef IS_OP
+#undef IS_OP
 
   inline bool HasS() const { return (SField() == 1); }
 
   // Indicate whether Rd can be the CSP or ZR. This does not check that the
   // instruction actually has an Rd field.
   R31Type RdMode() const {
     // The following instructions use CSP as Rd:
     //  Add/sub (immediate) when not setting the flags.
     //  Add/sub (extended) when not setting the flags.
     //  Logical (immediate) when not setting the flags.
@@ skipping 18 matching lines @@
   }
 
   // Indicate whether Rn can be CSP or ZR. This does not check that the
   // instruction actually has an Rn field.
   R31Type RnMode() const {
     // The following instructions use CSP as Rn:
     //  All loads and stores.
     //  Add/sub (immediate).
     //  Add/sub (extended).
     // Otherwise, r31 is ZR.
-    if (IsLoadStoreOp() ||
-        IsAddSubImmOp() ||
+    if (IsLoadStoreOp() || IsAddSubImmOp() ||
         (IsAddSubShiftExtOp() && IsExtend())) {
       return R31IsSP;
     }
     return R31IsZR;
   }
 
   // Logical immediates can't encode zero, so a return value of zero is used to
   // indicate a failure case. Specifically, where the constraints on imm_s are
   // not met.
   uint64_t ImmLogical() {
-    const uint8_t reg_size =
-        SFField() == 1 ? kXRegSizeInBits : kWRegSizeInBits;
+    const uint8_t reg_size = SFField() == 1 ? kXRegSizeInBits : kWRegSizeInBits;
     const int64_t n = NField();
     const int64_t imm_s = ImmSField();
     const int64_t imm_r = ImmRField();
 
     // An integer is constructed from the n, imm_s and imm_r bits according to
     // the following table:
     //
     //  N   imms    immr    size        S             R
     //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
     //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
@@ skipping 17 matching lines @@
       if ((imm_s >> 1) == 0x1F) {
         return 0;
       }
       for (int width = 0x20; width >= 0x2; width >>= 1) {
         if ((imm_s & width) == 0) {
           int mask = width - 1;
           if ((imm_s & mask) == mask) {
             return 0;
           }
           uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1;
-          return RepeatBitsAcrossReg(reg_size,
-                                     RotateRight(bits, imm_r & mask, width),
-                                     width);
+          return RepeatBitsAcrossReg(
+              reg_size, RotateRight(bits, imm_r & mask, width), width);
         }
       }
     }
     UNREACHABLE();
     return 0;
   }
 
   static int64_t VFPExpandImm(uint8_t imm8) {
-    const int64_t sign =
-        static_cast<int64_t>((imm8 & 0x80) >> 7) << 63;
-    const int64_t hi_exp =
-        static_cast<int64_t>(!((imm8 & 0x40) >> 6)) << 62;
-    const int64_t mid_exp =
-        (((imm8 & 0x40) >> 6) == 0) ? 0 : (0xffLL << 54);
-    const int64_t low_exp =
-        static_cast<int64_t>((imm8 & 0x30) >> 4) << 52;
-    const int64_t frac =
-        static_cast<int64_t>(imm8 & 0x0f) << 48;
+    const int64_t sign = static_cast<int64_t>((imm8 & 0x80) >> 7) << 63;
+    const int64_t hi_exp = static_cast<int64_t>(!((imm8 & 0x40) >> 6)) << 62;
+    const int64_t mid_exp = (((imm8 & 0x40) >> 6) == 0) ? 0 : (0xffLL << 54);
+    const int64_t low_exp = static_cast<int64_t>((imm8 & 0x30) >> 4) << 52;
+    const int64_t frac = static_cast<int64_t>(imm8 & 0x0f) << 48;
     return sign | hi_exp | mid_exp | low_exp | frac;
   }
 
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // RUNTIME_VM_CONSTANTS_ARM64_H_