clang-format runtime/vm

runtime/vm/constants_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef RUNTIME_VM_CONSTANTS_ARM_H_
 #define RUNTIME_VM_CONSTANTS_ARM_H_
 
 #include "platform/globals.h"
 #include "platform/assert.h"
 
@@ skipping 43 matching lines @@
 // R12:   Volatile
 // R13:   Stack pointer
 // R14:   Link register
 // R15:   Program counter
 // Stack alignment: 4 bytes always, 4 bytes at public interfaces
 
 // iOS passes floating point arguments in registers (hardfp)
 
 
 enum Register {
-  R0  =  0,
-  R1  =  1,
-  R2  =  2,
-  R3  =  3,
-  R4  =  4,
-  R5  =  5,  // PP
-  R6  =  6,  // CTX
-  R7  =  7,  // iOS FP
-  R8  =  8,
-  R9  =  9,
+  R0 = 0,
+  R1 = 1,
+  R2 = 2,
+  R3 = 3,
+  R4 = 4,
+  R5 = 5,  // PP
+  R6 = 6,  // CTX
+  R7 = 7,  // iOS FP
+  R8 = 8,
+  R9 = 9,
   R10 = 10,  // THR
   R11 = 11,  // Linux FP
   R12 = 12,  // IP aka TMP
   R13 = 13,  // SP
   R14 = 14,  // LR
   R15 = 15,  // PC
   kNumberOfCpuRegisters = 16,
   kNoRegister = -1,  // Signals an illegal register.
 
-  // Aliases.
+// Aliases.
 #if defined(TARGET_ABI_IOS)
-  FP   = R7,
+  FP = R7,
   NOTFP = R11,
 #elif defined(TARGET_ABI_EABI)
-  FP   = R11,
+  FP = R11,
   NOTFP = R7,
 #else
 #error Unknown ABI
 #endif
-  IP  = R12,
-  SP  = R13,
-  LR  = R14,
-  PC  = R15,
+  IP = R12,
+  SP = R13,
+  LR = R14,
+  PC = R15,
 };
 
 
 // Values for single-precision floating point registers.
 enum SRegister {
   kNoSRegister = -1,
-  S0  =  0,
-  S1  =  1,
-  S2  =  2,
-  S3  =  3,
-  S4  =  4,
-  S5  =  5,
-  S6  =  6,
-  S7  =  7,
-  S8  =  8,
-  S9  =  9,
+  S0 = 0,
+  S1 = 1,
+  S2 = 2,
+  S3 = 3,
+  S4 = 4,
+  S5 = 5,
+  S6 = 6,
+  S7 = 7,
+  S8 = 8,
+  S9 = 9,
   S10 = 10,
   S11 = 11,
   S12 = 12,
   S13 = 13,
   S14 = 14,
   S15 = 15,
   S16 = 16,
   S17 = 17,
   S18 = 18,
   S19 = 19,
   S20 = 20,
   S21 = 21,
   S22 = 22,
   S23 = 23,
   S24 = 24,
   S25 = 25,
   S26 = 26,
   S27 = 27,
   S28 = 28,
   S29 = 29,
   S30 = 30,
   S31 = 31,
   kNumberOfSRegisters = 32,
 };
 
 
 // Values for double-precision floating point registers.
 enum DRegister {
   kNoDRegister = -1,
-  D0  =  0,
-  D1  =  1,
-  D2  =  2,
-  D3  =  3,
-  D4  =  4,
-  D5  =  5,
-  D6  =  6,
-  D7  =  7,
-  D8  =  8,
-  D9  =  9,
+  D0 = 0,
+  D1 = 1,
+  D2 = 2,
+  D3 = 3,
+  D4 = 4,
+  D5 = 5,
+  D6 = 6,
+  D7 = 7,
+  D8 = 8,
+  D9 = 9,
   D10 = 10,
   D11 = 11,
   D12 = 12,
   D13 = 13,
   D14 = 14,
   D15 = 15,
 #if defined(VFPv3_D16)
   kNumberOfDRegisters = 16,
   // Leaving these defined, but marking them as kNoDRegister to avoid polluting
   // other parts of the code with #ifdef's. Instead, query kNumberOfDRegisters
@@ skipping 32 matching lines @@
   D30 = 30,
   D31 = 31,
   kNumberOfDRegisters = 32,
 #endif
   kNumberOfOverlappingDRegisters = 16,
 };
 
 
 enum QRegister {
   kNoQRegister = -1,
-  Q0  =  0,
-  Q1  =  1,
-  Q2  =  2,
-  Q3  =  3,
-  Q4  =  4,
-  Q5  =  5,
-  Q6  =  6,
-  Q7  =  7,
+  Q0 = 0,
+  Q1 = 1,
+  Q2 = 2,
+  Q3 = 3,
+  Q4 = 4,
+  Q5 = 5,
+  Q6 = 6,
+  Q7 = 7,
 #if defined(VFPv3_D16)
   kNumberOfQRegisters = 8,
-  Q8  = kNoQRegister,
-  Q9  = kNoQRegister,
+  Q8 = kNoQRegister,
+  Q9 = kNoQRegister,
   Q10 = kNoQRegister,
   Q11 = kNoQRegister,
   Q12 = kNoQRegister,
   Q13 = kNoQRegister,
   Q14 = kNoQRegister,
   Q15 = kNoQRegister,
 #else
-  Q8  =  8,
-  Q9  =  9,
+  Q8 = 8,
+  Q9 = 9,
   Q10 = 10,
   Q11 = 11,
   Q12 = 12,
   Q13 = 13,
   Q14 = 14,
   Q15 = 15,
   kNumberOfQRegisters = 16,
 #endif
 };
 
@@ skipping 18 matching lines @@
 
 static inline SRegister OddSRegisterOf(DRegister d) {
 #if defined(VFPv3_D32)
   ASSERT(d < D16);
 #endif
   return static_cast<SRegister>((d * 2) + 1);
 }
 
 
 // Register aliases for floating point scratch registers.
-const QRegister QTMP = Q7;  // Overlaps with DTMP, STMP.
+const QRegister QTMP = Q7;                     // Overlaps with DTMP, STMP.
 const DRegister DTMP = EvenDRegisterOf(QTMP);  // Overlaps with STMP.
 const SRegister STMP = EvenSRegisterOf(DTMP);
 
 // Architecture independent aliases.
 typedef QRegister FpuRegister;
 
 const FpuRegister FpuTMP = QTMP;
 const int kNumberOfFpuRegisters = kNumberOfQRegisters;
 const FpuRegister kNoFpuRegister = kNoQRegister;
 
 // Register aliases.
-const Register TMP = IP;  // Used as scratch register by assembler.
+const Register TMP = IP;            // Used as scratch register by assembler.
 const Register TMP2 = kNoRegister;  // There is no second assembler temporary.
-const Register CTX = R6;  // Location of current context at method entry.
-const Register PP = R5;  // Caches object pool pointer in generated code.
+const Register CTX = R6;    // Location of current context at method entry.
+const Register PP = R5;     // Caches object pool pointer in generated code.
 const Register SPREG = SP;  // Stack pointer register.
 const Register FPREG = FP;  // Frame pointer register.
 const Register LRREG = LR;  // Link register.
 const Register ICREG = R9;  // IC data register.
 const Register ARGS_DESC_REG = R4;
 const Register CODE_REG = R6;
 const Register THR = R10;  // Caches current thread in generated code.
 const Register CALLEE_SAVED_TEMP = R8;
 
 // R15 encodes APSR in the vmrs instruction.
@@ skipping 11 matching lines @@
 // List of registers used in load/store multiple.
 typedef uint16_t RegList;
 const RegList kAllCpuRegistersList = 0xFFFF;
 
 
 // C++ ABI call registers.
 const RegList kAbiArgumentCpuRegs =
     (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3);
 #if defined(TARGET_ABI_IOS)
 const RegList kAbiPreservedCpuRegs =
-    (1 << R4)  | (1 << R5) | (1 << R6) | (1 << R8) |
-    (1 << R10) | (1 << R11);
+    (1 << R4) | (1 << R5) | (1 << R6) | (1 << R8) | (1 << R10) | (1 << R11);
 const int kAbiPreservedCpuRegCount = 6;
 #elif defined(TARGET_ABI_EABI)
-const RegList kAbiPreservedCpuRegs =
-    (1 << R4) | (1 << R5) | (1 << R6) | (1 << R7) |
-    (1 << R8) | (1 << R9) | (1 << R10);
+const RegList kAbiPreservedCpuRegs = (1 << R4) | (1 << R5) | (1 << R6) |
+                                     (1 << R7) | (1 << R8) | (1 << R9) |
+                                     (1 << R10);
 const int kAbiPreservedCpuRegCount = 7;
 #else
 #error Unknown ABI
 #endif
 const QRegister kAbiFirstPreservedFpuReg = Q4;
 const QRegister kAbiLastPreservedFpuReg = Q7;
 const int kAbiPreservedFpuRegCount = 4;
 
-const RegList kReservedCpuRegisters =
-    (1 << SPREG) |
-    (1 << FPREG) |
-    (1 << TMP)   |
-    (1 << PP)    |
-    (1 << THR)   |
-    (1 << PC);
+const RegList kReservedCpuRegisters = (1 << SPREG) | (1 << FPREG) | (1 << TMP) |
+                                      (1 << PP) | (1 << THR) | (1 << PC);
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     kAllCpuRegistersList & ~kReservedCpuRegisters;
 // Registers available to Dart that are not preserved by runtime calls.
 const RegList kDartVolatileCpuRegs =
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 #if defined(TARGET_ABI_IOS)
 const int kDartVolatileCpuRegCount = 6;
 #elif defined(TARGET_ABI_EABI)
 const int kDartVolatileCpuRegCount = 5;
 #endif
 const QRegister kDartFirstVolatileFpuReg = Q0;
 const QRegister kDartLastVolatileFpuReg = Q3;
 const int kDartVolatileFpuRegCount = 4;
 
 
 // Values for the condition field as defined in section A3.2.
 enum Condition {
   kNoCondition = -1,
-  EQ =  0,  // equal
-  NE =  1,  // not equal
-  CS =  2,  // carry set/unsigned higher or same
-  CC =  3,  // carry clear/unsigned lower
-  MI =  4,  // minus/negative
-  PL =  5,  // plus/positive or zero
-  VS =  6,  // overflow
-  VC =  7,  // no overflow
-  HI =  8,  // unsigned higher
-  LS =  9,  // unsigned lower or same
-  GE = 10,  // signed greater than or equal
-  LT = 11,  // signed less than
-  GT = 12,  // signed greater than
-  LE = 13,  // signed less than or equal
-  AL = 14,  // always (unconditional)
+  EQ = 0,                  // equal
+  NE = 1,                  // not equal
+  CS = 2,                  // carry set/unsigned higher or same
+  CC = 3,                  // carry clear/unsigned lower
+  MI = 4,                  // minus/negative
+  PL = 5,                  // plus/positive or zero
+  VS = 6,                  // overflow
+  VC = 7,                  // no overflow
+  HI = 8,                  // unsigned higher
+  LS = 9,                  // unsigned lower or same
+  GE = 10,                 // signed greater than or equal
+  LT = 11,                 // signed less than
+  GT = 12,                 // signed greater than
+  LE = 13,                 // signed less than or equal
+  AL = 14,                 // always (unconditional)
   kSpecialCondition = 15,  // special condition (refer to section A3.2.1)
   kMaxCondition = 16,
 };
 
 
 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
 // as defined in section A3.4
 enum Opcode {
   kNoOperand = -1,
-  AND =  0,  // Logical AND
-  EOR =  1,  // Logical Exclusive OR
-  SUB =  2,  // Subtract
-  RSB =  3,  // Reverse Subtract
-  ADD =  4,  // Add
-  ADC =  5,  // Add with Carry
-  SBC =  6,  // Subtract with Carry
-  RSC =  7,  // Reverse Subtract with Carry
-  TST =  8,  // Test
-  TEQ =  9,  // Test Equivalence
+  AND = 0,   // Logical AND
+  EOR = 1,   // Logical Exclusive OR
+  SUB = 2,   // Subtract
+  RSB = 3,   // Reverse Subtract
+  ADD = 4,   // Add
+  ADC = 5,   // Add with Carry
+  SBC = 6,   // Subtract with Carry
+  RSC = 7,   // Reverse Subtract with Carry
+  TST = 8,   // Test
+  TEQ = 9,   // Test Equivalence
   CMP = 10,  // Compare
   CMN = 11,  // Compare Negated
   ORR = 12,  // Logical (inclusive) OR
   MOV = 13,  // Move
   BIC = 14,  // Bit Clear
   MVN = 15,  // Move Not
   kMaxOperand = 16
 };
 
 
@@ skipping 93 matching lines @@
 // Example: Test whether the instruction at ptr sets the condition code bits.
 //
 // bool InstructionSetsConditionCodes(byte* ptr) {
 //   Instr* instr = Instr::At(ptr);
 //   int type = instr->TypeField();
 //   return ((type == 0) || (type == 1)) && instr->HasS();
 // }
 //
 class Instr {
  public:
-  enum {
-    kInstrSize = 4,
-    kInstrSizeLog2 = 2,
-    kPCReadOffset = 8
-  };
+  enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
 
   static const int32_t kNopInstruction =  // nop
       ((AL << kConditionShift) | (0x32 << 20) | (0xf << 12));
 
-  static const int32_t kBreakPointCode = 0xdeb0;  // For breakpoint.
-  static const int32_t kStopMessageCode = 0xdeb1;  // For Stop(message).
+  static const int32_t kBreakPointCode = 0xdeb0;      // For breakpoint.
+  static const int32_t kStopMessageCode = 0xdeb1;     // For Stop(message).
   static const int32_t kSimulatorBreakCode = 0xdeb2;  // For breakpoint in sim.
   static const int32_t kSimulatorRedirectCode = 0xca11;  // For redirection.
 
   // Breakpoint instruction filling assembler code buffers in debug mode.
   static const int32_t kBreakPointInstruction =  // bkpt(0xdeb0)
       ((AL << kConditionShift) | (0x12 << 20) | (0xdeb << 8) | (0x7 << 4));
 
   // Breakpoint instruction used by the simulator.
   // Should be distinct from kBreakPointInstruction and from a typical user
   // breakpoint inserted in generated code for debugging, e.g. bkpt(0).
   static const int32_t kSimulatorBreakpointInstruction =
       // svc #kBreakpointSvcCode
       ((AL << kConditionShift) | (0xf << 24) | kSimulatorBreakCode);
 
   // Runtime call redirection instruction used by the simulator.
   static const int32_t kSimulatorRedirectInstruction =
       ((AL << kConditionShift) | (0xf << 24) | kSimulatorRedirectCode);
 
   // Get the raw instruction bits.
   inline int32_t InstructionBits() const {
     return *reinterpret_cast<const int32_t*>(this);
   }
 
   // Set the raw instruction bits to value.
   inline void SetInstructionBits(int32_t value) {
     *reinterpret_cast<int32_t*>(this) = value;
   }
 
   // Read one particular bit out of the instruction bits.
-  inline int Bit(int nr) const {
-    return (InstructionBits() >> nr) & 1;
-  }
+  inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
 
   // Read a bit field out of the instruction bits.
   inline int Bits(int shift, int count) const {
     return (InstructionBits() >> shift) & ((1 << count) - 1);
   }
 
 
   // Accessors for the different named fields used in the ARM encoding.
   // The naming of these accessor corresponds to figure A3-1.
   // Generally applicable fields
   inline Condition ConditionField() const {
     return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
   }
   inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
 
-  inline Register RnField() const { return static_cast<Register>(
-                                        Bits(kRnShift, kRnBits)); }
-  inline Register RdField() const { return static_cast<Register>(
-                                        Bits(kRdShift, kRdBits)); }
+  inline Register RnField() const {
+    return static_cast<Register>(Bits(kRnShift, kRnBits));
+  }
+  inline Register RdField() const {
+    return static_cast<Register>(Bits(kRdShift, kRdBits));
+  }
 
   // Fields used in Data processing instructions
   inline Opcode OpcodeField() const {
     return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
   }
   inline int SField() const { return Bits(kSShift, kSBits); }
   // with register
   inline Register RmField() const {
     return static_cast<Register>(Bits(kRmShift, kRmBits));
   }
-  inline Shift ShiftField() const { return static_cast<Shift>(
-                                        Bits(kShiftShift, kShiftBits)); }
+  inline Shift ShiftField() const {
+    return static_cast<Shift>(Bits(kShiftShift, kShiftBits));
+  }
   inline int RegShiftField() const { return Bit(4); }
   inline Register RsField() const {
     return static_cast<Register>(Bits(kRsShift, kRsBits));
   }
-  inline int ShiftAmountField() const { return Bits(kShiftImmShift,
-                                                    kShiftImmBits); }
+  inline int ShiftAmountField() const {
+    return Bits(kShiftImmShift, kShiftImmBits);
+  }
   // with immediate
   inline int RotateField() const { return Bits(kRotateShift, kRotateBits); }
   inline int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
 
   // Fields used in Load/Store instructions
   inline int PUField() const { return Bits(23, 2); }
-  inline int  BField() const { return Bit(22); }
-  inline int  WField() const { return Bit(21); }
-  inline int  LField() const { return Bit(20); }
+  inline int BField() const { return Bit(22); }
+  inline int WField() const { return Bit(21); }
+  inline int LField() const { return Bit(20); }
   // with register uses same fields as Data processing instructions above
   // with immediate
-  inline int Offset12Field() const { return Bits(kOffset12Shift,
-                                                 kOffset12Bits); }
+  inline int Offset12Field() const {
+    return Bits(kOffset12Shift, kOffset12Bits);
+  }
   // multiple
   inline int RlistField() const { return Bits(0, 16); }
   // extra loads and stores
   inline int SignField() const { return Bit(6); }
   inline int HField() const { return Bit(5); }
   inline int ImmedHField() const { return Bits(8, 4); }
   inline int ImmedLField() const { return Bits(0, 4); }
 
   // Fields used in Branch instructions
   inline int LinkField() const { return Bits(kLinkShift, kLinkBits); }
@@ skipping 14 matching lines @@
 
   // Field used in VFP float immediate move instruction
   inline float ImmFloatField() const {
     uint32_t imm32 = (Bit(19) << 31) | (((1 << 5) - Bit(18)) << 25) |
                      (Bits(16, 2) << 23) | (Bits(0, 4) << 19);
     return bit_cast<float, uint32_t>(imm32);
   }
 
   // Field used in VFP double immediate move instruction
   inline double ImmDoubleField() const {
-    uint64_t imm64 = (Bit(19)*(1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
-                     (Bits(16, 2)*(1LL << 52)) | (Bits(0, 4)*(1LL << 48));
+    uint64_t imm64 = (Bit(19) * (1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
+                     (Bits(16, 2) * (1LL << 52)) | (Bits(0, 4) * (1LL << 48));
     return bit_cast<double, uint64_t>(imm64);
   }
 
   inline Register DivRdField() const {
     return static_cast<Register>(Bits(kDivRdShift, kDivRdBits));
   }
   inline Register DivRmField() const {
     return static_cast<Register>(Bits(kDivRmShift, kDivRmBits));
   }
   inline Register DivRnField() const {
     return static_cast<Register>(Bits(kDivRnShift, kDivRnBits));
   }
 
   // Test for data processing instructions of type 0 or 1.
   // See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
   // section A5.1 "ARM instruction set encoding".
   inline bool IsDataProcessing() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(Bits(26, 2) == 0);  // Type 0 or 1.
     return ((Bits(20, 5) & 0x19) != 0x10) &&
-      ((Bit(25) == 1) ||  // Data processing immediate.
-       (Bit(4) == 0) ||  // Data processing register.
-       (Bit(7) == 0));  // Data processing register-shifted register.
+           ((Bit(25) == 1) ||  // Data processing immediate.
+            (Bit(4) == 0) ||   // Data processing register.
+            (Bit(7) == 0));    // Data processing register-shifted register.
   }
 
   // Tests for special encodings of type 0 instructions (extra loads and stores,
   // as well as multiplications, synchronization primitives, and miscellaneous).
   // Can only be called for a type 0 or 1 instruction.
   inline bool IsMiscellaneous() const {
     ASSERT(Bits(26, 2) == 0);  // Type 0 or 1.
     return ((Bit(25) == 0) && ((Bits(20, 5) & 0x19) == 0x10) && (Bit(7) == 0));
   }
   inline bool IsMultiplyOrSyncPrimitive() const {
@@ skipping 39 matching lines @@
     return static_cast<QRegister>(bits >> 1);
   }
   inline QRegister QmField() const {
     const intptr_t bits = Bits(kRmShift, kRmBits) + (Bit(5) << 4);
     return static_cast<QRegister>(bits >> 1);
   }
 
   inline bool IsDivision() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(TypeField() == 3);
-    return ((Bit(4) == 1) && (Bits(5, 3) == 0) &&
-            (Bit(20) == 1) && (Bits(22, 3) == 4));
+    return ((Bit(4) == 1) && (Bits(5, 3) == 0) && (Bit(20) == 1) &&
+            (Bits(22, 3) == 4));
   }
 
   // Test for VFP data processing or single transfer instructions of type 7.
   inline bool IsVFPDataProcessingOrSingleTransfer() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(TypeField() == 7);
     return ((Bit(24) == 0) && (Bits(9, 3) == 5));
     // Bit(4) == 0: Data Processing
     // Bit(4) == 1: 8, 16, or 32-bit Transfer between ARM Core and VFP
   }
@@ skipping 25 matching lines @@
     ASSERT(ConditionField() == kSpecialCondition);
     return (Bits(25, 3) == 1);
   }
 
   inline bool IsSIMDLoadStore() const {
     ASSERT(ConditionField() == kSpecialCondition);
     return (Bits(24, 4) == 4) && (Bit(20) == 0);
   }
 
   // Special accessors that test for existence of a value.
-  inline bool HasS()    const { return SField() == 1; }
-  inline bool HasB()    const { return BField() == 1; }
-  inline bool HasW()    const { return WField() == 1; }
-  inline bool HasL()    const { return LField() == 1; }
+  inline bool HasS() const { return SField() == 1; }
+  inline bool HasB() const { return BField() == 1; }
+  inline bool HasW() const { return WField() == 1; }
+  inline bool HasL() const { return LField() == 1; }
   inline bool HasSign() const { return SignField() == 1; }
-  inline bool HasH()    const { return HField() == 1; }
+  inline bool HasH() const { return HField() == 1; }
   inline bool HasLink() const { return LinkField() == 1; }
 
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // RUNTIME_VM_CONSTANTS_ARM_H_