clang-format runtime/vm

runtime/vm/assembler_x64.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/heap.h"
@@ skipping 469 matching lines @@
 void Assembler::cmovlessq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0x4C);
   EmitOperand(dst & 7, operand);
 }
 
 
-
 void Assembler::movss(XmmRegister dst, const Address& src) {
   ASSERT(dst <= XMM15);
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitREX_RB(dst, src);
   EmitUint8(0x0F);
   EmitUint8(0x10);
   EmitOperand(dst & 7, src);
 }
 
@@ skipping 2284 matching lines @@
 
 
 void Assembler::LoadObjectHelper(Register dst,
                                  const Object& object,
                                  bool is_unique) {
   ASSERT(!object.IsICData() || ICData::Cast(object).IsOriginal());
   ASSERT(!object.IsField() || Field::Cast(object).IsOriginal());
   if (Thread::CanLoadFromThread(object)) {
     movq(dst, Address(THR, Thread::OffsetFromThread(object)));
   } else if (CanLoadFromObjectPool(object)) {
-    const intptr_t idx =
-        is_unique ? object_pool_wrapper_.AddObject(object)
-                  : object_pool_wrapper_.FindObject(object);
+    const intptr_t idx = is_unique ? object_pool_wrapper_.AddObject(object)
+                                   : object_pool_wrapper_.FindObject(object);
     const int32_t offset = ObjectPool::element_offset(idx);
     LoadWordFromPoolOffset(dst, offset - kHeapObjectTag);
   } else {
     ASSERT(object.IsSmi());
     LoadImmediate(dst, Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
 void Assembler::LoadFunctionFromCalleePool(Register dst,
@@ skipping 48 matching lines @@
 }
 
 
 void Assembler::CompareObject(Register reg, const Object& object) {
   ASSERT(!object.IsICData() || ICData::Cast(object).IsOriginal());
   ASSERT(!object.IsField() || Field::Cast(object).IsOriginal());
   if (Thread::CanLoadFromThread(object)) {
     cmpq(reg, Address(THR, Thread::OffsetFromThread(object)));
   } else if (CanLoadFromObjectPool(object)) {
     const intptr_t idx = object_pool_wrapper_.FindObject(object, kNotPatchable);
-    const int32_t offset =  ObjectPool::element_offset(idx);
-    cmpq(reg, Address(PP, offset-kHeapObjectTag));
+    const int32_t offset = ObjectPool::element_offset(idx);
+    cmpq(reg, Address(PP, offset - kHeapObjectTag));
   } else {
     ASSERT(object.IsSmi());
-    CompareImmediate(
-        reg, Immediate(reinterpret_cast<int64_t>(object.raw())));
+    CompareImmediate(reg, Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
 intptr_t Assembler::FindImmediate(int64_t imm) {
   return object_pool_wrapper_.FindImmediate(imm);
 }
 
 
 void Assembler::LoadImmediate(Register reg, const Immediate& imm) {
@@ skipping 43 matching lines @@
   // For the value we are only interested in the new/old bit and the tag bit.
   andl(value, Immediate(kNewObjectAlignmentOffset | kHeapObjectTag));
   // Shift the tag bit into the carry.
   shrl(value, Immediate(1));
   // Add the tag bits together, if the value is not a Smi the addition will
   // overflow into the next bit, leaving us with a zero low bit.
   adcl(value, object);
   // Mask out higher, uninteresting bits which were polluted by dest.
   andl(value, Immediate(kObjectAlignment - 1));
   // Compare with the expected bit pattern.
-  cmpl(value, Immediate(
-      (kNewObjectAlignmentOffset >> 1) + kHeapObjectTag +
-      kOldObjectAlignmentOffset + kHeapObjectTag));
+  cmpl(value, Immediate((kNewObjectAlignmentOffset >> 1) + kHeapObjectTag +
+                        kOldObjectAlignmentOffset + kHeapObjectTag));
   j(NOT_ZERO, no_update, Assembler::kNearJump);
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
   movq(dest, value);
@@ skipping 417 matching lines @@
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   movq(temp_reg, Address(temp_reg, table_offset));
   testb(Address(temp_reg, state_offset),
         Immediate(ClassHeapStats::TraceAllocationMask()));
   // We are tracing for this class, jump to the trace label which will use
   // the allocation stub.
   j(NOT_ZERO, trace, near_jump);
 }
 
 
-void Assembler::UpdateAllocationStats(intptr_t cid,
-                                      Heap::Space space) {
+void Assembler::UpdateAllocationStats(intptr_t cid, Heap::Space space) {
   ASSERT(cid > 0);
   intptr_t counter_offset =
       ClassTable::CounterOffsetFor(cid, space == Heap::kNew);
   Register temp_reg = TMP;
   LoadIsolate(temp_reg);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   movq(temp_reg, Address(temp_reg, table_offset));
   incq(Address(temp_reg, counter_offset));
 }
@@ skipping 113 matching lines @@
     return;
   }
   intptr_t bytes_needed = alignment - mod;
   while (bytes_needed > MAX_NOP_SIZE) {
     nop(MAX_NOP_SIZE);
     bytes_needed -= MAX_NOP_SIZE;
   }
   if (bytes_needed) {
     nop(bytes_needed);
   }
-  ASSERT(((offset + buffer_.GetPosition()) & (alignment-1)) == 0);
+  ASSERT(((offset + buffer_.GetPosition()) & (alignment - 1)) == 0);
 }
 
 
 void Assembler::EmitOperand(int rm, const Operand& operand) {
   ASSERT(rm >= 0 && rm < 8);
   const intptr_t length = operand.length_;
   ASSERT(length > 0);
   // Emit the ModRM byte updated with the given RM value.
   ASSERT((operand.encoding_[0] & 0x38) == 0);
   EmitUint8(operand.encoding_[0] + (rm << 3));
@@ skipping 104 matching lines @@
   }
   EmitUint8(0xD3);
   EmitOperand(rm, Operand(operand));
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == kBitsPerInt32);
   ASSERT(RawObject::kClassIdTagSize == kBitsPerInt32);
   ASSERT(sizeof(classid_t) == sizeof(uint32_t));
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
   movl(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
   movq(result, Address(result, offset));
@@ skipping 13 matching lines @@
 }
 
 
 void Assembler::SmiUntagOrCheckClass(Register object,
                                      intptr_t class_id,
                                      Label* is_smi) {
   ASSERT(kSmiTagShift == 1);
   ASSERT(RawObject::kClassIdTagPos == kBitsPerInt32);
   ASSERT(RawObject::kClassIdTagSize == kBitsPerInt32);
   ASSERT(sizeof(classid_t) == sizeof(uint32_t));
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
 
   // Untag optimistically. Tag bit is shifted into the CARRY.
   SmiUntag(object);
   j(NOT_CARRY, is_smi, kNearJump);
   // Load cid: can't use LoadClassId, object is untagged. Use TIMES_2 scale
   // factor in the addressing mode to compensate for this.
   movl(TMP, Address(object, TIMES_2, class_id_offset));
   cmpl(TMP, Immediate(class_id));
 }
 
@@ skipping 27 matching lines @@
 
 Address Assembler::ElementAddressForIntIndex(bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index) {
   if (is_external) {
     return Address(array, index * index_scale);
   } else {
     const int64_t disp = static_cast<int64_t>(index) * index_scale +
-        Instance::DataOffsetFor(cid);
+                         Instance::DataOffsetFor(cid);
     ASSERT(Utils::IsInt(32, disp));
     return FieldAddress(array, static_cast<int32_t>(disp));
   }
 }
 
 
 static ScaleFactor ToScaleFactor(intptr_t index_scale) {
   // Note that index is expected smi-tagged, (i.e, times 2) for all arrays with
   // index scale factor > 1. E.g., for Uint8Array and OneByteString the index is
   // expected to be untagged before accessing.
   ASSERT(kSmiTagShift == 1);
   switch (index_scale) {
-    case 1: return TIMES_1;
-    case 2: return TIMES_1;
-    case 4: return TIMES_2;
-    case 8: return TIMES_4;
-    case 16: return TIMES_8;
+    case 1:
+      return TIMES_1;
+    case 2:
+      return TIMES_1;
+    case 4:
+      return TIMES_2;
+    case 8:
+      return TIMES_4;
+    case 16:
+      return TIMES_8;
     default:
       UNREACHABLE();
       return TIMES_1;
   }
 }
 
 
 Address Assembler::ElementAddressForRegIndex(bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              Register index) {
   if (is_external) {
     return Address(array, index, ToScaleFactor(index_scale), 0);
   } else {
-    return FieldAddress(array,
-                        index,
-                        ToScaleFactor(index_scale),
+    return FieldAddress(array, index, ToScaleFactor(index_scale),
                         Instance::DataOffsetFor(cid));
   }
 }
 
 
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
-  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
-  "r8", "r9", "r10", "r11", "r12", "r13", "thr", "pp"
-};
+    "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
+    "r8",  "r9",  "r10", "r11", "r12", "r13", "thr", "pp"};
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* xmm_reg_names[kNumberOfXmmRegisters] = {
-  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
-  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
-};
+    "xmm0", "xmm1", "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",  "xmm7",
+    "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"};
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64