clang-format runtime/vm

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef RUNTIME_VM_ASSEMBLER_MIPS_H_
 #define RUNTIME_VM_ASSEMBLER_MIPS_H_
 
 #ifndef RUNTIME_VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 12 matching lines @@
 // "MIPS® Architecture For Programmers Volume II-A:
 //   The MIPS32® Instruction Set" in short "VolII-A"
 namespace dart {
 
 // Forward declarations.
 class RuntimeEntry;
 class StubEntry;
 
 class Immediate : public ValueObject {
  public:
-  explicit Immediate(int32_t value) : value_(value) { }
+  explicit Immediate(int32_t value) : value_(value) {}
 
-  Immediate(const Immediate& other) : ValueObject(), value_(other.value_) { }
+  Immediate(const Immediate& other) : ValueObject(), value_(other.value_) {}
   Immediate& operator=(const Immediate& other) {
     value_ = other.value_;
     return *this;
   }
 
  private:
   int32_t value_;
 
   int32_t value() const { return value_; }
 
   friend class Assembler;
 };
 
 
 class Address : public ValueObject {
  public:
   explicit Address(Register base, int32_t offset = 0)
-      : ValueObject(), base_(base), offset_(offset) { }
+      : ValueObject(), base_(base), offset_(offset) {}
 
   // This addressing mode does not exist.
   Address(Register base, Register offset);
 
   Address(const Address& other)
-      : ValueObject(), base_(other.base_), offset_(other.offset_) { }
+      : ValueObject(), base_(other.base_), offset_(other.offset_) {}
   Address& operator=(const Address& other) {
     base_ = other.base_;
     offset_ = other.offset_;
     return *this;
   }
 
   uint32_t encoding() const {
     ASSERT(Utils::IsInt(kImmBits, offset_));
     uint16_t imm_value = static_cast<uint16_t>(offset_);
     return (base_ << kRsShift) | imm_value;
   }
 
   static bool CanHoldOffset(int32_t offset) {
     return Utils::IsInt(kImmBits, offset);
   }
 
   Register base() const { return base_; }
   int32_t offset() const { return offset_; }
 
  private:
   Register base_;
   int32_t offset_;
 };
 
 
 class FieldAddress : public Address {
  public:
   FieldAddress(Register base, int32_t disp)
-      : Address(base, disp - kHeapObjectTag) { }
+      : Address(base, disp - kHeapObjectTag) {}
 
-  FieldAddress(const FieldAddress& other) : Address(other) { }
+  FieldAddress(const FieldAddress& other) : Address(other) {}
 
   FieldAddress& operator=(const FieldAddress& other) {
     Address::operator=(other);
     return *this;
   }
 };
 
 
 class Label : public ValueObject {
  public:
-  Label() : position_(0) { }
+  Label() : position_(0) {}
 
   ~Label() {
     // Assert if label is being destroyed with unresolved branches pending.
     ASSERT(!IsLinked());
   }
 
   // Returns the position for bound and linked labels. Cannot be used
   // for unused labels.
   intptr_t Position() const {
     ASSERT(!IsUnused());
     return IsBound() ? -position_ - kWordSize : position_ - kWordSize;
   }
 
   bool IsBound() const { return position_ < 0; }
   bool IsUnused() const { return position_ == 0; }
   bool IsLinked() const { return position_ > 0; }
 
  private:
   intptr_t position_;
 
-  void Reinitialize() {
-    position_ = 0;
-  }
+  void Reinitialize() { position_ = 0; }
 
   void BindTo(intptr_t position) {
     ASSERT(!IsBound());
     position_ = -position - kWordSize;
     ASSERT(IsBound());
   }
 
   void LinkTo(intptr_t position) {
     ASSERT(!IsBound());
     position_ = position + kWordSize;
@@ skipping 18 matching lines @@
     kRightPos = kLeftPos + kLeftSize,
     kRightSize = 6,
     kRelOpPos = kRightPos + kRightSize,
     kRelOpSize = 4,
     kImmPos = kRelOpPos + kRelOpSize,
     kImmSize = 16,
   };
 
   class LeftBits : public BitField<uword, Register, kLeftPos, kLeftSize> {};
   class RightBits : public BitField<uword, Register, kRightPos, kRightSize> {};
-  class RelOpBits :
-      public BitField<uword, RelationOperator, kRelOpPos, kRelOpSize> {};
+  class RelOpBits
+      : public BitField<uword, RelationOperator, kRelOpPos, kRelOpSize> {};
   class ImmBits : public BitField<uword, uint16_t, kImmPos, kImmSize> {};
 
   Register left() const { return LeftBits::decode(bits_); }
   Register right() const { return RightBits::decode(bits_); }
   RelationOperator rel_op() const { return RelOpBits::decode(bits_); }
   int16_t imm() const { return static_cast<int16_t>(ImmBits::decode(bits_)); }
 
   static bool IsValidImm(int32_t value) {
     // We want both value and value + 1 to fit in an int16_t.
     return (-0x08000 <= value) && (value < 0x7fff);
   }
 
   void set_rel_op(RelationOperator value) {
     ASSERT(IsValidRelOp(value));
     bits_ = RelOpBits::update(value, bits_);
   }
 
   // Uninitialized condition.
-  Condition() : ValueObject(), bits_(0) { }
+  Condition() : ValueObject(), bits_(0) {}
 
   // Copy constructor.
-  Condition(const Condition& other) : ValueObject(), bits_(other.bits_) { }
+  Condition(const Condition& other) : ValueObject(), bits_(other.bits_) {}
 
   // Copy assignment operator.
   Condition& operator=(const Condition& other) {
     bits_ = other.bits_;
     return *this;
   }
 
   Condition(Register left,
             Register right,
             RelationOperator rel_op,
@@ skipping 40 matching lines @@
 class Assembler : public ValueObject {
  public:
   explicit Assembler(bool use_far_branches = false)
       : buffer_(),
         prologue_offset_(-1),
         has_single_entry_point_(true),
         use_far_branches_(use_far_branches),
         delay_slot_available_(false),
         in_delay_slot_(false),
         comments_(),
-        constant_pool_allowed_(true) {
-  }
-  ~Assembler() { }
+        constant_pool_allowed_(true) {}
+  ~Assembler() {}
 
   void PopRegister(Register r) { Pop(r); }
 
   void Bind(Label* label);
   void Jump(Label* label) { b(label); }
 
   // Misc. functionality
   intptr_t CodeSize() const { return buffer_.Size(); }
   intptr_t prologue_offset() const { return prologue_offset_; }
   bool has_single_entry_point() const { return has_single_entry_point_; }
 
   // Count the fixups that produce a pointer offset, without processing
   // the fixups.
-  intptr_t CountPointerOffsets() const {
-    return buffer_.CountPointerOffsets();
-  }
+  intptr_t CountPointerOffsets() const { return buffer_.CountPointerOffsets(); }
 
   const ZoneGrowableArray<intptr_t>& GetPointerOffsets() const {
     return buffer_.pointer_offsets();
   }
 
   ObjectPoolWrapper& object_pool_wrapper() { return object_pool_wrapper_; }
 
   RawObjectPool* MakeObjectPool() {
     return object_pool_wrapper_.MakeObjectPool();
   }
 
   void FinalizeInstructions(const MemoryRegion& region) {
     buffer_.FinalizeInstructions(region);
   }
 
   bool use_far_branches() const {
     return FLAG_use_far_branches || use_far_branches_;
   }
 
-  void set_use_far_branches(bool b) {
-    use_far_branches_ = b;
-  }
+  void set_use_far_branches(bool b) { use_far_branches_ = b; }
 
   void EnterFrame();
   void LeaveFrameAndReturn();
 
   // Set up a stub frame so that the stack traversal code can easily identify
   // a stub frame.
   void EnterStubFrame(intptr_t frame_size = 0);
   void LeaveStubFrame();
   // A separate macro for when a Ret immediately follows, so that we can use
   // the branch delay slot.
   void LeaveStubFrameAndReturn(Register ra = RA);
 
   void MonomorphicCheckedEntry();
 
   void UpdateAllocationStats(intptr_t cid,
                              Register temp_reg,
                              Heap::Space space);
 
   void UpdateAllocationStatsWithSize(intptr_t cid,
                                      Register size_reg,
                                      Register temp_reg,
                                      Heap::Space space);
 
 
-  void MaybeTraceAllocation(intptr_t cid,
-                            Register temp_reg,
-                            Label* trace);
+  void MaybeTraceAllocation(intptr_t cid, Register temp_reg, Label* trace);
 
   // Inlined allocation of an instance of class 'cls', code has no runtime
   // calls. Jump to 'failure' if the instance cannot be allocated here.
   // Allocated instance is returned in 'instance_reg'.
   // Only the tags field of the object is initialized.
   void TryAllocate(const Class& cls,
                    Label* failure,
                    Register instance_reg,
                    Register temp_reg);
 
@@ skipping 25 matching lines @@
   void SetPrologueOffset() {
     if (prologue_offset_ == -1) {
       prologue_offset_ = CodeSize();
     }
   }
 
   // A utility to be able to assemble an instruction into the delay slot.
   Assembler* delay_slot() {
     ASSERT(delay_slot_available_);
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
-        Instr::kNopInstruction);
+           Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions in alphabetical order.
   void addd(DRegister dd, DRegister ds, DRegister dt) {
     // DRegisters start at the even FRegisters.
     FRegister fd = static_cast<FRegister>(dd * 2);
@@ skipping 16 matching lines @@
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
   }
 
   void andi(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ANDI, rs, rt, imm_value);
   }
 
   // Unconditional branch.
-  void b(Label* l) {
-    beq(R0, R0, l);
-  }
+  void b(Label* l) { beq(R0, R0, l); }
 
-  void bal(Label *l) {
+  void bal(Label* l) {
     ASSERT(!in_delay_slot_);
     EmitRegImmBranch(BGEZAL, R0, l);
     EmitBranchDelayNop();
   }
 
   // Branch on floating point false.
   void bc1f(Label* l) {
     EmitFpuBranch(false, l);
     EmitBranchDelayNop();
   }
@@ skipping 89 matching lines @@
   // Branch if not equal, likely taken.
   // Delay slot executed only when branch taken.
   void bnel(Register rs, Register rt, Label* l) {
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitBranch(BNEL, rs, rt, l);
     EmitBranchDelayNop();
   }
 
   static int32_t BreakEncoding(int32_t code) {
     ASSERT(Utils::IsUint(20, code));
-    return SPECIAL << kOpcodeShift |
-           code << kBreakCodeShift |
+    return SPECIAL << kOpcodeShift | code << kBreakCodeShift |
            BREAK << kFunctionShift;
   }
 
 
-  void break_(int32_t code) {
-    Emit(BreakEncoding(code));
-  }
+  void break_(int32_t code) { Emit(BreakEncoding(code)); }
 
-  static uword GetBreakInstructionFiller() {
-    return BreakEncoding(0);
-  }
+  static uword GetBreakInstructionFiller() { return BreakEncoding(0); }
 
   // FPU compare, always false.
   void cfd(DRegister ds, DRegister dt) {
     FRegister fs = static_cast<FRegister>(ds * 2);
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_F);
   }
 
   // FPU compare, true if unordered, i.e. one is NaN.
   void cund(DRegister ds, DRegister dt) {
@@ skipping 69 matching lines @@
     FRegister fd = static_cast<FRegister>(dd * 2);
     EmitFpuRType(COP1, FMT_W, F0, fs, fd, COP1_CVT_D);
   }
 
   // Convert a 64-bit double in ds to a 32-bit float in fd.
   void cvtsd(FRegister fd, DRegister ds) {
     FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_CVT_S);
   }
 
-  void div(Register rs, Register rt) {
-    EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
-  }
+  void div(Register rs, Register rt) { EmitRType(SPECIAL, rs, rt, R0, 0, DIV); }
 
   void divd(DRegister dd, DRegister ds, DRegister dt) {
     FRegister fd = static_cast<FRegister>(dd * 2);
     FRegister fs = static_cast<FRegister>(ds * 2);
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_DIV);
   }
 
   void divu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
   void jalr(Register rs, Register rd = RA) {
     ASSERT(rs != rd);
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, rd, 0, JALR);
     EmitBranchDelayNop();
   }
 
   void jr(Register rs) {
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, R0, 0, JR);
     EmitBranchDelayNop();
   }
 
-  void lb(Register rt, const Address& addr) {
-    EmitLoadStore(LB, rt, addr);
-  }
+  void lb(Register rt, const Address& addr) { EmitLoadStore(LB, rt, addr); }
 
-  void lbu(Register rt, const Address& addr) {
-    EmitLoadStore(LBU, rt, addr);
-  }
+  void lbu(Register rt, const Address& addr) { EmitLoadStore(LBU, rt, addr); }
 
   void ldc1(DRegister dt, const Address& addr) {
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuLoadStore(LDC1, ft, addr);
   }
 
-  void lh(Register rt, const Address& addr) {
-    EmitLoadStore(LH, rt, addr);
-  }
+  void lh(Register rt, const Address& addr) { EmitLoadStore(LH, rt, addr); }
 
-  void lhu(Register rt, const Address& addr) {
-    EmitLoadStore(LHU, rt, addr);
-  }
+  void lhu(Register rt, const Address& addr) { EmitLoadStore(LHU, rt, addr); }
 
-  void ll(Register rt, const Address& addr) {
-    EmitLoadStore(LL, rt, addr);
-  }
+  void ll(Register rt, const Address& addr) { EmitLoadStore(LL, rt, addr); }
 
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
-  void lw(Register rt, const Address& addr) {
-    EmitLoadStore(LW, rt, addr);
-  }
+  void lw(Register rt, const Address& addr) { EmitLoadStore(LW, rt, addr); }
 
   void lwc1(FRegister ft, const Address& addr) {
     EmitFpuLoadStore(LWC1, ft, addr);
   }
 
   void madd(Register rs, Register rt) {
     EmitRType(SPECIAL2, rs, rt, R0, 0, MADD);
   }
 
   void maddu(Register rs, Register rt) {
     EmitRType(SPECIAL2, rs, rt, R0, 0, MADDU);
   }
 
   void mfc1(Register rt, FRegister fs) {
-    Emit(COP1 << kOpcodeShift |
-         COP1_MF << kCop1SubShift |
-         rt << kRtShift |
+    Emit(COP1 << kOpcodeShift | COP1_MF << kCop1SubShift | rt << kRtShift |
          fs << kFsShift);
   }
 
-  void mfhi(Register rd) {
-    EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
-  }
+  void mfhi(Register rd) { EmitRType(SPECIAL, R0, R0, rd, 0, MFHI); }
 
-  void mflo(Register rd) {
-    EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
-  }
+  void mflo(Register rd) { EmitRType(SPECIAL, R0, R0, rd, 0, MFLO); }
 
-  void mov(Register rd, Register rs) {
-    or_(rd, rs, ZR);
-  }
+  void mov(Register rd, Register rs) { or_(rd, rs, ZR); }
 
   void movd(DRegister dd, DRegister ds) {
     FRegister fd = static_cast<FRegister>(dd * 2);
     FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_MOV);
   }
 
   // Move if floating point false.
   void movf(Register rd, Register rs) {
     EmitRType(SPECIAL, rs, R0, rd, 0, MOVCI);
@@ skipping 11 matching lines @@
   // rd <- (rt == 0) ? rs : rd;
   void movz(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ);
   }
 
   void movs(FRegister fd, FRegister fs) {
     EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV);
   }
 
   void mtc1(Register rt, FRegister fs) {
-    Emit(COP1 << kOpcodeShift |
-         COP1_MT << kCop1SubShift |
-         rt << kRtShift |
+    Emit(COP1 << kOpcodeShift | COP1_MT << kCop1SubShift | rt << kRtShift |
          fs << kFsShift);
   }
 
-  void mthi(Register rs) {
-    EmitRType(SPECIAL, rs, R0, R0, 0, MTHI);
-  }
+  void mthi(Register rs) { EmitRType(SPECIAL, rs, R0, R0, 0, MTHI); }
 
-  void mtlo(Register rs) {
-    EmitRType(SPECIAL, rs, R0, R0, 0, MTLO);
-  }
+  void mtlo(Register rs) { EmitRType(SPECIAL, rs, R0, R0, 0, MTLO); }
 
   void muld(DRegister dd, DRegister ds, DRegister dt) {
     FRegister fd = static_cast<FRegister>(dd * 2);
     FRegister fs = static_cast<FRegister>(ds * 2);
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_MUL);
   }
 
   void mult(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULT);
   }
 
   void multu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULTU);
   }
 
   void negd(DRegister dd, DRegister ds) {
     FRegister fd = static_cast<FRegister>(dd * 2);
     FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_NEG);
   }
 
-  void nop() {
-    Emit(Instr::kNopInstruction);
-  }
+  void nop() { Emit(Instr::kNopInstruction); }
 
   void nor(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, NOR);
   }
 
   void or_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, OR);
   }
 
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
-  void sb(Register rt, const Address& addr) {
-    EmitLoadStore(SB, rt, addr);
-  }
+  void sb(Register rt, const Address& addr) { EmitLoadStore(SB, rt, addr); }
 
   // rt = 1 on success, 0 on failure.
-  void sc(Register rt, const Address& addr) {
-    EmitLoadStore(SC, rt, addr);
-  }
+  void sc(Register rt, const Address& addr) { EmitLoadStore(SC, rt, addr); }
 
   void sdc1(DRegister dt, const Address& addr) {
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuLoadStore(SDC1, ft, addr);
   }
 
-  void sh(Register rt, const Address& addr) {
-    EmitLoadStore(SH, rt, addr);
-  }
+  void sh(Register rt, const Address& addr) { EmitLoadStore(SH, rt, addr); }
 
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
 
   void sllv(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLLV);
   }
 
   void slt(Register rd, Register rs, Register rt) {
@@ skipping 45 matching lines @@
     FRegister fd = static_cast<FRegister>(dd * 2);
     FRegister fs = static_cast<FRegister>(ds * 2);
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_SUB);
   }
 
   void subu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SUBU);
   }
 
-  void sw(Register rt, const Address& addr) {
-    EmitLoadStore(SW, rt, addr);
-  }
+  void sw(Register rt, const Address& addr) { EmitLoadStore(SW, rt, addr); }
 
   void swc1(FRegister ft, const Address& addr) {
     EmitFpuLoadStore(SWC1, ft, addr);
   }
 
   void xori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(XORI, rs, rt, imm_value);
   }
 
   void xor_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, XOR);
   }
 
   // Macros in alphabetical order.
 
   // Addition of rs and rt with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
   // rd and ro must not be TMP.
   // ro must be different from all the other registers.
   // If rd, rs, and rt are the same register, then a scratch register different
   // from the other registers is needed.
-  void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro,
+  void AdduDetectOverflow(Register rd,
+                          Register rs,
+                          Register rt,
+                          Register ro,
                           Register scratch = kNoRegister);
 
   // ro must be different from rd and rs.
   // rd and ro must not be TMP.
   // If rd and rs are the same, a scratch register different from the other
   // registers is needed.
-  void AddImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
-                                  Register ro, Register scratch = kNoRegister) {
+  void AddImmediateDetectOverflow(Register rd,
+                                  Register rs,
+                                  int32_t imm,
+                                  Register ro,
+                                  Register scratch = kNoRegister) {
     ASSERT(!in_delay_slot_);
     LoadImmediate(rd, imm);
     AdduDetectOverflow(rd, rs, rd, ro, scratch);
   }
 
   // Subtraction of rt from rs (rs - rt) with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
   // None of rd, rs, rt, or ro may be TMP.
   // ro must be different from the other registers.
   void SubuDetectOverflow(Register rd, Register rs, Register rt, Register ro);
 
   // ro must be different from rd and rs.
   // None of rd, rs, rt, or ro may be TMP.
-  void SubImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
+  void SubImmediateDetectOverflow(Register rd,
+                                  Register rs,
+                                  int32_t imm,
                                   Register ro) {
     ASSERT(!in_delay_slot_);
     LoadImmediate(rd, imm);
     SubuDetectOverflow(rd, rs, rd, ro);
   }
 
   void Branch(const StubEntry& stub_entry, Register pp = PP);
 
   void BranchLink(const StubEntry& stub_entry,
                   Patchability patchable = kNotPatchable);
@@ skipping 149 matching lines @@
     return rd;
   }
 
   // Branch to label if condition is true.
   void BranchOnCondition(Condition cond, Label* l) {
     ASSERT(!in_delay_slot_);
     Register left = cond.left();
     Register right = cond.right();
     RelationOperator rel_op = cond.rel_op();
     switch (rel_op) {
-      case NV: return;
-      case AL: b(l); return;
+      case NV:
+        return;
+      case AL:
+        b(l);
+        return;
       case EQ:  // fall through.
       case NE: {
         if (left == IMM) {
           addiu(AT, ZR, Immediate(cond.imm()));
           left = AT;
         } else if (right == IMM) {
           addiu(AT, ZR, Immediate(cond.imm()));
           right = AT;
         }
         if (rel_op == EQ) {
@@ skipping 119 matching lines @@
           sltu(AT, right, left);
           beq(AT, ZR, l);
         }
         break;
       }
       default:
         UNREACHABLE();
     }
   }
 
-  void BranchEqual(Register rd, Register rn, Label* l) {
-    beq(rd, rn, l);
-  }
+  void BranchEqual(Register rd, Register rn, Label* l) { beq(rd, rn, l); }
 
   void BranchEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       beq(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, imm.value());
       beq(rd, CMPRES2, l);
     }
   }
 
   void BranchEqual(Register rd, const Object& object, Label* l) {
     ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadObject(CMPRES2, object);
     beq(rd, CMPRES2, l);
   }
 
-  void BranchNotEqual(Register rd, Register rn, Label* l) {
-    bne(rd, rn, l);
-  }
+  void BranchNotEqual(Register rd, Register rn, Label* l) { bne(rd, rn, l); }
 
   void BranchNotEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       bne(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, imm.value());
       bne(rd, CMPRES2, l);
     }
@@ skipping 46 matching lines @@
         ASSERT(rd != CMPRES2);
         LoadImmediate(CMPRES2, imm.value());
         BranchUnsignedGreater(rd, CMPRES2, l);
       }
     }
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     slt(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
-    beq(CMPRES2, ZR, l);  // If CMPRES2 = 0, then rd >= rs.
+    beq(CMPRES2, ZR, l);   // If CMPRES2 = 0, then rd >= rs.
   }
 
   void BranchSignedGreaterEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       bgez(rd, l);
     } else {
       if (Utils::IsInt(kImmBits, imm.value())) {
         slti(CMPRES2, rd, imm);
         beq(CMPRES2, ZR, l);
@@ skipping 116 matching lines @@
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
     ASSERT(!in_delay_slot_);
     lw(rt, Address(SP));
     addiu(SP, SP, Immediate(kWordSize));
   }
 
-  void Ret() {
-    jr(RA);
-  }
+  void Ret() { jr(RA); }
 
-  void SmiTag(Register reg) {
-    sll(reg, reg, kSmiTagSize);
-  }
+  void SmiTag(Register reg) { sll(reg, reg, kSmiTagSize); }
 
-  void SmiTag(Register dst, Register src) {
-    sll(dst, src, kSmiTagSize);
-  }
+  void SmiTag(Register dst, Register src) { sll(dst, src, kSmiTagSize); }
 
-  void SmiUntag(Register reg) {
-    sra(reg, reg, kSmiTagSize);
-  }
+  void SmiUntag(Register reg) { sra(reg, reg, kSmiTagSize); }
 
-  void SmiUntag(Register dst, Register src) {
-    sra(dst, src, kSmiTagSize);
-  }
+  void SmiUntag(Register dst, Register src) { sra(dst, src, kSmiTagSize); }
 
   void BranchIfNotSmi(Register reg, Label* label) {
     andi(CMPRES1, reg, Immediate(kSmiTagMask));
     bne(CMPRES1, ZR, label);
   }
 
   void LoadFromOffset(Register reg, Register base, int32_t offset) {
     ASSERT(!in_delay_slot_);
     if (Utils::IsInt(kImmBits, offset)) {
       lw(reg, Address(base, offset));
@@ skipping 63 matching lines @@
   void PushObject(const Object& object);
 
   void LoadIsolate(Register result);
 
   void LoadClassId(Register result, Register object);
   void LoadClassById(Register result, Register class_id);
   void LoadClass(Register result, Register object);
   void LoadClassIdMayBeSmi(Register result, Register object);
   void LoadTaggedClassIdMayBeSmi(Register result, Register object);
 
-  void StoreIntoObject(Register object,  // Object we are storing into.
+  void StoreIntoObject(Register object,      // Object we are storing into.
                        const Address& dest,  // Where we are storing into.
-                       Register value,  // Value we are storing.
+                       Register value,       // Value we are storing.
                        bool can_value_be_smi = true);
   void StoreIntoObjectOffset(Register object,
                              int32_t offset,
                              Register value,
                              bool can_value_be_smi = true);
 
   void StoreIntoObjectNoBarrier(Register object,
                                 const Address& dest,
                                 Register value);
   void StoreIntoObjectNoBarrierOffset(Register object,
@@ skipping 53 matching lines @@
 
   static Address VMTagAddress() {
     return Address(THR, Thread::vm_tag_offset());
   }
 
   // On some other platforms, we draw a distinction between safe and unsafe
   // smis.
   static bool IsSafe(const Object& object) { return true; }
   static bool IsSafeSmi(const Object& object) { return object.IsSmi(); }
 
-  bool constant_pool_allowed() const {
-    return constant_pool_allowed_;
-  }
-  void set_constant_pool_allowed(bool b) {
-    constant_pool_allowed_ = b;
-  }
+  bool constant_pool_allowed() const { return constant_pool_allowed_; }
+  void set_constant_pool_allowed(bool b) { constant_pool_allowed_ = b; }
 
  private:
   AssemblerBuffer buffer_;
   ObjectPoolWrapper object_pool_wrapper_;
 
   intptr_t prologue_offset_;
   bool has_single_entry_point_;
   bool use_far_branches_;
   bool delay_slot_available_;
   bool in_delay_slot_;
 
   class CodeComment : public ZoneAllocated {
    public:
     CodeComment(intptr_t pc_offset, const String& comment)
-        : pc_offset_(pc_offset), comment_(comment) { }
+        : pc_offset_(pc_offset), comment_(comment) {}
 
     intptr_t pc_offset() const { return pc_offset_; }
     const String& comment() const { return comment_; }
 
    private:
     intptr_t pc_offset_;
     const String& comment_;
 
     DISALLOW_COPY_AND_ASSIGN(CodeComment);
   };
@@ skipping 13 matching lines @@
   void Emit(int32_t value) {
     // Emitting an instruction clears the delay slot state.
     in_delay_slot_ = false;
     delay_slot_available_ = false;
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     buffer_.Emit<int32_t>(value);
   }
 
   // Encode CPU instructions according to the types specified in
   // Figures 4-1, 4-2 and 4-3 in VolI-A.
-  void EmitIType(Opcode opcode,
-                 Register rs,
-                 Register rt,
-                 uint16_t imm) {
-    Emit(opcode << kOpcodeShift |
-         rs << kRsShift |
-         rt << kRtShift |
-         imm);
+  void EmitIType(Opcode opcode, Register rs, Register rt, uint16_t imm) {
+    Emit(opcode << kOpcodeShift | rs << kRsShift | rt << kRtShift | imm);
   }
 
-  void EmitLoadStore(Opcode opcode, Register rt,
-                     const Address &addr) {
-    Emit(opcode << kOpcodeShift |
-         rt << kRtShift |
-         addr.encoding());
+  void EmitLoadStore(Opcode opcode, Register rt, const Address& addr) {
+    Emit(opcode << kOpcodeShift | rt << kRtShift | addr.encoding());
   }
 
-  void EmitFpuLoadStore(Opcode opcode, FRegister ft,
-                        const Address &addr) {
-    Emit(opcode << kOpcodeShift |
-         ft << kFtShift |
-         addr.encoding());
+  void EmitFpuLoadStore(Opcode opcode, FRegister ft, const Address& addr) {
+    Emit(opcode << kOpcodeShift | ft << kFtShift | addr.encoding());
   }
 
-  void EmitRegImmType(Opcode opcode,
-                      Register rs,
-                      RtRegImm code,
-                      uint16_t imm) {
-    Emit(opcode << kOpcodeShift |
-         rs << kRsShift |
-         code << kRtShift |
-         imm);
+  void EmitRegImmType(Opcode opcode, Register rs, RtRegImm code, uint16_t imm) {
+    Emit(opcode << kOpcodeShift | rs << kRsShift | code << kRtShift | imm);
   }
 
-  void EmitJType(Opcode opcode, uint32_t destination) {
-    UNIMPLEMENTED();
-  }
+  void EmitJType(Opcode opcode, uint32_t destination) { UNIMPLEMENTED(); }
 
   void EmitRType(Opcode opcode,
                  Register rs,
                  Register rt,
                  Register rd,
                  int sa,
                  SpecialFunction func) {
     ASSERT(Utils::IsUint(5, sa));
-    Emit(opcode << kOpcodeShift |
-         rs << kRsShift |
-         rt << kRtShift |
-         rd << kRdShift |
-         sa << kSaShift |
-         func << kFunctionShift);
+    Emit(opcode << kOpcodeShift | rs << kRsShift | rt << kRtShift |
+         rd << kRdShift | sa << kSaShift | func << kFunctionShift);
   }
 
   void EmitFpuRType(Opcode opcode,
                     Format fmt,
                     FRegister ft,
                     FRegister fs,
                     FRegister fd,
                     Cop1Function func) {
-    Emit(opcode << kOpcodeShift |
-         fmt << kFmtShift |
-         ft << kFtShift |
-         fs << kFsShift |
-         fd << kFdShift |
-         func << kCop1FnShift);
+    Emit(opcode << kOpcodeShift | fmt << kFmtShift | ft << kFtShift |
+         fs << kFsShift | fd << kFdShift | func << kCop1FnShift);
   }
 
   int32_t EncodeBranchOffset(int32_t offset, int32_t instr);
 
   void EmitFarJump(int32_t offset, bool link);
   void EmitFarBranch(Opcode b, Register rs, Register rt, int32_t offset);
   void EmitFarRegImmBranch(RtRegImm b, Register rs, int32_t offset);
   void EmitFarFpuBranch(bool kind, int32_t offset);
   void EmitBranch(Opcode b, Register rs, Register rt, Label* label);
   void EmitRegImmBranch(RtRegImm b, Register rs, Label* label);
-  void EmitFpuBranch(bool kind, Label *label);
+  void EmitFpuBranch(bool kind, Label* label);
 
   void EmitBranchDelayNop() {
     Emit(Instr::kNopInstruction);  // Branch delay NOP.
     delay_slot_available_ = true;
   }
 
   void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
 
   // Shorter filtering sequence that assumes that value is not a smi.
   void StoreIntoObjectFilterNoSmi(Register object,
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // RUNTIME_VM_ASSEMBLER_MIPS_H_