clang-format runtime/vm

runtime/vm/assembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
@@ skipping 34 matching lines @@
 
 static bool CanEncodeBranchOffset(int32_t offset) {
   ASSERT(Utils::IsAligned(offset, 4));
   return Utils::IsInt(18, offset);
 }
 
 
 int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t instr) {
   if (!CanEncodeBranchOffset(offset)) {
     ASSERT(!use_far_branches());
-    Thread::Current()->long_jump_base()->Jump(
-        1, Object::branch_offset_error());
+    Thread::Current()->long_jump_base()->Jump(1, Object::branch_offset_error());
   }
 
   // Properly preserve only the bits supported in the instruction.
   offset >>= 2;
   offset &= kBranchOffsetMask;
   return (instr & ~kBranchOffsetMask) | offset;
 }
 
 
 static intptr_t DecodeBranchOffset(int32_t instr) {
   // Sign-extend, left-shift by 2.
   return (((instr & kBranchOffsetMask) << 16) >> 14);
 }
 
 
 static int32_t DecodeLoadImmediate(int32_t ori_instr, int32_t lui_instr) {
   return (((lui_instr & kBranchOffsetMask) << 16) |
-           (ori_instr & kBranchOffsetMask));
+          (ori_instr & kBranchOffsetMask));
 }
 
 
 static int32_t EncodeLoadImmediate(int32_t dest, int32_t instr) {
   return ((instr & ~kBranchOffsetMask) | (dest & kBranchOffsetMask));
 }
 
 
 class PatchFarJump : public AssemblerFixup {
  public:
   PatchFarJump() {}
 
   void Process(const MemoryRegion& region, intptr_t position) {
     const int32_t high = region.Load<int32_t>(position);
     const int32_t low = region.Load<int32_t>(position + Instr::kInstrSize);
     const int32_t offset = DecodeLoadImmediate(low, high);
     const int32_t dest = region.start() + offset;
 
     if ((Instr::At(reinterpret_cast<uword>(&high))->OpcodeField() == LUI) &&
         (Instr::At(reinterpret_cast<uword>(&low))->OpcodeField() == ORI)) {
       // Change the offset to the absolute value.
       const int32_t encoded_low =
           EncodeLoadImmediate(dest & kBranchOffsetMask, low);
-      const int32_t encoded_high =
-          EncodeLoadImmediate(dest >> 16, high);
+      const int32_t encoded_high = EncodeLoadImmediate(dest >> 16, high);
 
       region.Store<int32_t>(position, encoded_high);
       region.Store<int32_t>(position + Instr::kInstrSize, encoded_low);
       return;
     }
     // If the offset loading instructions aren't there, we must have replaced
     // the far branch with a near one, and so these instructions should be NOPs.
     ASSERT((high == Instr::kNopInstruction) && (low == Instr::kNopInstruction));
   }
 
@@ skipping 12 matching lines @@
   if (link) {
     EmitRType(SPECIAL, T9, R0, RA, 0, JALR);
   } else {
     EmitRType(SPECIAL, T9, R0, R0, 0, JR);
   }
 }
 
 
 static Opcode OppositeBranchOpcode(Opcode b) {
   switch (b) {
-    case BEQ: return BNE;
-    case BNE: return BEQ;
-    case BGTZ: return BLEZ;
-    case BLEZ: return BGTZ;
-    case BEQL: return BNEL;
-    case BNEL: return BEQL;
-    case BGTZL: return BLEZL;
-    case BLEZL: return BGTZL;
+    case BEQ:
+      return BNE;
+    case BNE:
+      return BEQ;
+    case BGTZ:
+      return BLEZ;
+    case BLEZ:
+      return BGTZ;
+    case BEQL:
+      return BNEL;
+    case BNEL:
+      return BEQL;
+    case BGTZL:
+      return BLEZL;
+    case BLEZL:
+      return BGTZL;
     default:
       UNREACHABLE();
       break;
   }
   return BNE;
 }
 
 
-void Assembler::EmitFarBranch(Opcode b, Register rs, Register rt,
+void Assembler::EmitFarBranch(Opcode b,
+                              Register rs,
+                              Register rt,
                               int32_t offset) {
   ASSERT(!in_delay_slot_);
   EmitIType(b, rs, rt, 4);
   nop();
   EmitFarJump(offset, false);
 }
 
 
 static RtRegImm OppositeBranchNoLink(RtRegImm b) {
   switch (b) {
-    case BLTZ: return BGEZ;
-    case BGEZ: return BLTZ;
-    case BLTZAL: return BGEZ;
-    case BGEZAL: return BLTZ;
+    case BLTZ:
+      return BGEZ;
+    case BGEZ:
+      return BLTZ;
+    case BLTZAL:
+      return BGEZ;
+    case BGEZAL:
+      return BLTZ;
     default:
       UNREACHABLE();
       break;
   }
   return BLTZ;
 }
 
 
 void Assembler::EmitFarRegImmBranch(RtRegImm b, Register rs, int32_t offset) {
   ASSERT(!in_delay_slot_);
@@ skipping 57 matching lines @@
       EmitFarRegImmBranch(b, rs, dest_off);
     } else {
       const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
       EmitRegImmType(REGIMM, rs, b, dest_off);
     }
     label->LinkTo(position);
   }
 }
 
 
-void Assembler::EmitFpuBranch(bool kind, Label *label) {
+void Assembler::EmitFpuBranch(bool kind, Label* label) {
   ASSERT(!in_delay_slot_);
   const int32_t b16 = kind ? (1 << 16) : 0;  // Bit 16 set for branch on true.
   if (label->IsBound()) {
     // Relative destination from an instruction after the branch.
     const int32_t dest =
         label->Position() - (buffer_.Size() + Instr::kInstrSize);
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       EmitFarFpuBranch(kind, label->Position());
     } else {
       const uint16_t dest_off = EncodeBranchOffset(dest, 0);
-      Emit(COP1 << kOpcodeShift |
-           COP1_BC << kCop1SubShift |
-           b16 |
-           dest_off);
+      Emit(COP1 << kOpcodeShift | COP1_BC << kCop1SubShift | b16 | dest_off);
     }
   } else {
     const intptr_t position = buffer_.Size();
     if (use_far_branches()) {
       const uint32_t dest_off = label->position_;
       EmitFarFpuBranch(kind, dest_off);
     } else {
       const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
-      Emit(COP1 << kOpcodeShift |
-           COP1_BC << kCop1SubShift |
-           b16 |
-           dest_off);
+      Emit(COP1 << kOpcodeShift | COP1_BC << kCop1SubShift | b16 | dest_off);
     }
     label->LinkTo(position);
   }
 }
 
 
 static int32_t FlipBranchInstruction(int32_t instr) {
   Instr* i = Instr::At(reinterpret_cast<uword>(&instr));
   if (i->OpcodeField() == REGIMM) {
     RtRegImm b = OppositeBranchNoLink(i->RegImmFnField());
@@ skipping 25 matching lines @@
       // Grab instructions that load the offset.
       const int32_t high =
           buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
       const int32_t low =
           buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
 
       // Change from relative to the branch to relative to the assembler buffer.
       dest = buffer_.Size();
       const int32_t encoded_low =
           EncodeLoadImmediate(dest & kBranchOffsetMask, low);
-      const int32_t encoded_high =
-          EncodeLoadImmediate(dest >> 16, high);
+      const int32_t encoded_high = EncodeLoadImmediate(dest >> 16, high);
 
       // Skip the unconditional far jump if the test fails by flipping the
       // sense of the branch instruction.
       buffer_.Store<int32_t>(position, FlipBranchInstruction(branch));
       buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize, encoded_high);
       buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize, encoded_low);
       label->position_ = DecodeLoadImmediate(low, high);
     } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
       // We assembled a far branch, but we don't need it. Replace with a near
       // branch.
 
       // Grab the link to the next branch.
       const int32_t high =
           buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
       const int32_t low =
           buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
 
       // Grab the original branch instruction.
       int32_t branch = buffer_.Load<int32_t>(position);
 
       // Clear out the old (far) branch.
       for (int i = 0; i < 5; i++) {
         buffer_.Store<int32_t>(position + i * Instr::kInstrSize,
-            Instr::kNopInstruction);
+                               Instr::kNopInstruction);
       }
 
       // Calculate the new offset.
       dest = dest - 4 * Instr::kInstrSize;
       const int32_t encoded = EncodeBranchOffset(dest, branch);
       buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize, encoded);
       label->position_ = DecodeLoadImmediate(low, high);
     } else {
       const int32_t next = buffer_.Load<int32_t>(position);
       const int32_t encoded = EncodeBranchOffset(dest, next);
@@ skipping 22 matching lines @@
       lui(rd, Immediate(offset_high));
       addu(rd, rd, pp);
       lw(rd, Address(rd, offset_low));
     } else {
       lw(rd, Address(pp, offset_low));
     }
   }
 }
 
 
-void Assembler::AdduDetectOverflow(Register rd, Register rs, Register rt,
-                                   Register ro, Register scratch) {
+void Assembler::AdduDetectOverflow(Register rd,
+                                   Register rs,
+                                   Register rt,
+                                   Register ro,
+                                   Register scratch) {
   ASSERT(!in_delay_slot_);
   ASSERT(rd != ro);
   ASSERT(rd != TMP);
   ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
 
   if ((rs == rt) && (rd == rs)) {
     ASSERT(scratch != kNoRegister);
     ASSERT(scratch != TMP);
     ASSERT(rd != scratch);
     ASSERT(ro != scratch);
     ASSERT(rs != scratch);
     ASSERT(rt != scratch);
     mov(scratch, rt);
     rt = scratch;
   }
 
   if (rd == rs) {
-    mov(TMP, rs);  // Preserve rs.
-    addu(rd, rs, rt);  // rs is overwritten.
+    mov(TMP, rs);        // Preserve rs.
+    addu(rd, rs, rt);    // rs is overwritten.
     xor_(TMP, rd, TMP);  // Original rs.
     xor_(ro, rd, rt);
     and_(ro, ro, TMP);
   } else if (rd == rt) {
-    mov(TMP, rt);  // Preserve rt.
-    addu(rd, rs, rt);  // rt is overwritten.
+    mov(TMP, rt);        // Preserve rt.
+    addu(rd, rs, rt);    // rt is overwritten.
     xor_(TMP, rd, TMP);  // Original rt.
     xor_(ro, rd, rs);
     and_(ro, ro, TMP);
   } else {
     addu(rd, rs, rt);
     xor_(ro, rd, rs);
     xor_(TMP, rd, rt);
     and_(ro, TMP, ro);
   }
 }
 
 
-void Assembler::SubuDetectOverflow(Register rd, Register rs, Register rt,
+void Assembler::SubuDetectOverflow(Register rd,
+                                   Register rs,
+                                   Register rt,
                                    Register ro) {
   ASSERT(!in_delay_slot_);
   ASSERT(rd != ro);
   ASSERT(rd != TMP);
   ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
   ASSERT(rs != TMP);
   ASSERT(rt != TMP);
 
   // This happens with some crankshaft code. Since Subu works fine if
   // left == right, let's not make that restriction here.
   if (rs == rt) {
     mov(rd, ZR);
     mov(ro, ZR);
     return;
   }
 
   if (rd == rs) {
-    mov(TMP, rs);  // Preserve left.
-    subu(rd, rs, rt);  // Left is overwritten.
-    xor_(ro, rd, TMP);  // scratch is original left.
+    mov(TMP, rs);        // Preserve left.
+    subu(rd, rs, rt);    // Left is overwritten.
+    xor_(ro, rd, TMP);   // scratch is original left.
     xor_(TMP, TMP, rs);  // scratch is original left.
     and_(ro, TMP, ro);
   } else if (rd == rt) {
-    mov(TMP, rt);  // Preserve right.
+    mov(TMP, rt);      // Preserve right.
     subu(rd, rs, rt);  // Right is overwritten.
     xor_(ro, rd, rs);
     xor_(TMP, rs, TMP);  // Original right.
     and_(ro, TMP, ro);
   } else {
     subu(rd, rs, rt);
     xor_(ro, rd, rs);
     xor_(TMP, rs, rt);
     and_(ro, TMP, ro);
   }
 }
 
 
 void Assembler::CheckCodePointer() {
 #ifdef DEBUG
   if (!FLAG_check_code_pointer) {
     return;
   }
   Comment("CheckCodePointer");
   Label cid_ok, instructions_ok;
   Push(CMPRES1);
   Push(CMPRES2);
   LoadClassId(CMPRES1, CODE_REG);
   BranchEqual(CMPRES1, Immediate(kCodeCid), &cid_ok);
   break_(0);
   Bind(&cid_ok);
   GetNextPC(CMPRES1, TMP);
   const intptr_t entry_offset = CodeSize() - Instr::kInstrSize +
-      Instructions::HeaderSize() - kHeapObjectTag;
+                                Instructions::HeaderSize() - kHeapObjectTag;
   AddImmediate(CMPRES1, CMPRES1, -entry_offset);
   lw(CMPRES2, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
   BranchEqual(CMPRES1, CMPRES2, &instructions_ok);
   break_(1);
   Bind(&instructions_ok);
   Pop(CMPRES2);
   Pop(CMPRES1);
 #endif
 }
 
@@ skipping 217 matching lines @@
   }
   Bind(&done);
 }
 
 
 void Assembler::StoreIntoObjectOffset(Register object,
                                       int32_t offset,
                                       Register value,
                                       bool can_value_be_smi) {
   if (Address::CanHoldOffset(offset - kHeapObjectTag)) {
-    StoreIntoObject(
-        object, FieldAddress(object, offset), value, can_value_be_smi);
+    StoreIntoObject(object, FieldAddress(object, offset), value,
+                    can_value_be_smi);
   } else {
     AddImmediate(TMP, object, offset - kHeapObjectTag);
     StoreIntoObject(object, Address(TMP), value, can_value_be_smi);
   }
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          Register value) {
@@ skipping 48 matching lines @@
 
 
 void Assembler::LoadIsolate(Register result) {
   lw(result, Address(THR, Thread::isolate_offset()));
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
   lhu(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(!in_delay_slot_);
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
@@ skipping 93 matching lines @@
 void Assembler::MaybeTraceAllocation(intptr_t cid,
                                      Register temp_reg,
                                      Label* trace) {
   ASSERT(cid > 0);
   ASSERT(!in_delay_slot_);
   ASSERT(temp_reg != kNoRegister);
   ASSERT(temp_reg != TMP);
   intptr_t state_offset = ClassTable::StateOffsetFor(cid);
   LoadIsolate(temp_reg);
   intptr_t table_offset =
-    Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
+      Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   lw(temp_reg, Address(temp_reg, table_offset));
   AddImmediate(temp_reg, state_offset);
   lw(temp_reg, Address(temp_reg, 0));
   andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask()));
   bne(CMPRES1, ZR, trace);
 }
 
 
 void Assembler::UpdateAllocationStats(intptr_t cid,
                                       Register temp_reg,
@@ skipping 17 matching lines @@
 
 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
                                               Register size_reg,
                                               Register temp_reg,
                                               Heap::Space space) {
   ASSERT(!in_delay_slot_);
   ASSERT(temp_reg != kNoRegister);
   ASSERT(cid > 0);
   ASSERT(temp_reg != TMP);
   const uword class_offset = ClassTable::ClassOffsetFor(cid);
-  const uword count_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_since_gc_old_space_offset();
-  const uword size_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_size_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_size_since_gc_old_space_offset();
+  const uword count_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_since_gc_old_space_offset();
+  const uword size_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_size_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_size_since_gc_old_space_offset();
   LoadIsolate(temp_reg);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   lw(temp_reg, Address(temp_reg, table_offset));
   AddImmediate(temp_reg, class_offset);
   lw(TMP, Address(temp_reg, count_field_offset));
   AddImmediate(TMP, 1);
   sw(TMP, Address(temp_reg, count_field_offset));
   lw(TMP, Address(temp_reg, size_field_offset));
   addu(TMP, TMP, size_reg);
@@ skipping 177 matching lines @@
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
     LoadImmediate(TMP, ~(OS::ActivationFrameAlignment() - 1));
     and_(SP, SP, TMP);
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   ASSERT(!in_delay_slot_);
-  const intptr_t kPushedRegistersSize =
-      kDartVolatileCpuRegCount * kWordSize +
-      3 * kWordSize +  // PP, FP and RA.
-      kDartVolatileFpuRegCount * kWordSize;
+  const intptr_t kPushedRegistersSize = kDartVolatileCpuRegCount * kWordSize +
+                                        3 * kWordSize +  // PP, FP and RA.
+                                        kDartVolatileFpuRegCount * kWordSize;
 
   SetPrologueOffset();
 
   Comment("EnterCallRuntimeFrame");
 
   // Save volatile CPU and FPU registers on the stack:
   // -------------
   // FPU Registers
   // CPU Registers
   // RA
@@ skipping 22 matching lines @@
   LoadPoolPointer();
 
   mov(FP, SP);
 
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
   ASSERT(!in_delay_slot_);
-  const intptr_t kPushedRegistersSize =
-      kDartVolatileCpuRegCount * kWordSize +
-      3 * kWordSize +  // FP and RA.
-      kDartVolatileFpuRegCount * kWordSize;
+  const intptr_t kPushedRegistersSize = kDartVolatileCpuRegCount * kWordSize +
+                                        3 * kWordSize +  // FP and RA.
+                                        kDartVolatileFpuRegCount * kWordSize;
 
   Comment("LeaveCallRuntimeFrame");
 
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
   mov(SP, FP);
 
   // Restore volatile CPU and FPU registers from the stack.
   lw(PP, Address(SP, 0 * kWordSize));
@@ skipping 14 matching lines @@
   }
   addiu(SP, SP, Immediate(kPushedRegistersSize));
 }
 
 
 Address Assembler::ElementAddressForIntIndex(bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index) const {
-  const int64_t offset = index * index_scale +
+  const int64_t offset =
+      index * index_scale +
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
   ASSERT(Utils::IsInt(32, offset));
   ASSERT(Address::CanHoldOffset(offset));
   return Address(array, static_cast<int32_t>(offset));
 }
 
 
 void Assembler::LoadElementAddressForIntIndex(Register address,
                                               bool is_external,
                                               intptr_t cid,
                                               intptr_t index_scale,
                                               Register array,
                                               intptr_t index) {
-  const int64_t offset = index * index_scale +
+  const int64_t offset =
+      index * index_scale +
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
   AddImmediate(address, array, offset);
 }
 
 
 Address Assembler::ElementAddressForRegIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
@@ skipping 100 matching lines @@
   srl(tmp, src, 8);
   sb(tmp, Address(addr, 1));
   srl(tmp, src, 16);
   sb(tmp, Address(addr, 2));
   srl(tmp, src, 24);
   sb(tmp, Address(addr, 3));
 }
 
 
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
-  "zr", "tmp", "v0", "v1", "a0", "a1", "a2", "a3",
-  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
-  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
+    "zr", "tmp", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2",
+    "t3", "t4",  "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5",
+    "s6", "s7",  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
 };
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
-  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+    "d0", "d1", "d2",  "d3",  "d4",  "d5",  "d6",  "d7",
+    "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 
 void Assembler::Stop(const char* message) {
   if (FLAG_print_stop_message) {
     UNIMPLEMENTED();
   }
   Label stop;
   b(&stop);
   Emit(reinterpret_cast<int32_t>(message));
   Bind(&stop);
   break_(Instr::kStopMessageCode);
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS