clang-format runtime/vm

runtime/vm/assembler_ia32.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_IA32)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/cpu.h"
@@ skipping 17 matching lines @@
     int32_t delta = region.start() + position + sizeof(int32_t);
     region.Store<int32_t>(position, pointer - delta);
   }
 
   virtual bool IsPointerOffset() const { return false; }
 };
 
 
 int32_t Assembler::jit_cookie() {
   if (jit_cookie_ == 0) {
-    jit_cookie_ = static_cast<int32_t>(
-        Isolate::Current()->random()->NextUInt32());
+    jit_cookie_ =
+        static_cast<int32_t>(Isolate::Current()->random()->NextUInt32());
   }
   return jit_cookie_;
 }
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
   memset(reinterpret_cast<void*>(data), Instr::kBreakPointInstruction, length);
 }
 
 
@@ skipping 609 matching lines @@
   EmitXmmRegisterOperand(dst, src);
 }
 
 
 void Assembler::notps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
-  } float_not_constant =
-      { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
-  xorps(dst,
-    Address::Absolute(reinterpret_cast<uword>(&float_not_constant)));
+  } float_not_constant = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
+  xorps(dst, Address::Absolute(reinterpret_cast<uword>(&float_not_constant)));
 }
 
 
 void Assembler::negateps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
-  } float_negate_constant =
-      { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
+  } float_negate_constant = {0x80000000, 0x80000000, 0x80000000, 0x80000000};
   xorps(dst,
         Address::Absolute(reinterpret_cast<uword>(&float_negate_constant)));
 }
 
 
 void Assembler::absps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
-  } float_absolute_constant =
-      { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
+  } float_absolute_constant = {0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF};
   andps(dst,
         Address::Absolute(reinterpret_cast<uword>(&float_absolute_constant)));
 }
 
 
 void Assembler::zerowps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
-  } float_zerow_constant =
-      { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 };
+  } float_zerow_constant = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000};
   andps(dst, Address::Absolute(reinterpret_cast<uword>(&float_zerow_constant)));
 }
 
 
 void Assembler::cmppseq(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xC2);
   EmitXmmRegisterOperand(dst, src);
   EmitUint8(0x0);
@@ skipping 145 matching lines @@
   EmitUint8(0x0F);
   EmitUint8(0x58);
   EmitXmmRegisterOperand(dst, src);
 }
 
 
 void Assembler::negatepd(XmmRegister dst) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
-  } double_negate_constant =
-      { 0x8000000000000000LL, 0x8000000000000000LL };
+  } double_negate_constant = {0x8000000000000000LL, 0x8000000000000000LL};
   xorpd(dst,
         Address::Absolute(reinterpret_cast<uword>(&double_negate_constant)));
 }
 
 
 void Assembler::subpd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
   EmitUint8(0x5C);
@@ skipping 16 matching lines @@
   EmitUint8(0x0F);
   EmitUint8(0x5E);
   EmitXmmRegisterOperand(dst, src);
 }
 
 
 void Assembler::abspd(XmmRegister dst) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
-  } double_absolute_constant =
-      { 0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL };
+  } double_absolute_constant = {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
   andpd(dst,
         Address::Absolute(reinterpret_cast<uword>(&double_absolute_constant)));
 }
 
 
 void Assembler::minpd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
   EmitUint8(0x5D);
@@ skipping 1320 matching lines @@
   // For the value we are only interested in the new/old bit and the tag bit.
   andl(value, Immediate(kNewObjectAlignmentOffset | kHeapObjectTag));
   // Shift the tag bit into the carry.
   shrl(value, Immediate(1));
   // Add the tag bits together, if the value is not a Smi the addition will
   // overflow into the next bit, leaving us with a zero low bit.
   adcl(value, object);
   // Mask out higher, uninteresting bits which were polluted by dest.
   andl(value, Immediate(kObjectAlignment - 1));
   // Compare with the expected bit pattern.
-  cmpl(value, Immediate(
-      (kNewObjectAlignmentOffset >> 1) + kHeapObjectTag +
-      kOldObjectAlignmentOffset + kHeapObjectTag));
+  cmpl(value, Immediate((kNewObjectAlignmentOffset >> 1) + kHeapObjectTag +
+                        kOldObjectAlignmentOffset + kHeapObjectTag));
   j(NOT_ZERO, no_update, Assembler::kNearJump);
 }
 
 
 // Destroys the value register.
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
@@ skipping 98 matching lines @@
   addl(ESP, Immediate(2 * kWordSize));
 }
 
 
 void Assembler::FloatNegate(XmmRegister f) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
-  } float_negate_constant =
-      { 0x80000000, 0x00000000, 0x80000000, 0x00000000 };
+  } float_negate_constant = {0x80000000, 0x00000000, 0x80000000, 0x00000000};
   xorps(f, Address::Absolute(reinterpret_cast<uword>(&float_negate_constant)));
 }
 
 
 void Assembler::DoubleNegate(XmmRegister d) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
-  } double_negate_constant =
-      {0x8000000000000000LL, 0x8000000000000000LL};
+  } double_negate_constant = {0x8000000000000000LL, 0x8000000000000000LL};
   xorpd(d, Address::Absolute(reinterpret_cast<uword>(&double_negate_constant)));
 }
 
 
 void Assembler::DoubleAbs(XmmRegister reg) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
-  } double_abs_constant =
-      {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
+  } double_abs_constant = {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
   andpd(reg, Address::Absolute(reinterpret_cast<uword>(&double_abs_constant)));
 }
 
 
 void Assembler::EnterFrame(intptr_t frame_size) {
   if (prologue_offset_ == -1) {
     Comment("PrologueOffset = %" Pd "", CodeSize());
     prologue_offset_ = CodeSize();
   }
 #ifdef DEBUG
@@ skipping 23 matching lines @@
   // the C++ world.
   AddImmediate(ESP, Immediate(-frame_space));
   if (OS::ActivationFrameAlignment() > 1) {
     andl(ESP, Immediate(~(OS::ActivationFrameAlignment() - 1)));
   }
 }
 
 
 static const intptr_t kNumberOfVolatileCpuRegisters = 3;
 static const Register volatile_cpu_registers[kNumberOfVolatileCpuRegisters] = {
-    EAX, ECX, EDX
-};
+    EAX, ECX, EDX};
 
 
 // XMM0 is used only as a scratch register in the optimized code. No need to
 // save it.
-static const intptr_t kNumberOfVolatileXmmRegisters =
-    kNumberOfXmmRegisters - 1;
+static const intptr_t kNumberOfVolatileXmmRegisters = kNumberOfXmmRegisters - 1;
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   Comment("EnterCallRuntimeFrame");
   EnterFrame(0);
 
   // Preserve volatile CPU registers.
   for (intptr_t i = 0; i < kNumberOfVolatileCpuRegisters; i++) {
     pushl(volatile_cpu_registers[i]);
   }
@@ skipping 80 matching lines @@
     return;
   }
   intptr_t bytes_needed = alignment - mod;
   while (bytes_needed > MAX_NOP_SIZE) {
     nop(MAX_NOP_SIZE);
     bytes_needed -= MAX_NOP_SIZE;
   }
   if (bytes_needed) {
     nop(bytes_needed);
   }
-  ASSERT(((offset + buffer_.GetPosition()) & (alignment-1)) == 0);
+  ASSERT(((offset + buffer_.GetPosition()) & (alignment - 1)) == 0);
 }
 
 
 void Assembler::Bind(Label* label) {
   intptr_t bound = buffer_.Size();
   ASSERT(!label->IsBound());  // Labels can only be bound once.
   while (label->IsLinked()) {
     intptr_t position = label->LinkPosition();
     intptr_t next = buffer_.Load<int32_t>(position);
     buffer_.Store<int32_t>(position, bound - (position + 4));
@@ skipping 75 matching lines @@
                             bool near_jump,
                             Register instance_reg,
                             Register temp_reg) {
   ASSERT(failure != NULL);
   ASSERT(temp_reg != kNoRegister);
   if (FLAG_inline_alloc) {
     // If this allocation is traced, program will jump to failure path
     // (i.e. the allocation stub) which will allocate the object and trace the
     // allocation call site.
     NOT_IN_PRODUCT(
-      MaybeTraceAllocation(cls.id(), temp_reg, failure, near_jump));
+        MaybeTraceAllocation(cls.id(), temp_reg, failure, near_jump));
     const intptr_t instance_size = cls.instance_size();
     Heap::Space space = Heap::kNew;
     movl(temp_reg, Address(THR, Thread::heap_offset()));
     movl(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
     addl(instance_reg, Immediate(instance_size));
     // instance_reg: potential next object start.
     cmpl(instance_reg, Address(temp_reg, Heap::EndOffset(space)));
     j(ABOVE_EQUAL, failure, near_jump);
     // Successfully allocated the object, now update top to point to
     // next object start and store the class in the class field of object.
@@ skipping 97 matching lines @@
 void Assembler::EnterStubFrame() {
   EnterDartFrame(0);
 }
 
 
 void Assembler::Stop(const char* message) {
   if (FLAG_print_stop_message) {
     pushl(EAX);  // Preserve EAX.
     movl(EAX, Immediate(reinterpret_cast<int32_t>(message)));
     Call(*StubCode::PrintStopMessage_entry());  // Passing message in EAX.
-    popl(EAX);  // Restore EAX.
+    popl(EAX);                                  // Restore EAX.
   } else {
     // Emit the message address as immediate operand in the test instruction.
     testl(EAX, Immediate(reinterpret_cast<int32_t>(message)));
   }
   // Emit the int3 instruction.
   int3();  // Execution can be resumed with the 'cont' command in gdb.
 }
 
 
 void Assembler::EmitOperand(int rm, const Operand& operand) {
@@ skipping 56 matching lines @@
 
 
 void Assembler::EmitNearLabelLink(Label* label) {
   ASSERT(!label->IsBound());
   intptr_t position = buffer_.Size();
   EmitUint8(0);
   label->NearLinkTo(position);
 }
 
 
-void Assembler::EmitGenericShift(int rm,
-                                 Register reg,
-                                 const Immediate& imm) {
+void Assembler::EmitGenericShift(int rm, Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   ASSERT(imm.is_int8());
   if (imm.value() == 1) {
     EmitUint8(0xD1);
     EmitOperand(rm, Operand(reg));
   } else {
     EmitUint8(0xC1);
     EmitOperand(rm, Operand(reg));
     EmitUint8(imm.value() & 0xFF);
   }
 }
 
 
 void Assembler::EmitGenericShift(int rm,
                                  const Operand& operand,
                                  Register shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   ASSERT(shifter == ECX);
   EmitUint8(0xD3);
   EmitOperand(rm, Operand(operand));
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
   movzxw(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
   movl(result, Address(result, offset));
@@ skipping 16 matching lines @@
 }
 
 
 void Assembler::SmiUntagOrCheckClass(Register object,
                                      intptr_t class_id,
                                      Register scratch,
                                      Label* is_smi) {
   ASSERT(kSmiTagShift == 1);
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
 
   // Untag optimistically. Tag bit is shifted into the CARRY.
   SmiUntag(object);
   j(NOT_CARRY, is_smi, kNearJump);
   // Load cid: can't use LoadClassId, object is untagged. Use TIMES_2 scale
   // factor in the addressing mode to compensate for this.
   movzxw(scratch, Address(object, TIMES_2, class_id_offset));
   cmpl(scratch, Immediate(class_id));
 }
 
@@ skipping 24 matching lines @@
 
 Address Assembler::ElementAddressForIntIndex(bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index) {
   if (is_external) {
     return Address(array, index * index_scale);
   } else {
     const int64_t disp = static_cast<int64_t>(index) * index_scale +
-        Instance::DataOffsetFor(cid);
+                         Instance::DataOffsetFor(cid);
     ASSERT(Utils::IsInt(32, disp));
     return FieldAddress(array, static_cast<int32_t>(disp));
   }
 }
 
 
 static ScaleFactor ToScaleFactor(intptr_t index_scale) {
   // Note that index is expected smi-tagged, (i.e, times 2) for all arrays with
   // index scale factor > 1. E.g., for Uint8Array and OneByteString the index is
   // expected to be untagged before accessing.
   ASSERT(kSmiTagShift == 1);
   switch (index_scale) {
-    case 1: return TIMES_1;
-    case 2: return TIMES_1;
-    case 4: return TIMES_2;
-    case 8: return TIMES_4;
-    case 16: return TIMES_8;
+    case 1:
+      return TIMES_1;
+    case 2:
+      return TIMES_1;
+    case 4:
+      return TIMES_2;
+    case 8:
+      return TIMES_4;
+    case 16:
+      return TIMES_8;
     default:
       UNREACHABLE();
       return TIMES_1;
   }
 }
 
 
 Address Assembler::ElementAddressForRegIndex(bool is_external,
-                                            intptr_t cid,
-                                            intptr_t index_scale,
-                                            Register array,
-                                            Register index) {
+                                             intptr_t cid,
+                                             intptr_t index_scale,
+                                             Register array,
+                                             Register index) {
   if (is_external) {
     return Address(array, index, ToScaleFactor(index_scale), 0);
   } else {
-    return FieldAddress(array,
-                        index,
-                        ToScaleFactor(index_scale),
+    return FieldAddress(array, index, ToScaleFactor(index_scale),
                         Instance::DataOffsetFor(cid));
   }
 }
 
 
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
-  "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
-};
+    "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* xmm_reg_names[kNumberOfXmmRegisters] = {
-  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
-};
+    "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"};
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_IA32