clang-format runtime/vm

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 namespace dart {
 
 DECLARE_FLAG(bool, check_code_pointer);
 DECLARE_FLAG(bool, inline_alloc);
 
 DEFINE_FLAG(bool, use_far_branches, false, "Always use far branches");
 
 
 Assembler::Assembler(bool use_far_branches)
     : buffer_(),
       prologue_offset_(-1),
       has_single_entry_point_(true),
       use_far_branches_(use_far_branches),
       comments_(),
-      constant_pool_allowed_(false) {
-}
+      constant_pool_allowed_(false) {}
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
   ASSERT(Utils::IsAligned(data, 4));
   ASSERT(Utils::IsAligned(length, 4));
   const uword end = data + length;
   while (data < end) {
     *reinterpret_cast<int32_t*>(data) = Instr::kBreakPointInstruction;
     data += 4;
   }
 }
 
 
 void Assembler::Emit(int32_t value) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   buffer_.Emit<int32_t>(value);
 }
 
 
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
-  "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
-  "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
-  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-  "r24", "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "r31",
+    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
+    "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
+    "r22", "r23", "r24", "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "r31",
 };
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
-  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
-  "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
-  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
-  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+    "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
+    "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
+    "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 
 void Assembler::Bind(Label* label) {
@@ skipping 49 matching lines @@
       const int32_t far_branch =
           buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
 
       // Grab the link to the next branch.
       const int32_t next = DecodeImm26BranchOffset(far_branch);
 
       // Re-target the guarding branch and flip the conditional sense.
       int32_t encoded_guard_branch =
           EncodeImm19BranchOffset(dest, guard_branch);
       const Condition c = DecodeImm19BranchCondition(encoded_guard_branch);
-      encoded_guard_branch = EncodeImm19BranchCondition(
-          InvertCondition(c), encoded_guard_branch);
+      encoded_guard_branch =
+          EncodeImm19BranchCondition(InvertCondition(c), encoded_guard_branch);
 
       // Write back the re-encoded instructions. The far branch becomes a nop.
-      buffer_.Store<int32_t>(
-          position + 0 * Instr::kInstrSize, encoded_guard_branch);
-      buffer_.Store<int32_t>(
-          position + 1 * Instr::kInstrSize, Instr::kNopInstruction);
+      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize,
+                             encoded_guard_branch);
+      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
+                             Instr::kNopInstruction);
       label->position_ = next;
     } else {
       const int32_t next = buffer_.Load<int32_t>(position);
       const int32_t encoded = EncodeImm19BranchOffset(dest, next);
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = DecodeImm19BranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
 }
@@ skipping 20 matching lines @@
   int count = 0;
   do {
     count++;
   } while (value >>= 1);
   return width - count;
 }
 
 
 static int CountOneBits(uint64_t value, int width) {
   // Mask out unused bits to ensure that they are not counted.
-  value &= (0xffffffffffffffffUL >> (64-width));
+  value &= (0xffffffffffffffffUL >> (64 - width));
 
   value = ((value >> 1) & 0x5555555555555555) + (value & 0x5555555555555555);
   value = ((value >> 2) & 0x3333333333333333) + (value & 0x3333333333333333);
   value = ((value >> 4) & 0x0f0f0f0f0f0f0f0f) + (value & 0x0f0f0f0f0f0f0f0f);
   value = ((value >> 8) & 0x00ff00ff00ff00ff) + (value & 0x00ff00ff00ff00ff);
   value = ((value >> 16) & 0x0000ffff0000ffff) + (value & 0x0000ffff0000ffff);
   value = ((value >> 32) & 0x00000000ffffffff) + (value & 0x00000000ffffffff);
 
   return value;
 }
@@ skipping 177 matching lines @@
     // If the raw smi does not fit into a 32-bit signed int, then we'll keep
     // the raw value in the object pool.
     return !Utils::IsInt(32, reinterpret_cast<int64_t>(object.raw()));
   }
   ASSERT(object.IsNotTemporaryScopedHandle());
   ASSERT(object.IsOld());
   return true;
 }
 
 
-void Assembler::LoadNativeEntry(Register dst,
-                                const ExternalLabel* label) {
+void Assembler::LoadNativeEntry(Register dst, const ExternalLabel* label) {
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindNativeEntry(label, kNotPatchable));
   LoadWordFromPoolOffset(dst, offset);
 }
 
 
 void Assembler::LoadIsolate(Register dst) {
   ldr(dst, Address(THR, Thread::isolate_offset()));
 }
 
@@ skipping 337 matching lines @@
              Operand::Immediate) {
     cmn(rn, op);
   } else {
     ASSERT(rn != TMP2);
     LoadImmediate(TMP2, imm);
     cmp(rn, Operand(TMP2));
   }
 }
 
 
-void Assembler::LoadFromOffset(
-    Register dest, Register base, int32_t offset, OperandSize sz) {
+void Assembler::LoadFromOffset(Register dest,
+                               Register base,
+                               int32_t offset,
+                               OperandSize sz) {
   if (Address::CanHoldOffset(offset, Address::Offset, sz)) {
     ldr(dest, Address(base, offset, Address::Offset, sz), sz);
   } else {
     ASSERT(base != TMP2);
     AddImmediate(TMP2, base, offset);
     ldr(dest, Address(TMP2), sz);
   }
 }
 
 
@@ skipping 12 matching lines @@
   if (Address::CanHoldOffset(offset, Address::Offset, kQWord)) {
     fldrq(dest, Address(base, offset, Address::Offset, kQWord));
   } else {
     ASSERT(base != TMP2);
     AddImmediate(TMP2, base, offset);
     fldrq(dest, Address(TMP2));
   }
 }
 
 
-void Assembler::StoreToOffset(
-    Register src, Register base, int32_t offset, OperandSize sz) {
+void Assembler::StoreToOffset(Register src,
+                              Register base,
+                              int32_t offset,
+                              OperandSize sz) {
   ASSERT(base != TMP2);
   if (Address::CanHoldOffset(offset, Address::Offset, sz)) {
     str(src, Address(base, offset, Address::Offset, sz), sz);
   } else {
     ASSERT(src != TMP2);
     AddImmediate(TMP2, base, offset);
     str(src, Address(TMP2), sz);
   }
 }
 
@@ skipping 35 matching lines @@
 
 
 void Assembler::VRSqrts(VRegister vd, VRegister vn) {
   ASSERT(vd != VTMP);
   ASSERT(vn != VTMP);
 
   // Reciprocal square root estimate.
   vrsqrtes(vd, vn);
   // 2 Newton-Raphson steps. xn+1 = xn * (3 - V1*xn^2) / 2.
   // First step.
-  vmuls(VTMP, vd, vd);  // VTMP <- xn^2
+  vmuls(VTMP, vd, vd);       // VTMP <- xn^2
   vrsqrtss(VTMP, vn, VTMP);  // VTMP <- (3 - V1*VTMP) / 2.
-  vmuls(vd, vd, VTMP);  // xn+1 <- xn * VTMP
+  vmuls(vd, vd, VTMP);       // xn+1 <- xn * VTMP
   // Second step.
   vmuls(VTMP, vd, vd);
   vrsqrtss(VTMP, vn, VTMP);
   vmuls(vd, vd, VTMP);
 }
 
 
-
 // Store into object.
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0));
 
   // Write-barrier triggers if the value is in the new space (has bit set) and
   // the object is in the old space (has bit cleared).
@@ skipping 17 matching lines @@
   tsti(TMP, Immediate(kNewObjectAlignmentOffset));
   b(no_update, EQ);
 }
 
 
 void Assembler::StoreIntoObjectOffset(Register object,
                                       int32_t offset,
                                       Register value,
                                       bool can_value_be_smi) {
   if (Address::CanHoldOffset(offset - kHeapObjectTag)) {
-    StoreIntoObject(
-        object, FieldAddress(object, offset), value, can_value_be_smi);
+    StoreIntoObject(object, FieldAddress(object, offset), value,
+                    can_value_be_smi);
   } else {
     AddImmediate(TMP, object, offset - kHeapObjectTag);
     StoreIntoObject(object, Address(TMP), value, can_value_be_smi);
   }
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
@@ skipping 74 matching lines @@
   } else {
     AddImmediate(TMP, object, offset - kHeapObjectTag);
     StoreIntoObjectNoBarrier(object, Address(TMP), value);
   }
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == kBitsPerInt32);
   ASSERT(RawObject::kClassIdTagSize == kBitsPerInt32);
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
   LoadFromOffset(result, object, class_id_offset - kHeapObjectTag,
                  kUnsignedWord);
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
@@ skipping 292 matching lines @@
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   ldr(temp_reg, Address(temp_reg, table_offset));
   AddImmediate(temp_reg, temp_reg, state_offset);
   ldr(temp_reg, Address(temp_reg, 0));
   tsti(temp_reg, Immediate(ClassHeapStats::TraceAllocationMask()));
   b(trace, NE);
 }
 
 
-void Assembler::UpdateAllocationStats(intptr_t cid,
-                                      Heap::Space space) {
+void Assembler::UpdateAllocationStats(intptr_t cid, Heap::Space space) {
   ASSERT(cid > 0);
   intptr_t counter_offset =
       ClassTable::CounterOffsetFor(cid, space == Heap::kNew);
   LoadIsolate(TMP2);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   ldr(TMP, Address(TMP2, table_offset));
   AddImmediate(TMP2, TMP, counter_offset);
   ldr(TMP, Address(TMP2, 0));
   AddImmediate(TMP, TMP, 1);
   str(TMP, Address(TMP2, 0));
 }
 
 
 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
                                               Register size_reg,
                                               Heap::Space space) {
   ASSERT(cid > 0);
   const uword class_offset = ClassTable::ClassOffsetFor(cid);
-  const uword count_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_since_gc_old_space_offset();
-  const uword size_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_size_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_size_since_gc_old_space_offset();
+  const uword count_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_since_gc_old_space_offset();
+  const uword size_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_size_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_size_since_gc_old_space_offset();
   LoadIsolate(TMP2);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   ldr(TMP, Address(TMP2, table_offset));
   AddImmediate(TMP2, TMP, class_offset);
   ldr(TMP, Address(TMP2, count_field_offset));
   AddImmediate(TMP, TMP, 1);
   str(TMP, Address(TMP2, count_field_offset));
   ldr(TMP, Address(TMP2, size_field_offset));
   add(TMP, TMP, Operand(size_reg));
@@ skipping 23 matching lines @@
     ldr(TMP, Address(temp_reg, Heap::EndOffset(space)));
     CompareRegisters(TMP, instance_reg);
     // fail if heap end unsigned less than or equal to instance_reg.
     b(failure, LS);
 
     // Successfully allocated the object, now update top to point to
     // next object start and store the class in the class field of object.
     str(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
 
     ASSERT(instance_size >= kHeapObjectTag);
-    AddImmediate(
-        instance_reg, instance_reg, -instance_size + kHeapObjectTag);
+    AddImmediate(instance_reg, instance_reg, -instance_size + kHeapObjectTag);
     NOT_IN_PRODUCT(UpdateAllocationStats(cls.id(), space));
 
     uword tags = 0;
     tags = RawObject::SizeTag::update(instance_size, tags);
     ASSERT(cls.id() != kIllegalCid);
     tags = RawObject::ClassIdTag::update(cls.id(), tags);
     LoadImmediate(TMP, tags);
     StoreFieldToOffset(TMP, instance_reg, Object::tags_offset());
   } else {
     b(failure);
@@ skipping 45 matching lines @@
     b(failure);
   }
 }
 
 
 Address Assembler::ElementAddressForIntIndex(bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index) const {
-  const int64_t offset = index * index_scale +
+  const int64_t offset =
+      index * index_scale +
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
   ASSERT(Utils::IsInt(32, offset));
   const OperandSize size = Address::OperandSizeFor(cid);
   ASSERT(Address::CanHoldOffset(offset, Address::Offset, size));
   return Address(array, static_cast<int32_t>(offset), Address::Offset, size);
 }
 
 
 void Assembler::LoadElementAddressForIntIndex(Register address,
                                               bool is_external,
                                               intptr_t cid,
                                               intptr_t index_scale,
                                               Register array,
                                               intptr_t index) {
-  const int64_t offset = index * index_scale +
+  const int64_t offset =
+      index * index_scale +
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
   AddImmediate(address, array, offset);
 }
 
 
 Address Assembler::ElementAddressForRegIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
@@ skipping 37 matching lines @@
     add(address, array, Operand(index, ASR, 1));
   } else {
     add(address, array, Operand(index, LSL, shift));
   }
   if (offset != 0) {
     AddImmediate(address, address, offset);
   }
 }
 
 
-void Assembler::LoadUnaligned(Register dst, Register addr, Register tmp,
+void Assembler::LoadUnaligned(Register dst,
+                              Register addr,
+                              Register tmp,
                               OperandSize sz) {
   ASSERT(dst != addr);
   ldr(dst, Address(addr, 0), kUnsignedByte);
   if (sz == kHalfword) {
     ldr(tmp, Address(addr, 1), kByte);
     orr(dst, dst, Operand(tmp, LSL, 8));
     return;
   }
   ldr(tmp, Address(addr, 1), kUnsignedByte);
   orr(dst, dst, Operand(tmp, LSL, 8));
@@ skipping 20 matching lines @@
   orr(dst, dst, Operand(tmp, LSL, 48));
   ldr(tmp, Address(addr, 7), kUnsignedByte);
   orr(dst, dst, Operand(tmp, LSL, 56));
   if (sz == kDoubleWord) {
     return;
   }
   UNIMPLEMENTED();
 }
 
 
-void Assembler::StoreUnaligned(Register src, Register addr, Register tmp,
+void Assembler::StoreUnaligned(Register src,
+                               Register addr,
+                               Register tmp,
                                OperandSize sz) {
   str(src, Address(addr, 0), kUnsignedByte);
   LsrImmediate(tmp, src, 8);
   str(tmp, Address(addr, 1), kUnsignedByte);
   if ((sz == kHalfword) || (sz == kUnsignedHalfword)) {
     return;
   }
   LsrImmediate(tmp, src, 16);
   str(tmp, Address(addr, 2), kUnsignedByte);
   LsrImmediate(tmp, src, 24);
@@ skipping 11 matching lines @@
   str(tmp, Address(addr, 7), kUnsignedByte);
   if (sz == kDoubleWord) {
     return;
   }
   UNIMPLEMENTED();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64