Thumb2 Backend: Make arithmetic instructions set condition codes by default

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 910 matching lines @@
 }
 
 
 // Low-level code emission routines depending on the addressing mode.
 // If this returns true then you have to use the rotate_imm and immed_8
 // that it returns, because it may have already changed the instruction
 // to match them!
 static bool fits_shifter(uint32_t imm32,
                          uint32_t* rotate_imm,
                          uint32_t* immed_8,
+                         SBitMode* smode,
                          Instr* instr) {
   // imm32 must be unsigned.
   for (int rot = 0; rot < 16; rot++) {
     uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));
     if ((imm8 <= 0xff)) {
       *rotate_imm = rot;
       *immed_8 = imm8;
       return true;
     }
   }
   // If the opcode is one with a complementary version and the complementary
   // immediate fits, change the opcode.
   if (instr != NULL) {
     if ((*instr & kMovMvnMask) == kMovMvnPattern) {
-      if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
+      if (fits_shifter(~imm32, rotate_imm, immed_8, smode, NULL)) {
         *instr ^= kMovMvnFlip;
         return true;
-      } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) {
-        if (CpuFeatures::IsSupported(ARMv7)) {
-          if (imm32 < 0x10000) {
-            *instr ^= kMovwLeaveCCFlip;
-            *instr |= EncodeMovwImmediate(imm32);
-            *rotate_imm = *immed_8 = 0;  // Not used for movw.
-            return true;
-          }
-        }
+      } else if (CpuFeatures::IsSupported(ARMv7) &&
+                 *smode != SetCC &&
+                 imm32 < 0x10000) {
+        *smode = LeaveCC;   // might have been DontCareCC
+        *instr ^= kMovwLeaveCCFlip;
+        *instr |= EncodeMovwImmediate(imm32);
+        *rotate_imm = *immed_8 = 0;  // Not used for movw.
+        return true;
       }
     } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) {
-      if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) {
+      if (fits_shifter(-static_cast<int>(imm32), rotate_imm,
+                       immed_8, NULL, NULL)) {
         *instr ^= kCmpCmnFlip;
         return true;
       }
     } else {
       Instr alu_insn = (*instr & kALUMask);
       if (alu_insn == ADD ||
           alu_insn == SUB) {
-        if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) {
+        if (fits_shifter(-static_cast<int>(imm32), rotate_imm,
+                         immed_8, smode, NULL)) {
           *instr ^= kAddSubFlip;
           return true;
         }
       } else if (alu_insn == AND ||
                  alu_insn == BIC) {
-        if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
+        if (fits_shifter(~imm32, rotate_imm, immed_8, smode, NULL)) {
           *instr ^= kAndBicFlip;
           return true;
         }
       }
     }
   }
   return false;
 }
 
 
@@ skipping 25 matching lines @@
     return false;
   }
   return CpuFeatures::IsSupported(ARMv7);
 }
 
 
 bool Operand::is_single_instruction(const Assembler* assembler,
                                     Instr instr) const {
   if (rm_.is_valid()) return true;
   uint32_t dummy1, dummy2;
+  SBitMode smode = (instr & S) != 0 ? SetCC : LeaveCC;
   if (must_output_reloc_info(assembler) ||
-      !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) {
+      !fits_shifter(imm32_, &dummy1, &dummy2, &smode, &instr)) {
     // The immediate operand cannot be encoded as a shifter operand, or use of
     // constant pool is required. For a mov instruction not setting the
     // condition code additional instruction conventions can be used.
     if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set
       return !use_movw_movt(*this, assembler);
     } else {
       // If this is not a mov or mvn instruction there will always an additional
       // instructions - either mov or ldr. The mov might actually be two
       // instructions mov or movw followed by movt so including the actual
       // instruction two or three instructions will be generated.
       return false;
     }
   } else {
     // No use of constant pool and the immediate operand can be encoded as a
     // shifter operand.
     return true;
   }
 }
 
 
 void Assembler::move_32_bit_immediate_thumb(Register rd,
-                                            SBit s,
+                                            SBitMode smode,
                                             const Operand& x,
                                             Condition cond) {
-  if (rd.code() != pc.code() && s == LeaveCC) {
+  if (rd.code() != pc.code() && smode != SetCC) {
     if (use_movw_movt(x, this)) {
       if (x.must_output_reloc_info(this)) {
         RecordRelocInfo(x.rmode_, x.imm32_, DONT_USE_CONSTANT_POOL);
         // Make sure the movw/movt doesn't get separated.
         BlockConstPoolFor(2);
       }
       if (cond != al) {
         pc_ -= kInstr16Size;
         it_thumb(cond, 2, true);
       }
       emit32(thumb32_mode3(MOV_32_IMM3) |
              thumb32_1reg_zero_extend_imm_split_4i38(rd, (x.imm32_ &  0xffff)));
       movt_thumb(rd, static_cast<uint32_t>(x.imm32_) >> 16, al);
       return;
     }
   }
   RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL);
   ldr_thumb(rd, MemOperand(pc, 0));
 }
 
 
 void Assembler::move_32_bit_immediate(Condition cond,
                                       Register rd,
-                                      SBit s,
                                       const Operand& x) {
-  if (rd.code() != pc.code() && s == LeaveCC) {
+  if (rd.code() != pc.code()) {
     if (use_movw_movt(x, this)) {
       if (x.must_output_reloc_info(this)) {
         RecordRelocInfo(x.rmode_, x.imm32_, DONT_USE_CONSTANT_POOL);
         // Make sure the movw/movt doesn't get separated.
         BlockConstPoolFor(2);
       }
       emit(cond | 0x30*B20 | rd.code()*B12 |
            EncodeMovwImmediate(x.imm32_ & 0xffff));
       movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond);
       return;
     }
   }
 
   RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL);
   ldr(rd, MemOperand(pc, 0), cond);
 }
 
 
 void Assembler::addrmod1(Instr instr,
+                         SBitMode smode,
                          Register rn,
                          Register rd,
                          const Operand& x) {
   CheckBuffer();
-  ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0);
+  ASSERT((instr & ~(kCondMask | kOpCodeMask)) == 0);
   if (!x.rm_.is_valid()) {
     // Immediate.
     uint32_t rotate_imm;
     uint32_t immed_8;
-    if (x.must_output_reloc_info(this) ||
-        !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
-      // The immediate operand cannot be encoded as a shifter operand, so load
-      // it first to register ip and change the original instruction to use ip.
-      // However, if the original instruction is a 'mov rd, x' (not setting the
-      // condition code), then replace it with a 'ldr rd, [pc]'.
-      CHECK(!rn.is(ip));  // rn should never be ip, or will be trashed
+    if (!x.must_output_reloc_info(this) &&
+        fits_shifter(x.imm32_, &rotate_imm, &immed_8, &smode, &instr)) {
+      // The immediate operand can be encoded directly in the shifter.
+      instr |= I | rotate_imm * B8 | immed_8;
+    } else {
+      // The immediate operand cannot be encoded as a shifter operand. We will
+      // need to generate extra instructions.
+      CHECK(!rn.is(ip));
       Condition cond = Instruction::ConditionField(instr);
-      if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set
-        move_32_bit_immediate(cond, rd, LeaveCC, x);
+      if ((instr & kMovMvnMask) == kMovMvnPattern && smode != SetCC) {
+        // If this is a move that doesn't set flags, we can just load directly
+        // into rd using movw/movt or a load from the constant pool.
+        move_32_bit_immediate(cond, rd, x);
+        return;
       } else {
-        if ((instr & kMovMvnMask) == kMovMvnPattern) {
-          // Moves need to use a constant pool entry.
-          RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL);
-          ldr(ip, MemOperand(pc, 0), cond);
-        } else if (x.must_output_reloc_info(this)) {
-          // Otherwise, use most efficient form of fetching from constant pool.
-          move_32_bit_immediate(cond, ip, LeaveCC, x);
-        } else {
-          // If this is not a mov or mvn instruction we may still be able to
-          // avoid a constant pool entry by using mvn or movw.
-          mov(ip, x, LeaveCC, cond);
-        }
-        addrmod1(instr, rn, rd, Operand(ip));
+        // Otherwise, we move the value into ip. This could be encoded as
+        // mvn, movw/movt, or a constant pool load: whatever is most efficient.
+        SBitMode mov_smode = smode == LeaveCC ? LeaveCC : DontCareCC;
+        mov(ip, x, mov_smode, cond);
+        addrmod1(instr, smode, rn, rd, Operand(ip));
+        return;
       }
-      return;
     }
-    instr |= I | rotate_imm*B8 | immed_8;
   } else if (!x.rs_.is_valid()) {
     // Immediate shift.
     instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
   } else {
     // Register shift.
     ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
     instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
   }
-  emit(instr | rn.code()*B16 | rd.code()*B12);
+  SBit s = sbit_from_mode(smode);
+  emit(instr | s | rn.code()*B16 | rd.code()*B12);
   if (rn.is(pc) || x.rm_.is(pc)) {
     // Block constant pool emission for one instruction after reading pc.
     BlockConstPoolFor(1);
   }
 }
 
 
 void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
   ASSERT((instr & ~(kCondMask | B | L)) == B26);
   int am = x.am_;
@@ skipping 209 matching lines @@
     emit16(thumb16_mode3(BX_REG) | thumb16_anyreg_encoding(target));
     return;
   }
   emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code());
 }
 
 
 // Data-processing instructions.
 
 void Assembler::and_(Register dst, Register src1, const Operand& src2,
-                     SBit s, Condition cond) {
+                     SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    and_thumb(dst, src1, src2, s, cond);
+    and_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | AND | s, src1, dst, src2);
+  addrmod1(cond | AND, smode, src1, dst, src2);
 }
 
 
 void Assembler::eor(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    eor_thumb(dst, src1, src2, s, cond);
+    eor_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | EOR | s, src1, dst, src2);
+  addrmod1(cond | EOR, smode, src1, dst, src2);
 }
 
 
 void Assembler::sub(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    sub_thumb(dst, src1, src2, s, cond);
+    sub_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | SUB | s, src1, dst, src2);
+  addrmod1(cond | SUB, smode, src1, dst, src2);
 }
 
 
 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    rsb_thumb(dst, src1, src2, s, cond);
+    rsb_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | RSB | s, src1, dst, src2);
+  addrmod1(cond | RSB, smode, src1, dst, src2);
 }
 
 
 void Assembler::add(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    add_thumb(dst, src1, src2, s, cond);
+    add_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | ADD | s, src1, dst, src2);
+  addrmod1(cond | ADD, smode, src1, dst, src2);
 }
 
 
 void Assembler::adc(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    adc_thumb(dst, src1, src2, s, cond);
+    adc_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | ADC | s, src1, dst, src2);
+  addrmod1(cond | ADC, smode, src1, dst, src2);
 }
 
 
 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    sbc_thumb(dst, src1, src2, s, cond);
+    sbc_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | SBC | s, src1, dst, src2);
+  addrmod1(cond | SBC, smode, src1, dst, src2);
 }
 
 
 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
-  addrmod1(cond | RSC | s, src1, dst, src2);
+                    SBitMode smode, Condition cond) {
+  addrmod1(cond | RSC, smode, src1, dst, src2);
 }
 
 
 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
   if (is_thumb_mode()) {
     tst_thumb(src1, src2, cond);
     return;
   }
-  addrmod1(cond | TST | S, src1, r0, src2);
+  addrmod1(cond | TST, SetCC, src1, r0, src2);
 }
 
 
 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
   if (is_thumb_mode()) {
     teq_thumb(src1, src2, cond);
     return;
   }
-  addrmod1(cond | TEQ | S, src1, r0, src2);
+  addrmod1(cond | TEQ, SetCC, src1, r0, src2);
 }
 
 
 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
   if (is_thumb_mode()) {
     cmp_thumb(src1, src2, cond);
     return;
   }
-  addrmod1(cond | CMP | S, src1, r0, src2);
+  addrmod1(cond | CMP, SetCC, src1, r0, src2);
 }
 
 
 void Assembler::cmp_raw_immediate(
     Register src, int raw_immediate, Condition cond) {
   ASSERT(is_uint12(raw_immediate));
   emit(cond | I | CMP | S | src.code() << 16 | raw_immediate);
 }
 
 
 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
   if (is_thumb_mode()) {
     cmn_thumb(src1, src2, cond);
     return;
   }
-  addrmod1(cond | CMN | S, src1, r0, src2);
+  addrmod1(cond | CMN, SetCC, src1, r0, src2);
 }
 
 
 void Assembler::orr(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    orr_thumb(dst, src1, src2, s, cond);
+    orr_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | ORR | s, src1, dst, src2);
+  addrmod1(cond | ORR, smode, src1, dst, src2);
 }
 
 
-void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
+void Assembler::mov(Register dst,
+                    const Operand& src,
+                    SBitMode smode,
+                    Condition cond) {
   if (dst.is(pc)) {
     positions_recorder()->WriteRecordedPositions();
   }
   // Don't allow nop instructions in the form mov rn, rn to be generated using
   // the mov instruction. They must be generated using nop(int/NopMarkerTypes)
   // or MarkCode(int/NopMarkerTypes) pseudo instructions.
-  ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al));
+  ASSERT(!(src.is_reg() && src.rm().is(dst) && smode != SetCC && cond == al));
   if (is_thumb_mode()) {
-    mov_thumb(dst, src, s, cond);
+    mov_thumb(dst, src, smode, cond);
     return;
   }
-  addrmod1(cond | MOV | s, r0, dst, src);
+  if (dst.code() == 15 && smode == DontCareCC) {
+    smode = LeaveCC;
+  }
+  addrmod1(cond | MOV, smode, r0, dst, src);
 }
 
 
 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
   ASSERT(immediate < 0x10000);
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    mov_imm_t3(reg, Operand(immediate), LeaveCCBit, al);
+    return;
+  }
+
   // May use movw if supported, but on unsupported platforms will try to use
   // equivalent rotated immed_8 value and other tricks before falling back to a
   // constant pool load.
   mov(reg, Operand(immediate), LeaveCC, cond);
 }
 
 
 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
   if (is_thumb_mode()) {
     movt_thumb(reg, immediate, cond);
     return;
   }
   emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
 }
 
 
 void Assembler::bic(Register dst, Register src1, const Operand& src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    bic_thumb(dst, src1, src2, s, cond);
+    bic_thumb(dst, src1, src2, smode, cond);
     return;
   }
-  addrmod1(cond | BIC | s, src1, dst, src2);
+  addrmod1(cond | BIC, smode, src1, dst, src2);
 }
 
 
-void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
+void Assembler::mvn(Register dst, const Operand& src,
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    mvn_thumb(dst, src, s, cond);
+    mvn_thumb(dst, src, smode, cond);
     return;
   }
-  addrmod1(cond | MVN | s, r0, dst, src);
+  addrmod1(cond | MVN, smode, r0, dst, src);
 }
 
 
 // Multiply instructions.
 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   if (is_thumb_mode()) {
-    mla_thumb(dst, src1, src2, srcA, s, cond);
+    mla_thumb(dst, src1, src2, srcA, smode, cond);
     return;
   }
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
+  SBit s = sbit_from_mode(smode);
   emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
                     Condition cond) {
   if (is_thumb_mode()) {
     mls_thumb(dst, src1, src2, srcA, cond);
     return;
@@ skipping 11 matching lines @@
     return;
   }
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(IsEnabled(SUDIV));
   emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 |
        src2.code()*B8 | B4 | src1.code());
 }
 
 
 void Assembler::mul(Register dst, Register src1, Register src2,
-                    SBit s, Condition cond) {
+                    SBitMode smode, Condition cond) {
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
   if (is_thumb_mode()) {
-    mul_thumb(dst, src1, src2, s, cond);
+    mul_thumb(dst, src1, src2, smode, cond);
     return;
   }
+  SBit s = sbit_from_mode(smode);
   // dst goes in bits 16-19 for this instruction!
   emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::smlal(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
-                      SBit s,
+                      SBitMode smode,
                       Condition cond) {
   if (is_thumb_mode()) {
-    smlal_thumb(dstL, dstH, src1, src2, s, cond);
+    smlal_thumb(dstL, dstH, src1, src2, smode, cond);
     return;
   }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
+  SBit s = smode == SetCC ? SetCCBit : LeaveCCBit;
   emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::smull(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
-                      SBit s,
+                      SBitMode smode,
                       Condition cond) {
   if (is_thumb_mode()) {
-    smull_thumb(dstL, dstH, src1, src2, s, cond);
+    smull_thumb(dstL, dstH, src1, src2, smode, cond);
     return;
   }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
+  SBit s = smode == SetCC ? SetCCBit : LeaveCCBit;
   emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::umlal(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
-                      SBit s,
+                      SBitMode smode,
                       Condition cond) {
   if (is_thumb_mode()) {
-    umlal_thumb(dstL, dstH, src1, src2, s, cond);
+    umlal_thumb(dstL, dstH, src1, src2, smode, cond);
     return;
   }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
+  SBit s = smode == SetCC ? SetCCBit : LeaveCCBit;
   emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::umull(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
-                      SBit s,
+                      SBitMode smode,
                       Condition cond) {
   if (is_thumb_mode()) {
-    umull_thumb(dstL, dstH, src1, src2, s, cond);
+    umull_thumb(dstL, dstH, src1, src2, smode, cond);
     return;
   }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
+  SBit s = smode == SetCC ? SetCCBit : LeaveCCBit;
   emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 // Miscellaneous arithmetic instructions.
 void Assembler::clz(Register dst, Register src, Condition cond) {
   // v5 and above.
   ASSERT(!dst.is(pc) && !src.is(pc));
 
@@ skipping 256 matching lines @@
 
 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
                     Condition cond) {
   ASSERT(fields >= B16 && fields < B20);  // at least one field set
   Instr instr;
   if (!src.rm_.is_valid()) {
     // Immediate.
     uint32_t rotate_imm;
     uint32_t immed_8;
     if (src.must_output_reloc_info(this) ||
-        !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
+        !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL, NULL)) {
       // Immediate operand cannot be encoded, load it first to register ip.
       RecordRelocInfo(src.rmode_, src.imm32_);
       ldr(ip, MemOperand(pc, 0), cond);
       msr(fields, Operand(ip), cond);
       return;
     }
     instr = I | rotate_imm*B8 | immed_8;
   } else {
     ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0);  // only rm allowed
     instr = src.rm_.code();
@@ skipping 1333 matching lines @@
 bool Assembler::IsNop(Instr instr, int type) {
   ASSERT(0 <= type && type <= 14);  // mov pc, pc isn't a nop.
   // Check for mov rx, rx where x = type.
   return instr == (al | 13*B21 | type*B12 | type);
 }
 
 
 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
   uint32_t dummy1;
   uint32_t dummy2;
-  return fits_shifter(imm32, &dummy1, &dummy2, NULL);
+  return fits_shifter(imm32, &dummy1, &dummy2, NULL, NULL);
 }
 
 
 // Debugging.
 void Assembler::RecordJSReturn() {
   positions_recorder()->WriteRecordedPositions();
   CheckBuffer();
   RecordRelocInfo(RelocInfo::JS_RETURN);
 }
 
@@ skipping 373 matching lines @@
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   next_buffer_check_ = pc_offset() + kCheckPoolInterval;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM