Thumb2 Backend: Thumb2 changes for Deoptimization and Code Aging

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 73 matching lines @@
   return kInstrSize;
 }
 
 
 void MacroAssembler::Call(Register target, Condition cond) {
   // Block constant pool for the call instruction sequence.
   BlockConstPoolScope block_const_pool(this);
   Label start;
   bind(&start);
   blx(target, cond);
-  ASSERT_EQ(CallSize(target, cond), SizeOfCodeGeneratedSince(&start));
 }
 
 
 int MacroAssembler::CallSize(
     Address target, RelocInfo::Mode rmode, Condition cond) {
   int size = 2 * kInstrSize;
   Instr mov_instr = cond | MOV | LeaveCC;
   intptr_t immediate = reinterpret_cast<intptr_t>(target);
   if (!Operand(immediate, rmode).is_single_instruction(this, mov_instr)) {
     size += kInstrSize;
@@ skipping 41 matching lines @@
 
   // Statement positions are expected to be recorded when the target
   // address is loaded. The mov method will automatically record
   // positions when pc is the target, since this is not the case here
   // we have to do it explicitly.
   positions_recorder()->WriteRecordedPositions();
 
   mov(ip, Operand(reinterpret_cast<int32_t>(target), rmode));
   blx(ip, cond);
 
-  ASSERT_EQ(CallSize(target, rmode, cond), SizeOfCodeGeneratedSince(&start));
   if (mode == NEVER_INLINE_TARGET_ADDRESS) {
     set_predictable_code_size(old_predictable_code_size);
   }
 }
 
 
 int MacroAssembler::CallSize(Handle<Code> code,
                              RelocInfo::Mode rmode,
                              TypeFeedbackId ast_id,
                              Condition cond) {
@@ skipping 209 matching lines @@
                               Condition cond) {
   if (CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
       isolate()->heap()->RootCanBeTreatedAsConstant(index) &&
       !predictable_code_size()) {
     // The CPU supports fast immediate values, and this root will never
     // change. We will load it as a relocatable immediate value.
     Handle<Object> root(&isolate()->heap()->roots_array_start()[index]);
     mov(destination, Operand(root), LeaveCC, cond);
     return;
   }
+  if (is_thumb_mode()) {
+    emit_it(cond);
+  }
   ldr(destination, MemOperand(kRootRegister, index << kPointerSizeLog2), cond);
 }
 
 
 void MacroAssembler::StoreRoot(Register source,
                                Heap::RootListIndex index,
                                Condition cond) {
   str(source, MemOperand(kRootRegister, index << kPointerSizeLog2), cond);
 }
 
@@ skipping 750 matching lines @@
       mov(r0, Operand(actual.immediate()));
     } else {
       cmp(expected.reg(), Operand(actual.reg()));
       b(eq, &regular_invoke);
     }
   }
 
   if (!definitely_matches) {
     if (!code_constant.is_null()) {
       mov(r3, Operand(code_constant));
+      CheckModeBit(r3);
       add(r3, r3, Operand(Code::kHeaderSize - kHeapObjectTag));
     }
 
     Handle<Code> adaptor =
         isolate()->builtins()->ArgumentsAdaptorTrampoline();
     if (flag == CALL_FUNCTION) {
       call_wrapper.BeforeCall(CallSize(adaptor));
       SetCallKind(r5, call_kind);
       Call(adaptor);
       call_wrapper.AfterCall();
@@ skipping 2319 matching lines @@
       num_reg_arguments, num_double_arguments);
   if (ActivationFrameAlignment() > kPointerSize) {
     ldr(sp, MemOperand(sp, stack_passed_arguments * kPointerSize));
   } else {
     add(sp, sp, Operand(stack_passed_arguments * sizeof(kPointerSize)));
   }
 }
 
 
 void MacroAssembler::GetRelocatedValueLocation(Register ldr_location,
-                               Register result) {
+                                               Register result) {
   const uint32_t kLdrOffsetMask = (1 << 12) - 1;
   const int32_t kPCRegOffset = 2 * kPointerSize;
+  const int32_t kThumbPCRegOffset = kPointerSize;
+  Label ldr_pc_arm, ldr_pc_thumb;
   ldr(result, MemOperand(ldr_location));
-  if (emit_debug_code()) {
+  if (FLAG_enable_thumb2_crankshaft || emit_debug_code()) {
     // Check that the instruction is a ldr reg, [pc + offset] .
-    and_(result, result, Operand(kLdrPCPattern));
-    cmp(result, Operand(kLdrPCPattern));
+    mov(ip, Operand(kLdrPCPattern));
+    and_(result, result, Operand(ip));
+    cmp(result, ip);
+    b(eq, &ldr_pc_arm);
+    // Result was clobbered. Restore it.
+    ldr(result, MemOperand(ldr_location, -3));
+    mov(ip, Operand(kThumbLdrPCPattern));
+    and_(result, result, Operand(ip));
+    cmp(result, ip);
     Check(eq, kTheInstructionToPatchShouldBeALoadFromPc);
-    // Result was clobbered. Restore it.
-    ldr(result, MemOperand(ldr_location));
+    ldr(result, MemOperand(ldr_location, 1));
+    and_(result, result, Operand(kLdrOffsetMask));
+    bic(ip, ldr_location, Operand(3));
+    add(result, ip, Operand(result));
+    add(result, result, Operand(kThumbPCRegOffset));
+    b(&ldr_pc_thumb);
   }
+  bind(&ldr_pc_arm);
+  ldr(result, MemOperand(ldr_location));
+
   // Get the address of the constant.
   and_(result, result, Operand(kLdrOffsetMask));
   add(result, ldr_location, Operand(result));
   add(result, result, Operand(kPCRegOffset));
+  bind(&ldr_pc_thumb);
 }
 
 
 void MacroAssembler::CheckPageFlag(
     Register object,
     Register scratch,
     int mask,
     Condition cc,
     Label* condition_met) {
   Bfc(scratch, object, 0, kPageSizeBits);
@@ skipping 296 matching lines @@
   ldr(ip, MemOperand(ip));
   cmp(scratch_reg, ip);
   b(gt, &no_memento_available);
   ldr(scratch_reg, MemOperand(scratch_reg, -AllocationMemento::kSize));
   cmp(scratch_reg,
       Operand(Handle<Map>(isolate()->heap()->allocation_memento_map())));
   bind(&no_memento_available);
 }
 
 
+void MacroAssembler::CheckModeBit(Register code) {
+  ldr(ip, FieldMemOperand(code, Code::kFlagsOffset));
+  tst(ip, Operand(0x1000));
+  add(code, code, Operand(1), LeaveCC, ne);
+}
+
+
 #ifdef DEBUG
 bool AreAliased(Register reg1,
                 Register reg2,
                 Register reg3,
                 Register reg4,
                 Register reg5,
                 Register reg6) {
   int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() +
     reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid();
 
@@ skipping 20 matching lines @@
   // bytes of instructions without failing with buffer size constraints.
   ASSERT(masm_.reloc_info_writer.pos() == address_ + size_ + Assembler::kGap);
 }
 
 
 CodePatcher::~CodePatcher() {
   // Indicate that code has changed.
   CPU::FlushICache(address_, size_);
 
   // Check that the code was patched as expected.
-  ASSERT(masm_.pc_ == address_ + size_);
   ASSERT(masm_.reloc_info_writer.pos() == address_ + size_ + Assembler::kGap);
 }
 
 
 void CodePatcher::Emit(Instr instr) {
   masm()->emit(instr);
 }
 
 
 void CodePatcher::Emit(Address addr) {
   masm()->emit(reinterpret_cast<Instr>(addr));
 }
 
 
 void CodePatcher::EmitCondition(Condition cond) {
   Instr instr = Assembler::instr_at(masm_.pc_);
   instr = (instr & ~kCondMask) | cond;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM