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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_MIPS64 | 7 #if V8_TARGET_ARCH_MIPS64 |
| 8 | 8 |
| 9 #include "src/base/division-by-constant.h" | 9 #include "src/base/division-by-constant.h" |
| 10 #include "src/bootstrapper.h" | 10 #include "src/bootstrapper.h" |
| (...skipping 1740 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 1751 | 1751 |
| 1752 void MacroAssembler::Ext(Register rt, | 1752 void MacroAssembler::Ext(Register rt, |
| 1753 Register rs, | 1753 Register rs, |
| 1754 uint16_t pos, | 1754 uint16_t pos, |
| 1755 uint16_t size) { | 1755 uint16_t size) { |
| 1756 DCHECK(pos < 32); | 1756 DCHECK(pos < 32); |
| 1757 DCHECK(pos + size < 33); | 1757 DCHECK(pos + size < 33); |
| 1758 ext_(rt, rs, pos, size); | 1758 ext_(rt, rs, pos, size); |
| 1759 } | 1759 } |
| 1760 | 1760 |
| 1761 void MacroAssembler::ExtractBits(Register rt, Register rs, uint16_t pos, | |
| 1762 uint16_t size) { | |
| 1763 DCHECK(pos < 64); | |
| 1764 DCHECK(size > 0 && size <= 64); | |
| 1765 DCHECK(pos + size <= 64); | |
| 1766 if (pos < 32) { | |
| 1767 if (size <= 32) { | |
| 1768 Dext(rt, rs, pos, size); | |
| 1769 } else { | |
| 1770 Dextm(rt, rs, pos, size); | |
| 1771 } | |
| 1772 } else if (pos < 64) { | |
|
miran.karic
2016/11/10 12:30:12
Can be just else Dextu(...
ivica.bogosavljevic
2016/11/10 13:31:41
Done.
| |
| 1773 if (size <= 32) { | |
| 1774 Dextu(rt, rs, pos, size); | |
| 1775 } | |
| 1776 } | |
| 1777 } | |
| 1761 | 1778 |
| 1762 void MacroAssembler::Dext(Register rt, Register rs, uint16_t pos, | 1779 void MacroAssembler::Dext(Register rt, Register rs, uint16_t pos, |
| 1763 uint16_t size) { | 1780 uint16_t size) { |
| 1764 DCHECK(pos < 32); | 1781 DCHECK(pos < 32); |
| 1765 DCHECK(pos + size < 33); | 1782 DCHECK(size > 0 && size <= 32); |
| 1766 dext_(rt, rs, pos, size); | 1783 dext_(rt, rs, pos, size); |
| 1767 } | 1784 } |
| 1768 | 1785 |
| 1769 | 1786 |
| 1770 void MacroAssembler::Dextm(Register rt, Register rs, uint16_t pos, | 1787 void MacroAssembler::Dextm(Register rt, Register rs, uint16_t pos, |
| 1771 uint16_t size) { | 1788 uint16_t size) { |
| 1772 DCHECK(pos < 32); | 1789 DCHECK(pos < 32); |
| 1773 DCHECK(size <= 64); | 1790 DCHECK(size > 32 && size <= 64); |
| 1791 DCHECK((pos + size) > 32 && (pos + size) <= 64); | |
| 1774 dextm(rt, rs, pos, size); | 1792 dextm(rt, rs, pos, size); |
| 1775 } | 1793 } |
| 1776 | 1794 |
| 1777 | 1795 |
| 1778 void MacroAssembler::Dextu(Register rt, Register rs, uint16_t pos, | 1796 void MacroAssembler::Dextu(Register rt, Register rs, uint16_t pos, |
| 1779 uint16_t size) { | 1797 uint16_t size) { |
| 1780 DCHECK(pos >= 32 && pos < 64); | 1798 DCHECK(pos >= 32 && pos < 64); |
| 1781 DCHECK(size < 33); | 1799 DCHECK(size < 0 && size <= 32); |
|
dusan.simicic
2016/11/10 10:03:13
Typo, size > 0.
| |
| 1800 DCHECK((pos + size) > 32 && (pos + size) <= 64); | |
| 1782 dextu(rt, rs, pos, size); | 1801 dextu(rt, rs, pos, size); |
| 1783 } | 1802 } |
| 1784 | 1803 |
| 1785 | 1804 |
| 1786 void MacroAssembler::Dins(Register rt, Register rs, uint16_t pos, | 1805 void MacroAssembler::Dins(Register rt, Register rs, uint16_t pos, |
| 1787 uint16_t size) { | 1806 uint16_t size) { |
| 1788 DCHECK(pos < 32); | 1807 DCHECK(pos < 32); |
| 1789 DCHECK(pos + size <= 32); | 1808 DCHECK(pos + size <= 32); |
| 1790 DCHECK(size != 0); | 1809 DCHECK(size != 0); |
| 1791 dins_(rt, rs, pos, size); | 1810 dins_(rt, rs, pos, size); |
| (...skipping 5352 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 7144 if (mag.shift > 0) sra(result, result, mag.shift); | 7163 if (mag.shift > 0) sra(result, result, mag.shift); |
| 7145 srl(at, dividend, 31); | 7164 srl(at, dividend, 31); |
| 7146 Addu(result, result, Operand(at)); | 7165 Addu(result, result, Operand(at)); |
| 7147 } | 7166 } |
| 7148 | 7167 |
| 7149 | 7168 |
| 7150 } // namespace internal | 7169 } // namespace internal |
| 7151 } // namespace v8 | 7170 } // namespace v8 |
| 7152 | 7171 |
| 7153 #endif // V8_TARGET_ARCH_MIPS64 | 7172 #endif // V8_TARGET_ARCH_MIPS64 |
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