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Side by Side Diff: src/compiler/mips64/instruction-selector-mips64.cc

Issue 2469253002: MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load` (Closed)
Patch Set: Created 4 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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1203 } else { 1203 } else {
1204 Mips64OperandGenerator g(this); 1204 Mips64OperandGenerator g(this);
1205 Emit(kMips64Shl, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), 1205 Emit(kMips64Shl, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
1206 g.TempImmediate(0)); 1206 g.TempImmediate(0));
1207 } 1207 }
1208 } 1208 }
1209 1209
1210 1210
1211 void InstructionSelector::VisitChangeUint32ToUint64(Node* node) { 1211 void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
1212 Mips64OperandGenerator g(this); 1212 Mips64OperandGenerator g(this);
1213 Node* value = node->InputAt(0);
1214 switch (value->opcode()) {
1215 // 32-bit operations will write their result in a 64 bit register,
1216 // clearing the top 32 bits of the destination register.
1217 case IrOpcode::kUint32Div:
1218 case IrOpcode::kUint32Mod:
1219 case IrOpcode::kUint32MulHigh: {
1220 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
1221 return;
1222 }
1223 case IrOpcode::kLoad: {
1224 LoadRepresentation load_rep = LoadRepresentationOf(value->op());
1225 if (load_rep.IsUnsigned()) {
1226 switch (load_rep.representation()) {
1227 case MachineRepresentation::kWord8:
1228 case MachineRepresentation::kWord16:
1229 case MachineRepresentation::kWord32:
1230 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
1231 return;
1232 default:
1233 break;
1234 }
1235 }
1236 }
1237 default:
1238 break;
1239 }
1213 Emit(kMips64Dext, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), 1240 Emit(kMips64Dext, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
1214 g.TempImmediate(0), g.TempImmediate(32)); 1241 g.TempImmediate(0), g.TempImmediate(32));
1215 } 1242 }
1216 1243
1217 1244
1218 void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) { 1245 void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
1219 Mips64OperandGenerator g(this); 1246 Mips64OperandGenerator g(this);
1220 Node* value = node->InputAt(0); 1247 Node* value = node->InputAt(0);
1221 if (CanCover(node, value)) { 1248 if (CanCover(node, value)) {
1222 switch (value->opcode()) { 1249 switch (value->opcode()) {
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2492 } else { 2519 } else {
2493 DCHECK(kArchVariant == kMips64r2); 2520 DCHECK(kArchVariant == kMips64r2);
2494 return MachineOperatorBuilder::AlignmentRequirements:: 2521 return MachineOperatorBuilder::AlignmentRequirements::
2495 NoUnalignedAccessSupport(); 2522 NoUnalignedAccessSupport();
2496 } 2523 }
2497 } 2524 }
2498 2525
2499 } // namespace compiler 2526 } // namespace compiler
2500 } // namespace internal 2527 } // namespace internal
2501 } // namespace v8 2528 } // namespace v8
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