OLD | NEW |
1 ; This file tests support for the select instruction with vector valued inputs. | 1 ; This file tests support for the select instruction with vector valued inputs. |
2 | 2 |
3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
4 ; RUN: | FileCheck %s | 4 ; RUN: | FileCheck %s |
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ |
6 ; RUN: | FileCheck %s | 6 ; RUN: | FileCheck %s |
7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ | 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ |
8 ; RUN: | FileCheck --check-prefix=SSE41 %s | 8 ; RUN: | FileCheck --check-prefix=SSE41 %s |
9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ | 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ |
10 ; RUN: | FileCheck --check-prefix=SSE41 %s | 10 ; RUN: | FileCheck --check-prefix=SSE41 %s |
(...skipping 11 matching lines...) Expand all Loading... |
22 ret <16 x i8> %res | 22 ret <16 x i8> %res |
23 ; CHECK-LABEL: test_select_v16i8 | 23 ; CHECK-LABEL: test_select_v16i8 |
24 ; CHECK: pand | 24 ; CHECK: pand |
25 ; CHECK: pandn | 25 ; CHECK: pandn |
26 ; CHECK: por | 26 ; CHECK: por |
27 | 27 |
28 ; SSE41-LABEL: test_select_v16i8 | 28 ; SSE41-LABEL: test_select_v16i8 |
29 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 29 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
30 | 30 |
31 ; MIPS32-LABEL: test_select_v16i8 | 31 ; MIPS32-LABEL: test_select_v16i8 |
32 ; MIPS32: lw [[T0:.*]],36(sp) | 32 ; MIPS32: addiu [[T0:.*]],sp,-20 |
33 ; MIPS32: lw [[T1:.*]],40(sp) | 33 ; MIPS32: sw [[T1:.*]], |
34 ; MIPS32: lw [[T2:.*]],44(sp) | 34 ; MIPS32: sw [[T2:.*]], |
35 ; MIPS32: lw [[T3:.*]],48(sp) | 35 ; MIPS32: sw [[T3:.*]], |
36 ; MIPS32: lw [[T4:.*]],52(sp) | 36 ; MIPS32: sw [[T4:.*]], |
37 ; MIPS32: lw [[T5:.*]],56(sp) | 37 ; MIPS32: sw [[T5:.*]], |
38 ; MIPS32: lw [[T6:.*]],60(sp) | 38 ; MIPS32: lw [[T6:.*]], |
39 ; MIPS32: lw [[T7:.*]],64(sp) | 39 ; MIPS32: lw [[T7:.*]], |
40 ; MIPS32: move [[T8:.*]],zero | 40 ; MIPS32: lw [[T8:.*]], |
41 ; MIPS32: move [[T9:.*]],zero | 41 ; MIPS32: lw [[T9:.*]], |
42 ; MIPS32: move [[T10:.*]],zero | 42 ; MIPS32: lw [[T10:.*]], |
43 ; MIPS32: move [[T11:.*]],zero | 43 ; MIPS32: lw [[T11:.*]], |
44 ; MIPS32: andi [[T12:.*]],a0,0xff | 44 ; MIPS32: lw [[T12:.*]], |
45 ; MIPS32: andi [[T12]],[[T12]],0x1 | 45 ; MIPS32: lw [[T13:.*]], |
46 ; MIPS32: andi [[T13:.*]],[[T0]],0xff | 46 ; MIPS32: move [[T14:.*]],zero |
47 ; MIPS32: andi [[T14:.*]],[[T4]],0xff | 47 ; MIPS32: move [[T15:.*]],zero |
48 ; MIPS32: movn [[T14]],[[T13]],[[T12]] | 48 ; MIPS32: move [[T5]],zero |
49 ; MIPS32: andi [[T14]],[[T14]],0xff | 49 ; MIPS32: move [[T4]],zero |
50 ; MIPS32: srl [[T8]],[[T8]],0x8 | 50 ; MIPS32: move [[T3]],a0 |
51 ; MIPS32: sll [[T8]],[[T8]],0x8 | 51 ; MIPS32: andi [[T3]],[[T3]],0xff |
52 ; MIPS32: or [[T14]],[[T14]],[[T8]] | 52 ; MIPS32: andi [[T3]],[[T3]],0x1 |
53 ; MIPS32: srl [[T8]],a0,0x8 | 53 ; MIPS32: move [[T2]],[[T6]] |
54 ; MIPS32: andi [[T8]],[[T8]],0xff | 54 ; MIPS32: andi [[T2]],[[T2]],0xff |
55 ; MIPS32: andi [[T8]],[[T8]],0x1 | 55 ; MIPS32: move [[T1]],[[T10]] |
56 ; MIPS32: srl [[T12]],[[T0]],0x8 | 56 ; MIPS32: andi [[T1]],[[T1]],0xff |
57 ; MIPS32: andi [[T12]],[[T12]],0xff | 57 ; MIPS32: movn [[T1]],[[T2]],[[T3]] |
58 ; MIPS32: srl [[T13]],[[T4]],0x8 | 58 ; MIPS32: andi [[T1]],[[T1]],0xff |
59 ; MIPS32: andi [[T13]],[[T13]],0xff | 59 ; MIPS32: srl [[T14]],[[T14]],0x8 |
60 ; MIPS32: movn [[T13]],[[T12]],[[T8]] | 60 ; MIPS32: sll [[T14]],[[T14]],0x8 |
61 ; MIPS32: andi [[T13]],[[T13]],0xff | 61 ; MIPS32: or [[T1]],[[T1]],[[T14]] |
62 ; MIPS32: sll [[T13]],[[T13]],0x8 | 62 ; MIPS32: move [[T14]],a0 |
63 ; MIPS32: lui [[T8]],0xffff | 63 ; MIPS32: srl [[T14]],[[T14]],0x8 |
64 ; MIPS32: ori [[T8]],[[T8]],0xff | 64 ; MIPS32: andi [[T14]],[[T14]],0xff |
65 ; MIPS32: and [[T14]],[[T14]],[[T8]] | 65 ; MIPS32: andi [[T14]],[[T14]],0x1 |
66 ; MIPS32: or [[T13]],[[T13]],[[T14]] | 66 ; MIPS32: move [[T3]],[[T6]] |
67 ; MIPS32: srl [[T8]],a0,0x10 | 67 ; MIPS32: srl [[T3]],[[T3]],0x8 |
68 ; MIPS32: andi [[T8]],[[T8]],0xff | 68 ; MIPS32: andi [[T3]],[[T3]],0xff |
69 ; MIPS32: andi [[T8]],[[T8]],0x1 | 69 ; MIPS32: move [[T2]],[[T10]] |
70 ; MIPS32: srl [[T12]],[[T0]],0x10 | 70 ; MIPS32: srl [[T2]],[[T2]],0x8 |
71 ; MIPS32: andi [[T12]],[[T12]],0xff | 71 ; MIPS32: andi [[T2]],[[T2]],0xff |
72 ; MIPS32: srl [[T14]],[[T4]],0x10 | 72 ; MIPS32: movn [[T2]],[[T3]],[[T14]] |
73 ; MIPS32: andi [[T14]],[[T14]],0xff | 73 ; MIPS32: andi [[T2]],[[T2]],0xff |
74 ; MIPS32: movn [[T14]],[[T12]],[[T8]] | 74 ; MIPS32: sll [[T2]],[[T2]],0x8 |
| 75 ; MIPS32: lui [[T14]],0xffff |
| 76 ; MIPS32: ori [[T14]],[[T14]],0xff |
| 77 ; MIPS32: and [[T1]],[[T1]],[[T14]] |
| 78 ; MIPS32: or [[T2]],[[T2]],[[T1]] |
| 79 ; MIPS32: move [[T14]],a0 |
| 80 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 81 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 82 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 83 ; MIPS32: move [[T3]],[[T6]] |
| 84 ; MIPS32: srl [[T3]],[[T3]],0x10 |
| 85 ; MIPS32: andi [[T3]],[[T3]],0xff |
| 86 ; MIPS32: move [[T1]],[[T10]] |
| 87 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 88 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 89 ; MIPS32: movn [[T1]],[[T3]],[[T14]] |
| 90 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 91 ; MIPS32: sll [[T1]],[[T1]],0x10 |
| 92 ; MIPS32: lui [[T14]],0xff00 |
| 93 ; MIPS32: ori [[T14]],[[T14]],0xffff |
| 94 ; MIPS32: and [[T2]],[[T2]],[[T14]] |
| 95 ; MIPS32: or [[T1]],[[T1]],[[T2]] |
| 96 ; MIPS32: srl [[T16:.*]],a0,0x18 |
| 97 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 98 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 99 ; MIPS32: srl [[T10]],[[T10]],0x18 |
| 100 ; MIPS32: movn [[T10]],[[T6]],[[T16]] |
| 101 ; MIPS32: srl [[T10]],[[T10]],0x18 |
| 102 ; MIPS32: sll [[T1]],[[T1]],0x8 |
| 103 ; MIPS32: srl [[T1]],[[T1]],0x8 |
| 104 ; MIPS32: or [[T10]],[[T10]],[[T1]] |
| 105 ; MIPS32: move [[T6]],a1 |
| 106 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 107 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 108 ; MIPS32: move [[T16]],[[T7]] |
| 109 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 110 ; MIPS32: move [[T14]],[[T11]] |
| 111 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 112 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
| 113 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 114 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 115 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 116 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
| 117 ; MIPS32: move [[T6]],a1 |
| 118 ; MIPS32: srl [[T6]],[[T6]],0x8 |
| 119 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 120 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 121 ; MIPS32: move [[T16]],[[T7]] |
| 122 ; MIPS32: srl [[T16]],[[T16]],0x8 |
| 123 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 124 ; MIPS32: move [[T15]],[[T11]] |
| 125 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 126 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 127 ; MIPS32: movn [[T15]],[[T16]],[[T6]] |
| 128 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 129 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 130 ; MIPS32: lui [[T6]],0xffff |
| 131 ; MIPS32: ori [[T6]],[[T6]],0xff |
| 132 ; MIPS32: and [[T14]],[[T14]],[[T6]] |
| 133 ; MIPS32: or [[T15]],[[T15]],[[T14]] |
| 134 ; MIPS32: move [[T6]],a1 |
| 135 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 136 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 137 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 138 ; MIPS32: move [[T16]],[[T7]] |
| 139 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 140 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 141 ; MIPS32: move [[T14]],[[T11]] |
| 142 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 143 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 144 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
75 ; MIPS32: andi [[T14]],[[T14]],0xff | 145 ; MIPS32: andi [[T14]],[[T14]],0xff |
76 ; MIPS32: sll [[T14]],[[T14]],0x10 | 146 ; MIPS32: sll [[T14]],[[T14]],0x10 |
77 ; MIPS32: lui [[T8]],0xff00 | 147 ; MIPS32: lui [[T6]],0xff00 |
78 ; MIPS32: ori [[T8]],[[T8]],0xffff | 148 ; MIPS32: ori [[T6]],[[T6]],0xffff |
79 ; MIPS32: and [[T13]],[[T13]],[[T8]] | 149 ; MIPS32: and [[T15]],[[T15]],[[T6]] |
80 ; MIPS32: or [[T14]],[[T14]],[[T13]] | 150 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
81 ; MIPS32: srl [[T15:.*]],a0,0x18 | 151 ; MIPS32: srl [[T17:.*]],a1,0x18 |
82 ; MIPS32: andi [[T15]],[[T15]],0x1 | 152 ; MIPS32: andi [[T17]],[[T17]],0x1 |
83 ; MIPS32: srl [[T0]],[[T0]],0x18 | 153 ; MIPS32: srl [[T7]],[[T7]],0x18 |
84 ; MIPS32: srl [[T4]],[[T4]],0x18 | 154 ; MIPS32: srl [[T11]],[[T11]],0x18 |
85 ; MIPS32: movn [[T4]],[[T0]],[[T15]] | 155 ; MIPS32: movn [[T11]],[[T7]],[[T17]] |
86 ; MIPS32: srl [[T4]],[[T4]],0x18 | 156 ; MIPS32: srl [[T11]],[[T11]],0x18 |
87 ; MIPS32: sll [[T14]],[[T14]],0x8 | 157 ; MIPS32: sll [[T14]],[[T14]],0x8 |
88 ; MIPS32: srl [[T14]],[[T14]],0x8 | 158 ; MIPS32: srl [[T14]],[[T14]],0x8 |
89 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] | 159 ; MIPS32: or [[T11]],[[T11]],[[T14]] |
90 ; MIPS32: andi [[T0]],a1,0xff | 160 ; MIPS32: move [[T6]],a2 |
91 ; MIPS32: andi [[T0]],[[T0]],0x1 | 161 ; MIPS32: andi [[T6]],[[T6]],0xff |
92 ; MIPS32: andi [[T15]],[[T1]],0xff | 162 ; MIPS32: andi [[T6]],[[T6]],0x1 |
93 ; MIPS32: andi [[T8]],[[T5]],0xff | 163 ; MIPS32: move [[T7]],[[T8]] |
94 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | 164 ; MIPS32: andi [[T7]],[[T7]],0xff |
95 ; MIPS32: andi [[T8]],[[T8]],0xff | 165 ; MIPS32: move [[T16]],[[T12]] |
96 ; MIPS32: srl [[T9]],[[T9]],0x8 | 166 ; MIPS32: andi [[T16]],[[T16]],0xff |
97 ; MIPS32: sll [[T9]],[[T9]],0x8 | 167 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
98 ; MIPS32: or [[T8]],[[T8]],[[T9]] | 168 ; MIPS32: andi [[T16]],[[T16]],0xff |
99 ; MIPS32: srl [[T0]],a1,0x8 | 169 ; MIPS32: srl [[T5]],[[T5]],0x8 |
100 ; MIPS32: andi [[T0]],[[T0]],0xff | 170 ; MIPS32: sll [[T5]],[[T5]],0x8 |
101 ; MIPS32: andi [[T0]],[[T0]],0x1 | 171 ; MIPS32: or [[T16]],[[T16]],[[T5]] |
102 ; MIPS32: srl [[T15]],[[T1]],0x8 | 172 ; MIPS32: move [[T6]],a2 |
103 ; MIPS32: andi [[T15]],[[T15]],0xff | 173 ; MIPS32: srl [[T6]],[[T6]],0x8 |
104 ; MIPS32: srl [[T9]],[[T5]],0x8 | 174 ; MIPS32: andi [[T6]],[[T6]],0xff |
105 ; MIPS32: andi [[T9]],[[T9]],0xff | 175 ; MIPS32: andi [[T6]],[[T6]],0x1 |
106 ; MIPS32: movn [[T9]],[[T15]],[[T0]] | 176 ; MIPS32: move [[T7]],[[T8]] |
107 ; MIPS32: andi [[T9]],[[T9]],0xff | 177 ; MIPS32: srl [[T7]],[[T7]],0x8 |
108 ; MIPS32: sll [[T9]],[[T9]],0x8 | 178 ; MIPS32: andi [[T7]],[[T7]],0xff |
109 ; MIPS32: lui [[T0]],0xffff | 179 ; MIPS32: move [[T17]],[[T12]] |
110 ; MIPS32: ori [[T0]],[[T0]],0xff | 180 ; MIPS32: srl [[T17]],[[T17]],0x8 |
111 ; MIPS32: and [[T8]],[[T8]],[[T0]] | 181 ; MIPS32: andi [[T17]],[[T17]],0xff |
112 ; MIPS32: or [[T9]],[[T9]],[[T8]] | 182 ; MIPS32: movn [[T17]],[[T7]],[[T6]] |
113 ; MIPS32: srl [[T0]],a1,0x10 | 183 ; MIPS32: andi [[T17]],[[T17]],0xff |
114 ; MIPS32: andi [[T0]],[[T0]],0xff | 184 ; MIPS32: sll [[T17]],[[T17]],0x8 |
115 ; MIPS32: andi [[T0]],[[T0]],0x1 | 185 ; MIPS32: lui [[T6]],0xffff |
116 ; MIPS32: srl [[T15]],[[T1]],0x10 | 186 ; MIPS32: ori [[T6]],[[T6]],0xff |
117 ; MIPS32: andi [[T15]],[[T15]],0xff | 187 ; MIPS32: and [[T16]],[[T16]],[[T6]] |
118 ; MIPS32: srl [[T8]],[[T5]],0x10 | 188 ; MIPS32: or [[T17]],[[T17]],[[T16]] |
119 ; MIPS32: andi [[T8]],[[T8]],0xff | 189 ; MIPS32: move [[T6]],a2 |
120 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | 190 ; MIPS32: srl [[T6]],[[T6]],0x10 |
121 ; MIPS32: andi [[T8]],[[T8]],0xff | 191 ; MIPS32: andi [[T6]],[[T6]],0xff |
122 ; MIPS32: sll [[T8]],[[T8]],0x10 | 192 ; MIPS32: andi [[T6]],[[T6]],0x1 |
123 ; MIPS32: lui [[T0]],0xff00 | 193 ; MIPS32: move [[T7]],[[T8]] |
124 ; MIPS32: ori [[T0]],[[T0]],0xffff | 194 ; MIPS32: srl [[T7]],[[T7]],0x10 |
125 ; MIPS32: and [[T9]],[[T9]],[[T0]] | 195 ; MIPS32: andi [[T7]],[[T7]],0xff |
126 ; MIPS32: or [[T8]],[[T8]],[[T9]] | 196 ; MIPS32: move [[T16]],[[T12]] |
127 ; MIPS32: srl [[T16:.*]],a1,0x18 | 197 ; MIPS32: srl [[T16]],[[T16]],0x10 |
128 ; MIPS32: andi [[T16]],[[T16]],0x1 | 198 ; MIPS32: andi [[T16]],[[T16]],0xff |
129 ; MIPS32: srl [[T1]],[[T1]],0x18 | 199 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
130 ; MIPS32: srl [[T5]],[[T5]],0x18 | 200 ; MIPS32: andi [[T16]],[[T16]],0xff |
131 ; MIPS32: movn [[T5]],[[T1]],[[T16]] | 201 ; MIPS32: sll [[T16]],[[T16]],0x10 |
132 ; MIPS32: srl [[T5]],[[T5]],0x18 | 202 ; MIPS32: lui [[T6]],0xff00 |
133 ; MIPS32: sll [[T8]],[[T8]],0x8 | 203 ; MIPS32: ori [[T6]],[[T6]],0xffff |
134 ; MIPS32: srl [[T8]],[[T8]],0x8 | 204 ; MIPS32: and [[T17]],[[T17]],[[T6]] |
135 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] | 205 ; MIPS32: or [[T16]],[[T16]],[[T17]] |
136 ; MIPS32: andi [[T0]],a2,0xff | 206 ; MIPS32: srl [[T18:.*]],a2,0x18 |
137 ; MIPS32: andi [[T0]],[[T0]],0x1 | 207 ; MIPS32: andi [[T18]],[[T18]],0x1 |
138 ; MIPS32: andi [[T1]],[[T2]],0xff | 208 ; MIPS32: srl [[T8]],[[T8]],0x18 |
139 ; MIPS32: andi [[T15]],[[T6]],0xff | 209 ; MIPS32: srl [[T12]],[[T12]],0x18 |
140 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | 210 ; MIPS32: movn [[T12]],[[T8]],[[T18]] |
141 ; MIPS32: andi [[T15]],[[T15]],0xff | 211 ; MIPS32: srl [[T12]],[[T12]],0x18 |
142 ; MIPS32: srl [[T10]],[[T10]],0x8 | |
143 ; MIPS32: sll [[T10]],[[T10]],0x8 | |
144 ; MIPS32: or [[T15]],[[T15]],[[T10]] | |
145 ; MIPS32: srl [[T0]],a2,0x8 | |
146 ; MIPS32: andi [[T0]],[[T0]],0xff | |
147 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
148 ; MIPS32: srl [[T1]],[[T2]],0x8 | |
149 ; MIPS32: andi [[T1]],[[T1]],0xff | |
150 ; MIPS32: srl [[T16]],[[T6]],0x8 | |
151 ; MIPS32: andi [[T16]],[[T16]],0xff | |
152 ; MIPS32: movn [[T16]],[[T1]],[[T0]] | |
153 ; MIPS32: andi [[T16]],[[T16]],0xff | |
154 ; MIPS32: sll [[T16]],[[T16]],0x8 | 212 ; MIPS32: sll [[T16]],[[T16]],0x8 |
155 ; MIPS32: lui [[T0]],0xffff | 213 ; MIPS32: srl [[T16]],[[T16]],0x8 |
156 ; MIPS32: ori [[T0]],[[T0]],0xff | 214 ; MIPS32: or [[T12]],[[T12]],[[T16]] |
157 ; MIPS32: and [[T15]],[[T15]],[[T0]] | 215 ; MIPS32: move [[T6]],a3 |
158 ; MIPS32: or [[T16]],[[T16]],[[T15]] | 216 ; MIPS32: andi [[T6]],[[T6]],0xff |
159 ; MIPS32: srl [[T0]],a2,0x10 | 217 ; MIPS32: andi [[T6]],[[T6]],0x1 |
160 ; MIPS32: andi [[T0]],[[T0]],0xff | 218 ; MIPS32: move [[T7]],[[T9]] |
161 ; MIPS32: andi [[T0]],[[T0]],0x1 | 219 ; MIPS32: andi [[T7]],[[T7]],0xff |
162 ; MIPS32: srl [[T1]],[[T2]],0x10 | 220 ; MIPS32: move [[T16]],[[T13]] |
163 ; MIPS32: andi [[T1]],[[T1]],0xff | 221 ; MIPS32: andi [[T16]],[[T16]],0xff |
164 ; MIPS32: srl [[T15]],[[T6]],0x10 | 222 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
165 ; MIPS32: andi [[T15]],[[T15]],0xff | 223 ; MIPS32: andi [[T16]],[[T16]],0xff |
166 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | 224 ; MIPS32: srl [[T4]],[[T4]],0x8 |
167 ; MIPS32: andi [[T15]],[[T15]],0xff | 225 ; MIPS32: sll [[T4]],[[T4]],0x8 |
168 ; MIPS32: sll [[T15]],[[T15]],0x10 | 226 ; MIPS32: or [[T16]],[[T16]],[[T4]] |
169 ; MIPS32: lui [[T0]],0xff00 | 227 ; MIPS32: move [[T6]],a3 |
170 ; MIPS32: ori [[T0]],[[T0]],0xffff | 228 ; MIPS32: srl [[T6]],[[T6]],0x8 |
171 ; MIPS32: and [[T16]],[[T16]],[[T0]] | 229 ; MIPS32: andi [[T6]],[[T6]],0xff |
172 ; MIPS32: or [[T15]],[[T15]],[[T16]] | 230 ; MIPS32: andi [[T6]],[[T6]],0x1 |
173 ; MIPS32: srl [[T17:.*]],a2,0x18 | 231 ; MIPS32: move [[T7]],[[T9]] |
174 ; MIPS32: andi [[T17]],[[T17]],0x1 | 232 ; MIPS32: srl [[T7]],[[T7]],0x8 |
175 ; MIPS32: srl [[T2]],[[T2]],0x18 | 233 ; MIPS32: andi [[T7]],[[T7]],0xff |
176 ; MIPS32: srl [[T6]],[[T6]],0x18 | 234 ; MIPS32: move [[T17]],[[T13]] |
177 ; MIPS32: movn [[T6]],[[T2]],[[T17]] | 235 ; MIPS32: srl [[T17]],[[T17]],0x8 |
178 ; MIPS32: srl [[T6]],[[T6]],0x18 | 236 ; MIPS32: andi [[T17]],[[T17]],0xff |
179 ; MIPS32: sll [[T15]],[[T15]],0x8 | 237 ; MIPS32: movn [[T17]],[[T7]],[[T6]] |
180 ; MIPS32: srl [[T15]],[[T15]],0x8 | 238 ; MIPS32: andi [[T17]],[[T17]],0xff |
181 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] | 239 ; MIPS32: sll [[T17]],[[T17]],0x8 |
182 ; MIPS32: andi [[T0]],a3,0xff | 240 ; MIPS32: lui [[T6]],0xffff |
183 ; MIPS32: andi [[T0]],[[T0]],0x1 | 241 ; MIPS32: ori [[T6]],[[T6]],0xff |
184 ; MIPS32: andi [[T1]],[[T3]],0xff | 242 ; MIPS32: and [[T16]],[[T16]],[[T6]] |
185 ; MIPS32: andi [[T15]],[[T7]],0xff | 243 ; MIPS32: or [[T17]],[[T17]],[[T16]] |
186 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | 244 ; MIPS32: move [[T6]],a3 |
187 ; MIPS32: andi [[T15]],[[T15]],0xff | 245 ; MIPS32: srl [[T6]],[[T6]],0x10 |
188 ; MIPS32: srl [[T11]],[[T11]],0x8 | 246 ; MIPS32: andi [[T6]],[[T6]],0xff |
189 ; MIPS32: sll [[T11]],[[T11]],0x8 | 247 ; MIPS32: andi [[T6]],[[T6]],0x1 |
190 ; MIPS32: or [[T15]],[[T15]],[[T11]] | 248 ; MIPS32: move [[T7]],[[T9]] |
191 ; MIPS32: srl [[T0]],a3,0x8 | 249 ; MIPS32: srl [[T7]],[[T7]],0x10 |
192 ; MIPS32: andi [[T0]],[[T0]],0xff | 250 ; MIPS32: andi [[T7]],[[T7]],0xff |
193 ; MIPS32: andi [[T0]],[[T0]],0x1 | 251 ; MIPS32: move [[T16]],[[T13]] |
194 ; MIPS32: srl [[T1]],[[T3]],0x8 | 252 ; MIPS32: srl [[T16]],[[T16]],0x10 |
195 ; MIPS32: andi [[T1]],[[T1]],0xff | 253 ; MIPS32: andi [[T16]],[[T16]],0xff |
196 ; MIPS32: srl [[T16]],[[T7]],0x8 | 254 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
197 ; MIPS32: andi [[T16]],[[T16]],0xff | 255 ; MIPS32: andi [[T16]],[[T16]],0xff |
198 ; MIPS32: movn [[T16]],[[T1]],[[T0]] | 256 ; MIPS32: sll [[T16]],[[T16]],0x10 |
199 ; MIPS32: andi [[T16]],[[T16]],0xff | 257 ; MIPS32: lui [[T6]],0xff00 |
| 258 ; MIPS32: ori [[T6]],[[T6]],0xffff |
| 259 ; MIPS32: and [[T17]],[[T17]],[[T6]] |
| 260 ; MIPS32: or [[T16]],[[T16]],[[T17]] |
| 261 ; MIPS32: srl [[T19:.*]],a3,0x18 |
| 262 ; MIPS32: andi [[T19]],[[T19]],0x1 |
| 263 ; MIPS32: srl [[T9]],[[T9]],0x18 |
| 264 ; MIPS32: srl [[T13]],[[T13]],0x18 |
| 265 ; MIPS32: movn [[T13]],[[T9]],[[T19]] |
| 266 ; MIPS32: srl [[T13]],[[T13]],0x18 |
200 ; MIPS32: sll [[T16]],[[T16]],0x8 | 267 ; MIPS32: sll [[T16]],[[T16]],0x8 |
201 ; MIPS32: lui [[T0]],0xffff | 268 ; MIPS32: srl [[T16]],[[T16]],0x8 |
202 ; MIPS32: ori [[T0]],[[T0]],0xff | 269 ; MIPS32: or [[T13]],[[T13]],[[T16]] |
203 ; MIPS32: and [[T15]],[[T15]],[[T0]] | 270 ; MIPS32: move v0,[[T10]] |
204 ; MIPS32: or [[T16]],[[T16]],[[T15]] | 271 ; MIPS32: move v1,[[T11]] |
205 ; MIPS32: srl [[T0]],a3,0x10 | 272 ; MIPS32: move a0,[[T12]] |
206 ; MIPS32: andi [[T0]],[[T0]],0xff | 273 ; MIPS32: move a1,[[T13]] |
207 ; MIPS32: andi [[T0]],[[T0]],0x1 | 274 ; MIPS32: lw [[T5]], |
208 ; MIPS32: srl [[T1]],[[T3]],0x10 | 275 ; MIPS32: lw [[T4]], |
209 ; MIPS32: andi [[T1]],[[T1]],0xff | 276 ; MIPS32: lw [[T3]], |
210 ; MIPS32: srl [[T15]],[[T7]],0x10 | 277 ; MIPS32: lw [[T2]], |
211 ; MIPS32: andi [[T15]],[[T15]],0xff | 278 ; MIPS32: lw [[T1]], |
212 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | 279 ; MIPS32: addiu [[T0]],sp,20 |
213 ; MIPS32: andi [[T15]],[[T15]],0xff | |
214 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
215 ; MIPS32: lui [[T0]],0xff00 | |
216 ; MIPS32: ori [[T0]],[[T0]],0xffff | |
217 ; MIPS32: and [[T16]],[[T16]],[[T0]] | |
218 ; MIPS32: or [[T15]],[[T15]],[[T16]] | |
219 ; MIPS32: srl [[T18:.*]],a3,0x18 | |
220 ; MIPS32: andi [[T18]],[[T18]],0x1 | |
221 ; MIPS32: srl [[T3]],[[T3]],0x18 | |
222 ; MIPS32: srl [[T7]],[[T7]],0x18 | |
223 ; MIPS32: movn [[T7]],[[T3]],[[T18]] | |
224 ; MIPS32: srl [[T7]],[[T7]],0x18 | |
225 ; MIPS32: sll [[T15]],[[T15]],0x8 | |
226 ; MIPS32: srl [[T15]],[[T15]],0x8 | |
227 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] | |
228 } | 280 } |
229 | 281 |
230 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, | 282 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, |
231 <16 x i1> %arg2) { | 283 <16 x i1> %arg2) { |
232 entry: | 284 entry: |
233 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 | 285 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 |
234 ret <16 x i1> %res | 286 ret <16 x i1> %res |
235 ; CHECK-LABEL: test_select_v16i1 | 287 ; CHECK-LABEL: test_select_v16i1 |
236 ; CHECK: pand | 288 ; CHECK: pand |
237 ; CHECK: pandn | 289 ; CHECK: pandn |
238 ; CHECK: por | 290 ; CHECK: por |
239 | 291 |
240 ; SSE41-LABEL: test_select_v16i1 | 292 ; SSE41-LABEL: test_select_v16i1 |
241 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 293 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
242 | 294 |
243 ; MIPS32-LABEL: test_select_v16i1 | 295 ; MIPS32-LABEL: test_select_v16i1 |
244 ; MIPS32: lw [[T0:.*]],36(sp) | 296 ; MIPS32: addiu [[T0:.*]],sp,-20 |
245 ; MIPS32: lw [[T1:.*]],40(sp) | 297 ; MIPS32: sw [[T1:.*]], |
246 ; MIPS32: lw [[T2:.*]],44(sp) | 298 ; MIPS32: sw [[T2:.*]], |
247 ; MIPS32: lw [[T3:.*]],48(sp) | 299 ; MIPS32: sw [[T3:.*]], |
248 ; MIPS32: lw [[T4:.*]],52(sp) | 300 ; MIPS32: sw [[T4:.*]], |
249 ; MIPS32: lw [[T5:.*]],56(sp) | 301 ; MIPS32: sw [[T5:.*]], |
250 ; MIPS32: lw [[T6:.*]],60(sp) | 302 ; MIPS32: lw [[T6:.*]], |
251 ; MIPS32: lw [[T7:.*]],64(sp) | 303 ; MIPS32: lw [[T7:.*]], |
252 ; MIPS32: move [[T8:.*]],zero | 304 ; MIPS32: lw [[T8:.*]], |
253 ; MIPS32: move [[T9:.*]],zero | 305 ; MIPS32: lw [[T9:.*]], |
254 ; MIPS32: move [[T10:.*]],zero | 306 ; MIPS32: lw [[T10:.*]], |
255 ; MIPS32: move [[T11:.*]],zero | 307 ; MIPS32: lw [[T11:.*]], |
256 ; MIPS32: andi [[T12:.*]],a0,0xff | 308 ; MIPS32: lw [[T12:.*]], |
257 ; MIPS32: andi [[T12]],[[T12]],0x1 | 309 ; MIPS32: lw [[T13:.*]], |
258 ; MIPS32: andi [[T13:.*]],[[T0]],0xff | 310 ; MIPS32: move [[T14:.*]],zero |
259 ; MIPS32: andi [[T13]],[[T13]],0x1 | 311 ; MIPS32: move [[T15:.*]],zero |
260 ; MIPS32: andi [[T14:.*]],[[T4]],0xff | 312 ; MIPS32: move [[T5]],zero |
261 ; MIPS32: andi [[T14]],[[T14]],0x1 | 313 ; MIPS32: move [[T4]],zero |
262 ; MIPS32: movn [[T14]],[[T13]],[[T12]] | 314 ; MIPS32: move [[T3]],a0 |
263 ; MIPS32: andi [[T14]],[[T14]],0xff | 315 ; MIPS32: andi [[T3]],[[T3]],0xff |
264 ; MIPS32: srl [[T8]],[[T8]],0x8 | 316 ; MIPS32: andi [[T3]],[[T3]],0x1 |
265 ; MIPS32: sll [[T8]],[[T8]],0x8 | 317 ; MIPS32: move [[T2]],[[T6]] |
266 ; MIPS32: or [[T14]],[[T14]],[[T8]] | 318 ; MIPS32: andi [[T2]],[[T2]],0xff |
267 ; MIPS32: srl [[T8]],a0,0x8 | 319 ; MIPS32: andi [[T2]],[[T2]],0x1 |
268 ; MIPS32: andi [[T8]],[[T8]],0xff | 320 ; MIPS32: move [[T1]],[[T10]] |
269 ; MIPS32: andi [[T8]],[[T8]],0x1 | 321 ; MIPS32: andi [[T1]],[[T1]],0xff |
270 ; MIPS32: srl [[T12]],[[T0]],0x8 | 322 ; MIPS32: andi [[T1]],[[T1]],0x1 |
271 ; MIPS32: andi [[T12]],[[T12]],0xff | 323 ; MIPS32: movn [[T1]],[[T2]],[[T3]] |
272 ; MIPS32: andi [[T12]],[[T12]],0x1 | 324 ; MIPS32: andi [[T1]],[[T1]],0xff |
273 ; MIPS32: srl [[T13]],[[T4]],0x8 | 325 ; MIPS32: srl [[T14]],[[T14]],0x8 |
274 ; MIPS32: andi [[T13]],[[T13]],0xff | 326 ; MIPS32: sll [[T14]],[[T14]],0x8 |
275 ; MIPS32: andi [[T13]],[[T13]],0x1 | 327 ; MIPS32: or [[T1]],[[T1]],[[T14]] |
276 ; MIPS32: movn [[T13]],[[T12]],[[T8]] | 328 ; MIPS32: move [[T14]],a0 |
277 ; MIPS32: andi [[T13]],[[T13]],0xff | 329 ; MIPS32: srl [[T14]],[[T14]],0x8 |
278 ; MIPS32: sll [[T13]],[[T13]],0x8 | 330 ; MIPS32: andi [[T14]],[[T14]],0xff |
279 ; MIPS32: lui [[T8]],0xffff | 331 ; MIPS32: andi [[T14]],[[T14]],0x1 |
280 ; MIPS32: ori [[T8]],[[T8]],0xff | 332 ; MIPS32: move [[T3]],[[T6]] |
281 ; MIPS32: and [[T14]],[[T14]],[[T8]] | 333 ; MIPS32: srl [[T3]],[[T3]],0x8 |
282 ; MIPS32: or [[T13]],[[T13]],[[T14]] | 334 ; MIPS32: andi [[T3]],[[T3]],0xff |
283 ; MIPS32: srl [[T8]],a0,0x10 | 335 ; MIPS32: andi [[T3]],[[T3]],0x1 |
284 ; MIPS32: andi [[T8]],[[T8]],0xff | 336 ; MIPS32: move [[T2]],[[T10]] |
285 ; MIPS32: andi [[T8]],[[T8]],0x1 | 337 ; MIPS32: srl [[T2]],[[T2]],0x8 |
286 ; MIPS32: srl [[T12]],[[T0]],0x10 | 338 ; MIPS32: andi [[T2]],[[T2]],0xff |
287 ; MIPS32: andi [[T12]],[[T12]],0xff | 339 ; MIPS32: andi [[T2]],[[T2]],0x1 |
288 ; MIPS32: andi [[T12]],[[T12]],0x1 | 340 ; MIPS32: movn [[T2]],[[T3]],[[T14]] |
289 ; MIPS32: srl [[T14]],[[T4]],0x10 | 341 ; MIPS32: andi [[T2]],[[T2]],0xff |
290 ; MIPS32: andi [[T14]],[[T14]],0xff | 342 ; MIPS32: sll [[T2]],[[T2]],0x8 |
291 ; MIPS32: andi [[T14]],[[T14]],0x1 | 343 ; MIPS32: lui [[T14]],0xffff |
292 ; MIPS32: movn [[T14]],[[T12]],[[T8]] | 344 ; MIPS32: ori [[T14]],[[T14]],0xff |
| 345 ; MIPS32: and [[T1]],[[T1]],[[T14]] |
| 346 ; MIPS32: or [[T2]],[[T2]],[[T1]] |
| 347 ; MIPS32: move [[T14]],a0 |
| 348 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 349 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 350 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 351 ; MIPS32: move [[T3]],[[T6]] |
| 352 ; MIPS32: srl [[T3]],[[T3]],0x10 |
| 353 ; MIPS32: andi [[T3]],[[T3]],0xff |
| 354 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 355 ; MIPS32: move [[T1]],[[T10]] |
| 356 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 357 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 358 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 359 ; MIPS32: movn [[T1]],[[T3]],[[T14]] |
| 360 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 361 ; MIPS32: sll [[T1]],[[T1]],0x10 |
| 362 ; MIPS32: lui [[T14]],0xff00 |
| 363 ; MIPS32: ori [[T14]],[[T14]],0xffff |
| 364 ; MIPS32: and [[T2]],[[T2]],[[T14]] |
| 365 ; MIPS32: or [[T1]],[[T1]],[[T2]] |
| 366 ; MIPS32: srl [[T16:.*]],a0,0x18 |
| 367 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 368 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 369 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 370 ; MIPS32: srl [[T10]],[[T10]],0x18 |
| 371 ; MIPS32: andi [[T10]],[[T10]],0x1 |
| 372 ; MIPS32: movn [[T10]],[[T6]],[[T16]] |
| 373 ; MIPS32: srl [[T10]],[[T10]],0x18 |
| 374 ; MIPS32: sll [[T1]],[[T1]],0x8 |
| 375 ; MIPS32: srl [[T1]],[[T1]],0x8 |
| 376 ; MIPS32: or [[T10]],[[T10]],[[T1]] |
| 377 ; MIPS32: move [[T6]],a1 |
| 378 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 379 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 380 ; MIPS32: move [[T16]],[[T7]] |
| 381 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 382 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 383 ; MIPS32: move [[T14]],[[T11]] |
| 384 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 385 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 386 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
| 387 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 388 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 389 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 390 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
| 391 ; MIPS32: move [[T6]],a1 |
| 392 ; MIPS32: srl [[T6]],[[T6]],0x8 |
| 393 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 394 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 395 ; MIPS32: move [[T16]],[[T7]] |
| 396 ; MIPS32: srl [[T16]],[[T16]],0x8 |
| 397 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 398 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 399 ; MIPS32: move [[T15]],[[T11]] |
| 400 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 401 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 402 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 403 ; MIPS32: movn [[T15]],[[T16]],[[T6]] |
| 404 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 405 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 406 ; MIPS32: lui [[T6]],0xffff |
| 407 ; MIPS32: ori [[T6]],[[T6]],0xff |
| 408 ; MIPS32: and [[T14]],[[T14]],[[T6]] |
| 409 ; MIPS32: or [[T15]],[[T15]],[[T14]] |
| 410 ; MIPS32: move [[T6]],a1 |
| 411 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 412 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 413 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 414 ; MIPS32: move [[T16]],[[T7]] |
| 415 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 416 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 417 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 418 ; MIPS32: move [[T14]],[[T11]] |
| 419 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 420 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 421 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 422 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
293 ; MIPS32: andi [[T14]],[[T14]],0xff | 423 ; MIPS32: andi [[T14]],[[T14]],0xff |
294 ; MIPS32: sll [[T14]],[[T14]],0x10 | 424 ; MIPS32: sll [[T14]],[[T14]],0x10 |
295 ; MIPS32: lui [[T8]],0xff00 | 425 ; MIPS32: lui [[T6]],0xff00 |
296 ; MIPS32: ori [[T8]],[[T8]],0xffff | 426 ; MIPS32: ori [[T6]],[[T6]],0xffff |
297 ; MIPS32: and [[T13]],[[T13]],[[T8]] | 427 ; MIPS32: and [[T15]],[[T15]],[[T6]] |
298 ; MIPS32: or [[T14]],[[T14]],[[T13]] | 428 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
299 ; MIPS32: srl [[T15:.*]],a0,0x18 | 429 ; MIPS32: srl [[T17:.*]],a1,0x18 |
300 ; MIPS32: andi [[T15]],[[T15]],0x1 | 430 ; MIPS32: andi [[T17]],[[T17]],0x1 |
301 ; MIPS32: srl [[T0]],[[T0]],0x18 | 431 ; MIPS32: srl [[T7]],[[T7]],0x18 |
302 ; MIPS32: andi [[T0]],[[T0]],0x1 | 432 ; MIPS32: andi [[T7]],[[T7]],0x1 |
303 ; MIPS32: srl [[T4]],[[T4]],0x18 | 433 ; MIPS32: srl [[T11]],[[T11]],0x18 |
304 ; MIPS32: andi [[T4]],[[T4]],0x1 | 434 ; MIPS32: andi [[T11]],[[T11]],0x1 |
305 ; MIPS32: movn [[T4]],[[T0]],[[T15]] | 435 ; MIPS32: movn [[T11]],[[T7]],[[T17]] |
306 ; MIPS32: srl [[T4]],[[T4]],0x18 | 436 ; MIPS32: srl [[T11]],[[T11]],0x18 |
307 ; MIPS32: sll [[T14]],[[T14]],0x8 | 437 ; MIPS32: sll [[T14]],[[T14]],0x8 |
308 ; MIPS32: srl [[T14]],[[T14]],0x8 | 438 ; MIPS32: srl [[T14]],[[T14]],0x8 |
309 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] | 439 ; MIPS32: or [[T11]],[[T11]],[[T14]] |
310 ; MIPS32: andi [[T0]],a1,0xff | 440 ; MIPS32: move [[T6]],a2 |
311 ; MIPS32: andi [[T0]],[[T0]],0x1 | 441 ; MIPS32: andi [[T6]],[[T6]],0xff |
312 ; MIPS32: andi [[T15]],[[T1]],0xff | 442 ; MIPS32: andi [[T6]],[[T6]],0x1 |
313 ; MIPS32: andi [[T15]],[[T15]],0x1 | 443 ; MIPS32: move [[T7]],[[T8]] |
314 ; MIPS32: andi [[T8]],[[T5]],0xff | 444 ; MIPS32: andi [[T7]],[[T7]],0xff |
| 445 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 446 ; MIPS32: move [[T16]],[[T12]] |
| 447 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 448 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 449 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 450 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 451 ; MIPS32: srl [[T5]],[[T5]],0x8 |
| 452 ; MIPS32: sll [[T5]],[[T5]],0x8 |
| 453 ; MIPS32: or [[T16]],[[T16]],[[T5]] |
| 454 ; MIPS32: move [[T6]],a2 |
| 455 ; MIPS32: srl [[T6]],[[T6]],0x8 |
| 456 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 457 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 458 ; MIPS32: move [[T7]],[[T8]] |
| 459 ; MIPS32: srl [[T7]],[[T7]],0x8 |
| 460 ; MIPS32: andi [[T7]],[[T7]],0xff |
| 461 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 462 ; MIPS32: move [[T17]],[[T12]] |
| 463 ; MIPS32: srl [[T17]],[[T17]],0x8 |
| 464 ; MIPS32: andi [[T17]],[[T17]],0xff |
| 465 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 466 ; MIPS32: movn [[T17]],[[T7]],[[T6]] |
| 467 ; MIPS32: andi [[T17]],[[T17]],0xff |
| 468 ; MIPS32: sll [[T17]],[[T17]],0x8 |
| 469 ; MIPS32: lui [[T6]],0xffff |
| 470 ; MIPS32: ori [[T6]],[[T6]],0xff |
| 471 ; MIPS32: and [[T16]],[[T16]],[[T6]] |
| 472 ; MIPS32: or [[T17]],[[T17]],[[T16]] |
| 473 ; MIPS32: move [[T6]],a2 |
| 474 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 475 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 476 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 477 ; MIPS32: move [[T7]],[[T8]] |
| 478 ; MIPS32: srl [[T7]],[[T7]],0x10 |
| 479 ; MIPS32: andi [[T7]],[[T7]],0xff |
| 480 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 481 ; MIPS32: move [[T16]],[[T12]] |
| 482 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 483 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 484 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 485 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 486 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 487 ; MIPS32: sll [[T16]],[[T16]],0x10 |
| 488 ; MIPS32: lui [[T6]],0xff00 |
| 489 ; MIPS32: ori [[T6]],[[T6]],0xffff |
| 490 ; MIPS32: and [[T17]],[[T17]],[[T6]] |
| 491 ; MIPS32: or [[T16]],[[T16]],[[T17]] |
| 492 ; MIPS32: srl [[T18:.*]],a2,0x18 |
| 493 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 494 ; MIPS32: srl [[T8]],[[T8]],0x18 |
315 ; MIPS32: andi [[T8]],[[T8]],0x1 | 495 ; MIPS32: andi [[T8]],[[T8]],0x1 |
316 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | 496 ; MIPS32: srl [[T12]],[[T12]],0x18 |
317 ; MIPS32: andi [[T8]],[[T8]],0xff | 497 ; MIPS32: andi [[T12]],[[T12]],0x1 |
318 ; MIPS32: srl [[T9]],[[T9]],0x8 | 498 ; MIPS32: movn [[T12]],[[T8]],[[T18]] |
319 ; MIPS32: sll [[T9]],[[T9]],0x8 | 499 ; MIPS32: srl [[T12]],[[T12]],0x18 |
320 ; MIPS32: or [[T8]],[[T8]],[[T9]] | 500 ; MIPS32: sll [[T16]],[[T16]],0x8 |
321 ; MIPS32: srl [[T0]],a1,0x8 | 501 ; MIPS32: srl [[T16]],[[T16]],0x8 |
322 ; MIPS32: andi [[T0]],[[T0]],0xff | 502 ; MIPS32: or [[T12]],[[T12]],[[T16]] |
323 ; MIPS32: andi [[T0]],[[T0]],0x1 | 503 ; MIPS32: move [[T6]],a3 |
324 ; MIPS32: srl [[T15]],[[T1]],0x8 | 504 ; MIPS32: andi [[T6]],[[T6]],0xff |
325 ; MIPS32: andi [[T15]],[[T15]],0xff | 505 ; MIPS32: andi [[T6]],[[T6]],0x1 |
326 ; MIPS32: andi [[T15]],[[T15]],0x1 | 506 ; MIPS32: move [[T7]],[[T9]] |
327 ; MIPS32: srl [[T9]],[[T5]],0x8 | 507 ; MIPS32: andi [[T7]],[[T7]],0xff |
328 ; MIPS32: andi [[T9]],[[T9]],0xff | 508 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 509 ; MIPS32: move [[T16]],[[T13]] |
| 510 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 511 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 512 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 513 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 514 ; MIPS32: srl [[T4]],[[T4]],0x8 |
| 515 ; MIPS32: sll [[T4]],[[T4]],0x8 |
| 516 ; MIPS32: or [[T16]],[[T16]],[[T4]] |
| 517 ; MIPS32: move [[T6]],a3 |
| 518 ; MIPS32: srl [[T6]],[[T6]],0x8 |
| 519 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 520 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 521 ; MIPS32: move [[T7]],[[T9]] |
| 522 ; MIPS32: srl [[T7]],[[T7]],0x8 |
| 523 ; MIPS32: andi [[T7]],[[T7]],0xff |
| 524 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 525 ; MIPS32: move [[T17]],[[T13]] |
| 526 ; MIPS32: srl [[T17]],[[T17]],0x8 |
| 527 ; MIPS32: andi [[T17]],[[T17]],0xff |
| 528 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 529 ; MIPS32: movn [[T17]],[[T7]],[[T6]] |
| 530 ; MIPS32: andi [[T17]],[[T17]],0xff |
| 531 ; MIPS32: sll [[T17]],[[T17]],0x8 |
| 532 ; MIPS32: lui [[T6]],0xffff |
| 533 ; MIPS32: ori [[T6]],[[T6]],0xff |
| 534 ; MIPS32: and [[T16]],[[T16]],[[T6]] |
| 535 ; MIPS32: or [[T17]],[[T17]],[[T16]] |
| 536 ; MIPS32: move [[T6]],a3 |
| 537 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 538 ; MIPS32: andi [[T6]],[[T6]],0xff |
| 539 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 540 ; MIPS32: move [[T7]],[[T9]] |
| 541 ; MIPS32: srl [[T7]],[[T7]],0x10 |
| 542 ; MIPS32: andi [[T7]],[[T7]],0xff |
| 543 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 544 ; MIPS32: move [[T16]],[[T13]] |
| 545 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 546 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 547 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 548 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 549 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 550 ; MIPS32: sll [[T16]],[[T16]],0x10 |
| 551 ; MIPS32: lui [[T6]],0xff00 |
| 552 ; MIPS32: ori [[T6]],[[T6]],0xffff |
| 553 ; MIPS32: and [[T17]],[[T17]],[[T6]] |
| 554 ; MIPS32: or [[T16]],[[T16]],[[T17]] |
| 555 ; MIPS32: srl [[T19:.*]],a3,0x18 |
| 556 ; MIPS32: andi [[T19]],[[T19]],0x1 |
| 557 ; MIPS32: srl [[T9]],[[T9]],0x18 |
329 ; MIPS32: andi [[T9]],[[T9]],0x1 | 558 ; MIPS32: andi [[T9]],[[T9]],0x1 |
330 ; MIPS32: movn [[T9]],[[T15]],[[T0]] | 559 ; MIPS32: srl [[T13]],[[T13]],0x18 |
331 ; MIPS32: andi [[T9]],[[T9]],0xff | 560 ; MIPS32: andi [[T13]],[[T13]],0x1 |
332 ; MIPS32: sll [[T9]],[[T9]],0x8 | 561 ; MIPS32: movn [[T13]],[[T9]],[[T19]] |
333 ; MIPS32: lui [[T0]],0xffff | 562 ; MIPS32: srl [[T13]],[[T13]],0x18 |
334 ; MIPS32: ori [[T0]],[[T0]],0xff | |
335 ; MIPS32: and [[T8]],[[T8]],[[T0]] | |
336 ; MIPS32: or [[T9]],[[T9]],[[T8]] | |
337 ; MIPS32: srl [[T0]],a1,0x10 | |
338 ; MIPS32: andi [[T0]],[[T0]],0xff | |
339 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
340 ; MIPS32: srl [[T15]],[[T1]],0x10 | |
341 ; MIPS32: andi [[T15]],[[T15]],0xff | |
342 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
343 ; MIPS32: srl [[T8]],[[T5]],0x10 | |
344 ; MIPS32: andi [[T8]],[[T8]],0xff | |
345 ; MIPS32: andi [[T8]],[[T8]],0x1 | |
346 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | |
347 ; MIPS32: andi [[T8]],[[T8]],0xff | |
348 ; MIPS32: sll [[T8]],[[T8]],0x10 | |
349 ; MIPS32: lui [[T0]],0xff00 | |
350 ; MIPS32: ori [[T0]],[[T0]],0xffff | |
351 ; MIPS32: and [[T9]],[[T9]],[[T0]] | |
352 ; MIPS32: or [[T8]],[[T8]],[[T9]] | |
353 ; MIPS32: srl [[T16:.*]],a1,0x18 | |
354 ; MIPS32: andi [[T16]],[[T16]],0x1 | |
355 ; MIPS32: srl [[T1]],[[T1]],0x18 | |
356 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
357 ; MIPS32: srl [[T5]],[[T5]],0x18 | |
358 ; MIPS32: andi [[T5]],[[T5]],0x1 | |
359 ; MIPS32: movn [[T5]],[[T1]],[[T16]] | |
360 ; MIPS32: srl [[T5]],[[T5]],0x18 | |
361 ; MIPS32: sll [[T8]],[[T8]],0x8 | |
362 ; MIPS32: srl [[T8]],[[T8]],0x8 | |
363 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] | |
364 ; MIPS32: andi [[T0]],a2,0xff | |
365 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
366 ; MIPS32: andi [[T1]],[[T2]],0xff | |
367 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
368 ; MIPS32: andi [[T15]],[[T6]],0xff | |
369 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
370 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
371 ; MIPS32: andi [[T15]],[[T15]],0xff | |
372 ; MIPS32: srl [[T10]],[[T10]],0x8 | |
373 ; MIPS32: sll [[T10]],[[T10]],0x8 | |
374 ; MIPS32: or [[T15]],[[T15]],[[T10]] | |
375 ; MIPS32: srl [[T0]],a2,0x8 | |
376 ; MIPS32: andi [[T0]],[[T0]],0xff | |
377 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
378 ; MIPS32: srl [[T1]],[[T2]],0x8 | |
379 ; MIPS32: andi [[T1]],[[T1]],0xff | |
380 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
381 ; MIPS32: srl [[T16]],[[T6]],0x8 | |
382 ; MIPS32: andi [[T16]],[[T16]],0xff | |
383 ; MIPS32: andi [[T16]],[[T16]],0x1 | |
384 ; MIPS32: movn [[T16]],[[T1]],[[T0]] | |
385 ; MIPS32: andi [[T16]],[[T16]],0xff | |
386 ; MIPS32: sll [[T16]],[[T16]],0x8 | 563 ; MIPS32: sll [[T16]],[[T16]],0x8 |
387 ; MIPS32: lui [[T0]],0xffff | 564 ; MIPS32: srl [[T16]],[[T16]],0x8 |
388 ; MIPS32: ori [[T0]],[[T0]],0xff | 565 ; MIPS32: or [[T13]],[[T13]],[[T16]] |
389 ; MIPS32: and [[T15]],[[T15]],[[T0]] | 566 ; MIPS32: move v0,[[T10]] |
390 ; MIPS32: or [[T16]],[[T16]],[[T15]] | 567 ; MIPS32: move v1,[[T11]] |
391 ; MIPS32: srl [[T0]],a2,0x10 | 568 ; MIPS32: move a0,[[T12]] |
392 ; MIPS32: andi [[T0]],[[T0]],0xff | 569 ; MIPS32: move a1,[[T13]] |
393 ; MIPS32: andi [[T0]],[[T0]],0x1 | 570 ; MIPS32: lw [[T5]], |
394 ; MIPS32: srl [[T1]],[[T2]],0x10 | 571 ; MIPS32: lw [[T4]], |
395 ; MIPS32: andi [[T1]],[[T1]],0xff | 572 ; MIPS32: lw [[T3]], |
396 ; MIPS32: andi [[T1]],[[T1]],0x1 | 573 ; MIPS32: lw [[T2]], |
397 ; MIPS32: srl [[T15]],[[T6]],0x10 | 574 ; MIPS32: lw [[T1]], |
398 ; MIPS32: andi [[T15]],[[T15]],0xff | 575 ; MIPS32: addiu [[T0]],sp,20 |
399 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
400 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
401 ; MIPS32: andi [[T15]],[[T15]],0xff | |
402 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
403 ; MIPS32: lui [[T0]],0xff00 | |
404 ; MIPS32: ori [[T0]],[[T0]],0xffff | |
405 ; MIPS32: and [[T16]],[[T16]],[[T0]] | |
406 ; MIPS32: or [[T15]],[[T15]],[[T16]] | |
407 ; MIPS32: srl [[T17:.*]],a2,0x18 | |
408 ; MIPS32: andi [[T17]],[[T17]],0x1 | |
409 ; MIPS32: srl [[T2]],[[T2]],0x18 | |
410 ; MIPS32: andi [[T2]],[[T2]],0x1 | |
411 ; MIPS32: srl [[T6]],[[T6]],0x18 | |
412 ; MIPS32: andi [[T6]],[[T6]],0x1 | |
413 ; MIPS32: movn [[T6]],[[T2]],[[T17]] | |
414 ; MIPS32: srl [[T6]],[[T6]],0x18 | |
415 ; MIPS32: sll [[T15]],[[T15]],0x8 | |
416 ; MIPS32: srl [[T15]],[[T15]],0x8 | |
417 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] | |
418 ; MIPS32: andi [[T0]],a3,0xff | |
419 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
420 ; MIPS32: andi [[T1]],[[T3]],0xff | |
421 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
422 ; MIPS32: andi [[T15]],[[T7]],0xff | |
423 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
424 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
425 ; MIPS32: andi [[T15]],[[T15]],0xff | |
426 ; MIPS32: srl [[T11]],[[T11]],0x8 | |
427 ; MIPS32: sll [[T11]],[[T11]],0x8 | |
428 ; MIPS32: or [[T15]],[[T15]],[[T11]] | |
429 ; MIPS32: srl [[T0]],a3,0x8 | |
430 ; MIPS32: andi [[T0]],[[T0]],0xff | |
431 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
432 ; MIPS32: srl [[T1]],[[T3]],0x8 | |
433 ; MIPS32: andi [[T1]],[[T1]],0xff | |
434 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
435 ; MIPS32: srl [[T16]],[[T7]],0x8 | |
436 ; MIPS32: andi [[T16]],[[T16]],0xff | |
437 ; MIPS32: andi [[T16]],[[T16]],0x1 | |
438 ; MIPS32: movn [[T16]],[[T1]],[[T0]] | |
439 ; MIPS32: andi [[T16]],[[T16]],0xff | |
440 ; MIPS32: sll [[T16]],[[T16]],0x8 | |
441 ; MIPS32: lui [[T0]],0xffff | |
442 ; MIPS32: ori [[T0]],[[T0]],0xff | |
443 ; MIPS32: and [[T15]],[[T15]],[[T0]] | |
444 ; MIPS32: or [[T16]],[[T16]],[[T15]] | |
445 ; MIPS32: srl [[T0]],a3,0x10 | |
446 ; MIPS32: andi [[T0]],[[T0]],0xff | |
447 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
448 ; MIPS32: srl [[T1]],[[T3]],0x10 | |
449 ; MIPS32: andi [[T1]],[[T1]],0xff | |
450 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
451 ; MIPS32: srl [[T15]],[[T7]],0x10 | |
452 ; MIPS32: andi [[T15]],[[T15]],0xff | |
453 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
454 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
455 ; MIPS32: andi [[T15]],[[T15]],0xff | |
456 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
457 ; MIPS32: lui [[T0]],0xff00 | |
458 ; MIPS32: ori [[T0]],[[T0]],0xffff | |
459 ; MIPS32: and [[T16]],[[T16]],[[T0]] | |
460 ; MIPS32: or [[T15]],[[T15]],[[T16]] | |
461 ; MIPS32: srl [[T18:.*]],a3,0x18 | |
462 ; MIPS32: andi [[T18]],[[T18]],0x1 | |
463 ; MIPS32: srl [[T3]],[[T3]],0x18 | |
464 ; MIPS32: andi [[T3]],[[T3]],0x1 | |
465 ; MIPS32: srl [[T7]],[[T7]],0x18 | |
466 ; MIPS32: andi [[T7]],[[T7]],0x1 | |
467 ; MIPS32: movn [[T7]],[[T3]],[[T18]] | |
468 ; MIPS32: srl [[T7]],[[T7]],0x18 | |
469 ; MIPS32: sll [[T15]],[[T15]],0x8 | |
470 ; MIPS32: srl [[T15]],[[T15]],0x8 | |
471 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] | |
472 } | 576 } |
473 | 577 |
474 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, | 578 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, |
475 <8 x i16> %arg2) { | 579 <8 x i16> %arg2) { |
476 entry: | 580 entry: |
477 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 | 581 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 |
478 ret <8 x i16> %res | 582 ret <8 x i16> %res |
479 ; CHECK-LABEL: test_select_v8i16 | 583 ; CHECK-LABEL: test_select_v8i16 |
480 ; CHECK: pand | 584 ; CHECK: pand |
481 ; CHECK: pandn | 585 ; CHECK: pandn |
482 ; CHECK: por | 586 ; CHECK: por |
483 | 587 |
484 ; SSE41-LABEL: test_select_v8i16 | 588 ; SSE41-LABEL: test_select_v8i16 |
485 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 589 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
486 | 590 |
487 ; MIPS32-LABEL: test_select_v8i16 | 591 ; MIPS32-LABEL: test_select_v8i16 |
488 ; MIPS32: lw [[T0:.*]],36(sp) | 592 ; MIPS32: addiu [[T0:.*]],sp,-20 |
489 ; MIPS32: lw [[T1:.*]],40(sp) | 593 ; MIPS32: sw [[T1:.*]], |
490 ; MIPS32: lw [[T2:.*]],44(sp) | 594 ; MIPS32: sw [[T2:.*]], |
491 ; MIPS32: lw [[T3:.*]],48(sp) | 595 ; MIPS32: sw [[T3:.*]], |
492 ; MIPS32: lw [[T4:.*]],52(sp) | 596 ; MIPS32: sw [[T4:.*]], |
493 ; MIPS32: lw [[T5:.*]],56(sp) | 597 ; MIPS32: sw [[T5:.*]], |
494 ; MIPS32: lw [[T6:.*]],60(sp) | 598 ; MIPS32: lw [[T6:.*]], |
495 ; MIPS32: lw [[T7:.*]],64(sp) | 599 ; MIPS32: lw [[T7:.*]], |
496 ; MIPS32: move [[T8:.*]],zero | 600 ; MIPS32: lw [[T8:.*]], |
497 ; MIPS32: move [[T9:.*]],zero | 601 ; MIPS32: lw [[T9:.*]], |
498 ; MIPS32: move [[T10:.*]],zero | 602 ; MIPS32: lw [[T10:.*]], |
499 ; MIPS32: move [[T11:.*]],zero | 603 ; MIPS32: lw [[T11:.*]], |
500 ; MIPS32: andi [[T12:.*]],a0,0xffff | 604 ; MIPS32: lw [[T12:.*]], |
501 ; MIPS32: andi [[T12]],[[T12]],0x1 | 605 ; MIPS32: lw [[T13:.*]], |
502 ; MIPS32: andi [[T13:.*]],[[T0]],0xffff | 606 ; MIPS32: move [[T14:.*]],zero |
503 ; MIPS32: andi [[T14:.*]],[[T4]],0xffff | 607 ; MIPS32: move [[T15:.*]],zero |
504 ; MIPS32: movn [[T14]],[[T13]],[[T12]] | 608 ; MIPS32: move [[T5]],zero |
| 609 ; MIPS32: move [[T4]],zero |
| 610 ; MIPS32: move [[T3]],a0 |
| 611 ; MIPS32: andi [[T3]],[[T3]],0xffff |
| 612 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 613 ; MIPS32: move [[T2]],[[T6]] |
| 614 ; MIPS32: andi [[T2]],[[T2]],0xffff |
| 615 ; MIPS32: move [[T1]],[[T10]] |
| 616 ; MIPS32: andi [[T1]],[[T1]],0xffff |
| 617 ; MIPS32: movn [[T1]],[[T2]],[[T3]] |
| 618 ; MIPS32: andi [[T1]],[[T1]],0xffff |
| 619 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 620 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 621 ; MIPS32: or [[T1]],[[T1]],[[T14]] |
| 622 ; MIPS32: srl [[T16:.*]],a0,0x10 |
| 623 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 624 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 625 ; MIPS32: srl [[T10]],[[T10]],0x10 |
| 626 ; MIPS32: movn [[T10]],[[T6]],[[T16]] |
| 627 ; MIPS32: sll [[T10]],[[T10]],0x10 |
| 628 ; MIPS32: sll [[T1]],[[T1]],0x10 |
| 629 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 630 ; MIPS32: or [[T10]],[[T10]],[[T1]] |
| 631 ; MIPS32: move [[T6]],a1 |
| 632 ; MIPS32: andi [[T6]],[[T6]],0xffff |
| 633 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 634 ; MIPS32: move [[T16]],[[T7]] |
| 635 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 636 ; MIPS32: move [[T14]],[[T11]] |
505 ; MIPS32: andi [[T14]],[[T14]],0xffff | 637 ; MIPS32: andi [[T14]],[[T14]],0xffff |
506 ; MIPS32: srl [[T8]],[[T8]],0x10 | 638 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
507 ; MIPS32: sll [[T8]],[[T8]],0x10 | 639 ; MIPS32: andi [[T14]],[[T14]],0xffff |
508 ; MIPS32: or [[T14]],[[T14]],[[T8]] | 640 ; MIPS32: srl [[T15]],[[T15]],0x10 |
509 ; MIPS32: srl [[T15:.*]],a0,0x10 | 641 ; MIPS32: sll [[T15]],[[T15]],0x10 |
510 ; MIPS32: andi [[T15]],[[T15]],0x1 | 642 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
511 ; MIPS32: srl [[T0]],[[T0]],0x10 | 643 ; MIPS32: srl [[T17:.*]],a1,0x10 |
512 ; MIPS32: srl [[T4]],[[T4]],0x10 | 644 ; MIPS32: andi [[T17]],[[T17]],0x1 |
513 ; MIPS32: movn [[T4]],[[T0]],[[T15]] | 645 ; MIPS32: srl [[T7]],[[T7]],0x10 |
514 ; MIPS32: sll [[T4]],[[T4]],0x10 | 646 ; MIPS32: srl [[T11]],[[T11]],0x10 |
| 647 ; MIPS32: movn [[T11]],[[T7]],[[T17]] |
| 648 ; MIPS32: sll [[T11]],[[T11]],0x10 |
515 ; MIPS32: sll [[T14]],[[T14]],0x10 | 649 ; MIPS32: sll [[T14]],[[T14]],0x10 |
516 ; MIPS32: srl [[T14]],[[T14]],0x10 | 650 ; MIPS32: srl [[T14]],[[T14]],0x10 |
517 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] | 651 ; MIPS32: or [[T11]],[[T11]],[[T14]] |
518 ; MIPS32: andi [[T0]],a1,0xffff | 652 ; MIPS32: move [[T6]],a2 |
519 ; MIPS32: andi [[T0]],[[T0]],0x1 | 653 ; MIPS32: andi [[T6]],[[T6]],0xffff |
520 ; MIPS32: andi [[T15]],[[T1]],0xffff | 654 ; MIPS32: andi [[T6]],[[T6]],0x1 |
521 ; MIPS32: andi [[T8]],[[T5]],0xffff | 655 ; MIPS32: move [[T7]],[[T8]] |
522 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | 656 ; MIPS32: andi [[T7]],[[T7]],0xffff |
523 ; MIPS32: andi [[T8]],[[T8]],0xffff | 657 ; MIPS32: move [[T16]],[[T12]] |
| 658 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 659 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 660 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 661 ; MIPS32: srl [[T5]],[[T5]],0x10 |
| 662 ; MIPS32: sll [[T5]],[[T5]],0x10 |
| 663 ; MIPS32: or [[T16]],[[T16]],[[T5]] |
| 664 ; MIPS32: srl [[T18:.*]],a2,0x10 |
| 665 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 666 ; MIPS32: srl [[T8]],[[T8]],0x10 |
| 667 ; MIPS32: srl [[T12]],[[T12]],0x10 |
| 668 ; MIPS32: movn [[T12]],[[T8]],[[T18]] |
| 669 ; MIPS32: sll [[T12]],[[T12]],0x10 |
| 670 ; MIPS32: sll [[T16]],[[T16]],0x10 |
| 671 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 672 ; MIPS32: or [[T12]],[[T12]],[[T16]] |
| 673 ; MIPS32: move [[T6]],a3 |
| 674 ; MIPS32: andi [[T6]],[[T6]],0xffff |
| 675 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 676 ; MIPS32: move [[T7]],[[T9]] |
| 677 ; MIPS32: andi [[T7]],[[T7]],0xffff |
| 678 ; MIPS32: move [[T16]],[[T13]] |
| 679 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 680 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 681 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 682 ; MIPS32: srl [[T4]],[[T4]],0x10 |
| 683 ; MIPS32: sll [[T4]],[[T4]],0x10 |
| 684 ; MIPS32: or [[T16]],[[T16]],[[T4]] |
| 685 ; MIPS32: srl [[T19:.*]],a3,0x10 |
| 686 ; MIPS32: andi [[T19]],[[T19]],0x1 |
524 ; MIPS32: srl [[T9]],[[T9]],0x10 | 687 ; MIPS32: srl [[T9]],[[T9]],0x10 |
525 ; MIPS32: sll [[T9]],[[T9]],0x10 | 688 ; MIPS32: srl [[T13]],[[T13]],0x10 |
526 ; MIPS32: or [[T8]],[[T8]],[[T9]] | 689 ; MIPS32: movn [[T13]],[[T9]],[[T19]] |
527 ; MIPS32: srl [[T16:.*]],a1,0x10 | 690 ; MIPS32: sll [[T13]],[[T13]],0x10 |
528 ; MIPS32: andi [[T16]],[[T16]],0x1 | 691 ; MIPS32: sll [[T16]],[[T16]],0x10 |
529 ; MIPS32: srl [[T1]],[[T1]],0x10 | 692 ; MIPS32: srl [[T16]],[[T16]],0x10 |
530 ; MIPS32: srl [[T5]],[[T5]],0x10 | 693 ; MIPS32: or [[T13]],[[T13]],[[T16]] |
531 ; MIPS32: movn [[T5]],[[T1]],[[T16]] | 694 ; MIPS32: move v0,[[T10]] |
532 ; MIPS32: sll [[T5]],[[T5]],0x10 | 695 ; MIPS32: move v1,[[T11]] |
533 ; MIPS32: sll [[T8]],[[T8]],0x10 | 696 ; MIPS32: move a0,[[T12]] |
534 ; MIPS32: srl [[T8]],[[T8]],0x10 | 697 ; MIPS32: move a1,[[T13]] |
535 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] | 698 ; MIPS32: lw [[T5]], |
536 ; MIPS32: andi [[T0]],a2,0xffff | 699 ; MIPS32: lw [[T4]], |
537 ; MIPS32: andi [[T0]],[[T0]],0x1 | 700 ; MIPS32: lw [[T3]], |
538 ; MIPS32: andi [[T1]],[[T2]],0xffff | 701 ; MIPS32: lw [[T2]], |
539 ; MIPS32: andi [[T15]],[[T6]],0xffff | 702 ; MIPS32: lw [[T1]], |
540 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | 703 ; MIPS32: addiu [[T0]],sp,20 |
541 ; MIPS32: andi [[T15]],[[T15]],0xffff | |
542 ; MIPS32: srl [[T10]],[[T10]],0x10 | |
543 ; MIPS32: sll [[T10]],[[T10]],0x10 | |
544 ; MIPS32: or [[T15]],[[T15]],[[T10]] | |
545 ; MIPS32: srl [[T17:.*]],a2,0x10 | |
546 ; MIPS32: andi [[T17]],[[T17]],0x1 | |
547 ; MIPS32: srl [[T2]],[[T2]],0x10 | |
548 ; MIPS32: srl [[T6]],[[T6]],0x10 | |
549 ; MIPS32: movn [[T6]],[[T2]],[[T17]] | |
550 ; MIPS32: sll [[T6]],[[T6]],0x10 | |
551 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
552 ; MIPS32: srl [[T15]],[[T15]],0x10 | |
553 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] | |
554 ; MIPS32: andi [[T0]],a3,0xffff | |
555 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
556 ; MIPS32: andi [[T1]],[[T3]],0xffff | |
557 ; MIPS32: andi [[T15]],[[T7]],0xffff | |
558 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
559 ; MIPS32: andi [[T15]],[[T15]],0xffff | |
560 ; MIPS32: srl [[T11]],[[T11]],0x10 | |
561 ; MIPS32: sll [[T11]],[[T11]],0x10 | |
562 ; MIPS32: or [[T15]],[[T15]],[[T11]] | |
563 ; MIPS32: srl [[T18:.*]],a3,0x10 | |
564 ; MIPS32: andi [[T18]],[[T18]],0x1 | |
565 ; MIPS32: srl [[T3]],[[T3]],0x10 | |
566 ; MIPS32: srl [[T7]],[[T7]],0x10 | |
567 ; MIPS32: movn [[T7]],[[T3]],[[T18]] | |
568 ; MIPS32: sll [[T7]],[[T7]],0x10 | |
569 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
570 ; MIPS32: srl [[T15]],[[T15]],0x10 | |
571 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] | |
572 } | 704 } |
573 | 705 |
574 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, | 706 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, |
575 <8 x i1> %arg2) { | 707 <8 x i1> %arg2) { |
576 entry: | 708 entry: |
577 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 | 709 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 |
578 ret <8 x i1> %res | 710 ret <8 x i1> %res |
579 ; CHECK-LABEL: test_select_v8i1 | 711 ; CHECK-LABEL: test_select_v8i1 |
580 ; CHECK: pand | 712 ; CHECK: pand |
581 ; CHECK: pandn | 713 ; CHECK: pandn |
582 ; CHECK: por | 714 ; CHECK: por |
583 | 715 |
584 ; SSE41-LABEL: test_select_v8i1 | 716 ; SSE41-LABEL: test_select_v8i1 |
585 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 717 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
586 | 718 |
587 ; MIPS32-LABEL: test_select_v8i1 | 719 ; MIPS32-LABEL: test_select_v8i1 |
588 ; MIPS32: lw [[T0:.*]],36(sp) | 720 ; MIPS32: addiu [[T0:.*]],sp,-20 |
589 ; MIPS32: lw [[T1:.*]],40(sp) | 721 ; MIPS32: sw [[T1:.*]], |
590 ; MIPS32: lw [[T2:.*]],44(sp) | 722 ; MIPS32: sw [[T2:.*]], |
591 ; MIPS32: lw [[T3:.*]],48(sp) | 723 ; MIPS32: sw [[T3:.*]], |
592 ; MIPS32: lw [[T4:.*]],52(sp) | 724 ; MIPS32: sw [[T4:.*]], |
593 ; MIPS32: lw [[T5:.*]],56(sp) | 725 ; MIPS32: sw [[T5:.*]], |
594 ; MIPS32: lw [[T6:.*]],60(sp) | 726 ; MIPS32: lw [[T6:.*]], |
595 ; MIPS32: lw [[T7:.*]],64(sp) | 727 ; MIPS32: lw [[T7:.*]], |
596 ; MIPS32: move [[T8:.*]],zero | 728 ; MIPS32: lw [[T8:.*]], |
597 ; MIPS32: move [[T9:.*]],zero | 729 ; MIPS32: lw [[T9:.*]], |
598 ; MIPS32: move [[T10:.*]],zero | 730 ; MIPS32: lw [[T10:.*]], |
599 ; MIPS32: move [[T11:.*]],zero | 731 ; MIPS32: lw [[T11:.*]], |
600 ; MIPS32: andi [[T12:.*]],a0,0xffff | 732 ; MIPS32: lw [[T12:.*]], |
601 ; MIPS32: andi [[T12]],[[T12]],0x1 | 733 ; MIPS32: lw [[T13:.*]], |
602 ; MIPS32: andi [[T13:.*]],[[T0]],0xffff | 734 ; MIPS32: move [[T14:.*]],zero |
603 ; MIPS32: andi [[T13]],[[T13]],0x1 | 735 ; MIPS32: move [[T15:.*]],zero |
604 ; MIPS32: andi [[T14:.*]],[[T4]],0xffff | 736 ; MIPS32: move [[T5]],zero |
| 737 ; MIPS32: move [[T4]],zero |
| 738 ; MIPS32: move [[T3]],a0 |
| 739 ; MIPS32: andi [[T3]],[[T3]],0xffff |
| 740 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 741 ; MIPS32: move [[T2]],[[T6]] |
| 742 ; MIPS32: andi [[T2]],[[T2]],0xffff |
| 743 ; MIPS32: andi [[T2]],[[T2]],0x1 |
| 744 ; MIPS32: move [[T1]],[[T10]] |
| 745 ; MIPS32: andi [[T1]],[[T1]],0xffff |
| 746 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 747 ; MIPS32: movn [[T1]],[[T2]],[[T3]] |
| 748 ; MIPS32: andi [[T1]],[[T1]],0xffff |
| 749 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 750 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 751 ; MIPS32: or [[T1]],[[T1]],[[T14]] |
| 752 ; MIPS32: srl [[T16:.*]],a0,0x10 |
| 753 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 754 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 755 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 756 ; MIPS32: srl [[T10]],[[T10]],0x10 |
| 757 ; MIPS32: andi [[T10]],[[T10]],0x1 |
| 758 ; MIPS32: movn [[T10]],[[T6]],[[T16]] |
| 759 ; MIPS32: sll [[T10]],[[T10]],0x10 |
| 760 ; MIPS32: sll [[T1]],[[T1]],0x10 |
| 761 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 762 ; MIPS32: or [[T10]],[[T10]],[[T1]] |
| 763 ; MIPS32: move [[T6]],a1 |
| 764 ; MIPS32: andi [[T6]],[[T6]],0xffff |
| 765 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 766 ; MIPS32: move [[T16]],[[T7]] |
| 767 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 768 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 769 ; MIPS32: move [[T14]],[[T11]] |
| 770 ; MIPS32: andi [[T14]],[[T14]],0xffff |
605 ; MIPS32: andi [[T14]],[[T14]],0x1 | 771 ; MIPS32: andi [[T14]],[[T14]],0x1 |
606 ; MIPS32: movn [[T14]],[[T13]],[[T12]] | 772 ; MIPS32: movn [[T14]],[[T16]],[[T6]] |
607 ; MIPS32: andi [[T14]],[[T14]],0xffff | 773 ; MIPS32: andi [[T14]],[[T14]],0xffff |
608 ; MIPS32: srl [[T8]],[[T8]],0x10 | 774 ; MIPS32: srl [[T15]],[[T15]],0x10 |
609 ; MIPS32: sll [[T8]],[[T8]],0x10 | 775 ; MIPS32: sll [[T15]],[[T15]],0x10 |
610 ; MIPS32: or [[T14]],[[T14]],[[T8]] | 776 ; MIPS32: or [[T14]],[[T14]],[[T15]] |
611 ; MIPS32: srl [[T15:.*]],a0,0x10 | 777 ; MIPS32: srl [[T17:.*]],a1,0x10 |
612 ; MIPS32: andi [[T15]],[[T15]],0x1 | 778 ; MIPS32: andi [[T17]],[[T17]],0x1 |
613 ; MIPS32: srl [[T0]],[[T0]],0x10 | 779 ; MIPS32: srl [[T7]],[[T7]],0x10 |
614 ; MIPS32: andi [[T0]],[[T0]],0x1 | 780 ; MIPS32: andi [[T7]],[[T7]],0x1 |
615 ; MIPS32: srl [[T4]],[[T4]],0x10 | 781 ; MIPS32: srl [[T11]],[[T11]],0x10 |
616 ; MIPS32: andi [[T4]],[[T4]],0x1 | 782 ; MIPS32: andi [[T11]],[[T11]],0x1 |
617 ; MIPS32: movn [[T4]],[[T0]],[[T15]] | 783 ; MIPS32: movn [[T11]],[[T7]],[[T17]] |
618 ; MIPS32: sll [[T4]],[[T4]],0x10 | 784 ; MIPS32: sll [[T11]],[[T11]],0x10 |
619 ; MIPS32: sll [[T14]],[[T14]],0x10 | 785 ; MIPS32: sll [[T14]],[[T14]],0x10 |
620 ; MIPS32: srl [[T14]],[[T14]],0x10 | 786 ; MIPS32: srl [[T14]],[[T14]],0x10 |
621 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] | 787 ; MIPS32: or [[T11]],[[T11]],[[T14]] |
622 ; MIPS32: andi [[T0]],a1,0xffff | 788 ; MIPS32: move [[T6]],a2 |
623 ; MIPS32: andi [[T0]],[[T0]],0x1 | 789 ; MIPS32: andi [[T6]],[[T6]],0xffff |
624 ; MIPS32: andi [[T15]],[[T1]],0xffff | 790 ; MIPS32: andi [[T6]],[[T6]],0x1 |
625 ; MIPS32: andi [[T15]],[[T15]],0x1 | 791 ; MIPS32: move [[T7]],[[T8]] |
626 ; MIPS32: andi [[T8]],[[T5]],0xffff | 792 ; MIPS32: andi [[T7]],[[T7]],0xffff |
| 793 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 794 ; MIPS32: move [[T16]],[[T12]] |
| 795 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 796 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 797 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 798 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 799 ; MIPS32: srl [[T5]],[[T5]],0x10 |
| 800 ; MIPS32: sll [[T5]],[[T5]],0x10 |
| 801 ; MIPS32: or [[T16]],[[T16]],[[T5]] |
| 802 ; MIPS32: srl [[T18:.*]],a2,0x10 |
| 803 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 804 ; MIPS32: srl [[T8]],[[T8]],0x10 |
627 ; MIPS32: andi [[T8]],[[T8]],0x1 | 805 ; MIPS32: andi [[T8]],[[T8]],0x1 |
628 ; MIPS32: movn [[T8]],[[T15]],[[T0]] | 806 ; MIPS32: srl [[T12]],[[T12]],0x10 |
629 ; MIPS32: andi [[T8]],[[T8]],0xffff | 807 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 808 ; MIPS32: movn [[T12]],[[T8]],[[T18]] |
| 809 ; MIPS32: sll [[T12]],[[T12]],0x10 |
| 810 ; MIPS32: sll [[T16]],[[T16]],0x10 |
| 811 ; MIPS32: srl [[T16]],[[T16]],0x10 |
| 812 ; MIPS32: or [[T12]],[[T12]],[[T16]] |
| 813 ; MIPS32: move [[T6]],a3 |
| 814 ; MIPS32: andi [[T6]],[[T6]],0xffff |
| 815 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 816 ; MIPS32: move [[T7]],[[T9]] |
| 817 ; MIPS32: andi [[T7]],[[T7]],0xffff |
| 818 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 819 ; MIPS32: move [[T16]],[[T13]] |
| 820 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 821 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 822 ; MIPS32: movn [[T16]],[[T7]],[[T6]] |
| 823 ; MIPS32: andi [[T16]],[[T16]],0xffff |
| 824 ; MIPS32: srl [[T4]],[[T4]],0x10 |
| 825 ; MIPS32: sll [[T4]],[[T4]],0x10 |
| 826 ; MIPS32: or [[T16]],[[T16]],[[T4]] |
| 827 ; MIPS32: srl [[T19:.*]],a3,0x10 |
| 828 ; MIPS32: andi [[T19]],[[T19]],0x1 |
630 ; MIPS32: srl [[T9]],[[T9]],0x10 | 829 ; MIPS32: srl [[T9]],[[T9]],0x10 |
631 ; MIPS32: sll [[T9]],[[T9]],0x10 | 830 ; MIPS32: andi [[T9]],[[T9]],0x1 |
632 ; MIPS32: or [[T8]],[[T8]],[[T9]] | 831 ; MIPS32: srl [[T13]],[[T13]],0x10 |
633 ; MIPS32: srl [[T16:.*]],a1,0x10 | 832 ; MIPS32: andi [[T13]],[[T13]],0x1 |
634 ; MIPS32: andi [[T16]],[[T16]],0x1 | 833 ; MIPS32: movn [[T13]],[[T9]],[[T19]] |
635 ; MIPS32: srl [[T1]],[[T1]],0x10 | 834 ; MIPS32: sll [[T13]],[[T13]],0x10 |
636 ; MIPS32: andi [[T1]],[[T1]],0x1 | 835 ; MIPS32: sll [[T16]],[[T16]],0x10 |
637 ; MIPS32: srl [[T5]],[[T5]],0x10 | 836 ; MIPS32: srl [[T16]],[[T16]],0x10 |
638 ; MIPS32: andi [[T5]],[[T5]],0x1 | 837 ; MIPS32: or [[T13]],[[T13]],[[T16]] |
639 ; MIPS32: movn [[T5]],[[T1]],[[T16]] | 838 ; MIPS32: move v0,[[T10]] |
640 ; MIPS32: sll [[T5]],[[T5]],0x10 | 839 ; MIPS32: move v1,[[T11]] |
641 ; MIPS32: sll [[T8]],[[T8]],0x10 | 840 ; MIPS32: move a0,[[T12]] |
642 ; MIPS32: srl [[T8]],[[T8]],0x10 | 841 ; MIPS32: move a1,[[T13]] |
643 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] | 842 ; MIPS32: lw [[T5]], |
644 ; MIPS32: andi [[T0]],a2,0xffff | 843 ; MIPS32: lw [[T4]], |
645 ; MIPS32: andi [[T0]],[[T0]],0x1 | 844 ; MIPS32: lw [[T3]], |
646 ; MIPS32: andi [[T1]],[[T2]],0xffff | 845 ; MIPS32: lw [[T2]], |
647 ; MIPS32: andi [[T1]],[[T1]],0x1 | 846 ; MIPS32: lw [[T1]], |
648 ; MIPS32: andi [[T15]],[[T6]],0xffff | 847 ; MIPS32: addiu [[T0]],sp,20 |
649 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
650 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
651 ; MIPS32: andi [[T15]],[[T15]],0xffff | |
652 ; MIPS32: srl [[T10]],[[T10]],0x10 | |
653 ; MIPS32: sll [[T10]],[[T10]],0x10 | |
654 ; MIPS32: or [[T15]],[[T15]],[[T10]] | |
655 ; MIPS32: srl [[T17:.*]],a2,0x10 | |
656 ; MIPS32: andi [[T17]],[[T17]],0x1 | |
657 ; MIPS32: srl [[T2]],[[T2]],0x10 | |
658 ; MIPS32: andi [[T2]],[[T2]],0x1 | |
659 ; MIPS32: srl [[T6]],[[T6]],0x10 | |
660 ; MIPS32: andi [[T6]],[[T6]],0x1 | |
661 ; MIPS32: movn [[T6]],[[T2]],[[T17]] | |
662 ; MIPS32: sll [[T6]],[[T6]],0x10 | |
663 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
664 ; MIPS32: srl [[T15]],[[T15]],0x10 | |
665 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] | |
666 ; MIPS32: andi [[T0]],a3,0xffff | |
667 ; MIPS32: andi [[T0]],[[T0]],0x1 | |
668 ; MIPS32: andi [[T1]],[[T3]],0xffff | |
669 ; MIPS32: andi [[T1]],[[T1]],0x1 | |
670 ; MIPS32: andi [[T15]],[[T7]],0xffff | |
671 ; MIPS32: andi [[T15]],[[T15]],0x1 | |
672 ; MIPS32: movn [[T15]],[[T1]],[[T0]] | |
673 ; MIPS32: andi [[T15]],[[T15]],0xffff | |
674 ; MIPS32: srl [[T11]],[[T11]],0x10 | |
675 ; MIPS32: sll [[T11]],[[T11]],0x10 | |
676 ; MIPS32: or [[T15]],[[T15]],[[T11]] | |
677 ; MIPS32: srl [[T18:.*]],a3,0x10 | |
678 ; MIPS32: andi [[T18]],[[T18]],0x1 | |
679 ; MIPS32: srl [[T3]],[[T3]],0x10 | |
680 ; MIPS32: andi [[T3]],[[T3]],0x1 | |
681 ; MIPS32: srl [[T7]],[[T7]],0x10 | |
682 ; MIPS32: andi [[T7]],[[T7]],0x1 | |
683 ; MIPS32: movn [[T7]],[[T3]],[[T18]] | |
684 ; MIPS32: sll [[T7]],[[T7]],0x10 | |
685 ; MIPS32: sll [[T15]],[[T15]],0x10 | |
686 ; MIPS32: srl [[T15]],[[T15]],0x10 | |
687 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] | |
688 } | 848 } |
689 | 849 |
690 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, | 850 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, |
691 <4 x i32> %arg2) { | 851 <4 x i32> %arg2) { |
692 entry: | 852 entry: |
693 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 | 853 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 |
694 ret <4 x i32> %res | 854 ret <4 x i32> %res |
695 ; CHECK-LABEL: test_select_v4i32 | 855 ; CHECK-LABEL: test_select_v4i32 |
696 ; CHECK: pand | 856 ; CHECK: pand |
697 ; CHECK: pandn | 857 ; CHECK: pandn |
698 ; CHECK: por | 858 ; CHECK: por |
699 | 859 |
700 ; SSE41-LABEL: test_select_v4i32 | 860 ; SSE41-LABEL: test_select_v4i32 |
701 ; SSE41: pslld xmm0,0x1f | 861 ; SSE41: pslld xmm0,0x1f |
702 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 862 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
703 | 863 |
704 ; MIPS32-LABEL: test_select_v4i32 | 864 ; MIPS32-LABEL: test_select_v4i32 |
705 ; MIPS32: lw [[T0:.*]],16(sp) | 865 ; MIPS32: lw [[T0:.*]], |
706 ; MIPS32: lw [[T1:.*]],20(sp) | 866 ; MIPS32: lw [[T1:.*]], |
707 ; MIPS32: lw [[T2:.*]],24(sp) | 867 ; MIPS32: lw [[T2:.*]], |
708 ; MIPS32: lw [[T3:.*]],28(sp) | 868 ; MIPS32: lw [[T3:.*]], |
709 ; MIPS32: lw [[T4:.*]],32(sp) | 869 ; MIPS32: lw [[T4:.*]], |
710 ; MIPS32: lw [[T5:.*]],36(sp) | 870 ; MIPS32: lw [[T5:.*]], |
711 ; MIPS32: lw [[T6:.*]],40(sp) | 871 ; MIPS32: lw [[T6:.*]], |
712 ; MIPS32: lw [[T7:.*]],44(sp) | 872 ; MIPS32: lw [[T7:.*]], |
713 ; MIPS32: andi [[T8:.*]],a0,0x1 | 873 ; MIPS32: andi [[T8:.*]],a0,0x1 |
714 ; MIPS32: movn [[T4]],[[T0]],[[T8]] | 874 ; MIPS32: movn [[T4]],[[T0]],[[T8]] |
715 ; MIPS32: andi [[T9:.*]],a1,0x1 | 875 ; MIPS32: andi [[T9:.*]],a1,0x1 |
716 ; MIPS32: movn [[T5]],[[T1]],[[T9]] | 876 ; MIPS32: movn [[T5]],[[T1]],[[T9]] |
717 ; MIPS32: andi [[T10:.*]],a2,0x1 | 877 ; MIPS32: andi [[T10:.*]],a2,0x1 |
718 ; MIPS32: movn [[T6]],[[T2]],[[T10]] | 878 ; MIPS32: movn [[T6]],[[T2]],[[T10]] |
719 ; MIPS32: andi [[T11:.*]],a3,0x1 | 879 ; MIPS32: andi [[T11:.*]],a3,0x1 |
720 ; MIPS32: movn [[T7]],[[T3]],[[T11]] | 880 ; MIPS32: movn [[T7]],[[T3]],[[T11]] |
721 ; MIPS32: move v0,[[T4]] | 881 ; MIPS32: move v0,[[T4]] |
722 ; MIPS32: move v1,[[T5]] | 882 ; MIPS32: move v1,[[T5]] |
723 ; MIPS32: move a0,[[T6]] | 883 ; MIPS32: move a0,[[T6]] |
724 ; MIPS32: move a1,[[T7]] | 884 ; MIPS32: move a1,[[T7]] |
725 } | 885 } |
726 | 886 |
727 define internal <4 x float> @test_select_v4f32( | 887 define internal <4 x float> @test_select_v4f32( |
728 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { | 888 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { |
729 entry: | 889 entry: |
730 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 | 890 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 |
731 ret <4 x float> %res | 891 ret <4 x float> %res |
732 ; CHECK-LABEL: test_select_v4f32 | 892 ; CHECK-LABEL: test_select_v4f32 |
733 ; CHECK: pand | 893 ; CHECK: pand |
734 ; CHECK: pandn | 894 ; CHECK: pandn |
735 ; CHECK: por | 895 ; CHECK: por |
736 | 896 |
737 ; SSE41-LABEL: test_select_v4f32 | 897 ; SSE41-LABEL: test_select_v4f32 |
738 ; SSE41: pslld xmm0,0x1f | 898 ; SSE41: pslld xmm0,0x1f |
739 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 899 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
740 | 900 |
741 ; MIPS32-LABEL: test_select_v4f32 | 901 ; MIPS32-LABEL: test_select_v4f32 |
742 ; MIPS32: lw [[T0:.*]],16(sp) | 902 ; MIPS32: lw [[T0:.*]], |
743 ; MIPS32: lw [[T1:.*]],20(sp) | 903 ; MIPS32: lw [[T1:.*]], |
744 ; MIPS32: lw [[T2:.*]],24(sp) | 904 ; MIPS32: lw [[T2:.*]], |
745 ; MIPS32: lw [[T3:.*]],28(sp) | 905 ; MIPS32: lw [[T3:.*]], |
746 ; MIPS32: lw [[T4:.*]],32(sp) | 906 ; MIPS32: lw [[T4:.*]], |
747 ; MIPS32: lw [[T5:.*]],36(sp) | 907 ; MIPS32: lw [[T5:.*]], |
748 ; MIPS32: lw [[T6:.*]],40(sp) | 908 ; MIPS32: lw [[T6:.*]], |
749 ; MIPS32: lw [[T7:.*]],44(sp) | 909 ; MIPS32: lw [[T7:.*]], |
750 ; MIPS32: lw [[T8:.*]],48(sp) | 910 ; MIPS32: lw [[T8:.*]], |
751 ; MIPS32: lw [[T9:.*]],52(sp) | 911 ; MIPS32: lw [[T9:.*]], |
752 ; MIPS32: andi [[T10:.*]],a2,0x1 | 912 ; MIPS32: andi [[T10:.*]],a2,0x1 |
753 ; MIPS32: mtc1 [[T2]],[[F0:.*]] | 913 ; MIPS32: mtc1 [[T2]],$f0 |
754 ; MIPS32: mtc1 [[T6]],[[F1:.*]] | 914 ; MIPS32: mtc1 [[T6]],$f1 |
755 ; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]] | 915 ; MIPS32: movn.s [[T11:.*]],$f0,[[T10]] |
756 ; MIPS32: mfc1 v0,[[T11]] | 916 ; MIPS32: mfc1 [[T2]],[[T11]] |
757 ; MIPS32: andi [[T12:.*]],a3,0x1 | 917 ; MIPS32: andi [[T12:.*]],a3,0x1 |
758 ; MIPS32: mtc1 [[T3]],[[F0]] | 918 ; MIPS32: mtc1 [[T3]],$f0 |
759 ; MIPS32: mtc1 [[T7]],[[T11]] | 919 ; MIPS32: mtc1 [[T7]],[[T11]] |
760 ; MIPS32: movn.s [[T11]],[[F0]],[[T12]] | 920 ; MIPS32: movn.s [[T11]],$f0,[[T12]] |
761 ; MIPS32: mfc1 v1,[[T11]] | 921 ; MIPS32: mfc1 [[T3]],[[T11]] |
762 ; MIPS32: andi [[T0]],[[T0]],0x1 | 922 ; MIPS32: andi [[T0]],[[T0]],0x1 |
763 ; MIPS32: mtc1 [[T4]],[[F0]] | 923 ; MIPS32: mtc1 [[T4]],$f0 |
764 ; MIPS32: mtc1 [[T8]],[[T11]] | 924 ; MIPS32: mtc1 [[T8]],[[T11]] |
765 ; MIPS32: movn.s [[T11]],[[F0]],[[T0]] | 925 ; MIPS32: movn.s [[T11]],$f0,[[T0]] |
766 ; MIPS32: mfc1 a1,[[T11]] | 926 ; MIPS32: mfc1 [[T4]],[[T11]] |
767 ; MIPS32: andi [[T1]],[[T1]],0x1 | 927 ; MIPS32: andi [[T1]],[[T1]],0x1 |
768 ; MIPS32: mtc1 [[T5]],[[F0]] | 928 ; MIPS32: mtc1 [[T5]],$f0 |
769 ; MIPS32: mtc1 [[T9]],[[T11]] | 929 ; MIPS32: mtc1 [[T9]],[[T11]] |
770 ; MIPS32: movn.s [[T11]],[[F0]],[[T1]] | 930 ; MIPS32: movn.s [[T11]],$f0,[[T1]] |
771 ; MIPS32: mfc1 a2,[[T11]] | 931 ; MIPS32: mfc1 [[T10]],[[T11]] |
772 ; MIPS32: move [[RET:.*]],a0 | 932 ; MIPS32: move [[T12]],a0 |
773 ; MIPS32: sw v0,0([[RET]]) | 933 ; MIPS32: sw [[T2]],0(a3) |
774 ; MIPS32: sw v1,4([[RET]]) | 934 ; MIPS32: sw v1,4(a3) |
775 ; MIPS32: sw a1,8([[RET]]) | 935 ; MIPS32: sw a1,8(a3) |
776 ; MIPS32: sw a2,12([[RET]]) | 936 ; MIPS32: sw [[T10]],12(a3) |
777 ; MIPS32: move v0,a0 | 937 ; MIPS32: move v0,a0 |
778 } | 938 } |
779 | 939 |
780 define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, | 940 define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, |
781 <4 x i1> %arg2) { | 941 <4 x i1> %arg2) { |
782 entry: | 942 entry: |
783 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 | 943 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 |
784 ret <4 x i1> %res | 944 ret <4 x i1> %res |
785 ; CHECK-LABEL: test_select_v4i1 | 945 ; CHECK-LABEL: test_select_v4i1 |
786 ; CHECK: pand | 946 ; CHECK: pand |
787 ; CHECK: pandn | 947 ; CHECK: pandn |
788 ; CHECK: por | 948 ; CHECK: por |
789 | 949 |
790 ; SSE41-LABEL: test_select_v4i1 | 950 ; SSE41-LABEL: test_select_v4i1 |
791 ; SSE41: pslld xmm0,0x1f | 951 ; SSE41: pslld xmm0,0x1f |
792 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 952 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
793 | 953 |
794 ; MIPS32-LABEL: test_select_v4i1 | 954 ; MIPS32-LABEL: test_select_v4i1 |
795 ; MIPS32: lw [[T0:.*]],16(sp) | 955 ; MIPS32: lw [[T0:.*]], |
796 ; MIPS32: lw [[T1:.*]],20(sp) | 956 ; MIPS32: lw [[T1:.*]], |
797 ; MIPS32: lw [[T2:.*]],24(sp) | 957 ; MIPS32: lw [[T2:.*]], |
798 ; MIPS32: lw [[T3:.*]],28(sp) | 958 ; MIPS32: lw [[T3:.*]], |
799 ; MIPS32: lw [[T4:.*]],32(sp) | 959 ; MIPS32: lw [[T4:.*]], |
800 ; MIPS32: lw [[T5:.*]],36(sp) | 960 ; MIPS32: lw [[T5:.*]], |
801 ; MIPS32: lw [[T6:.*]],40(sp) | 961 ; MIPS32: lw [[T6:.*]], |
802 ; MIPS32: lw [[T7:.*]],44(sp) | 962 ; MIPS32: lw [[T7:.*]], |
803 ; MIPS32: andi [[T8:.*]],a0,0x1 | 963 ; MIPS32: andi [[T8:.*]],a0,0x1 |
804 ; MIPS32: andi [[T0]],[[T0]],0x1 | 964 ; MIPS32: andi [[T0]],[[T0]],0x1 |
805 ; MIPS32: andi [[T4]],[[T4]],0x1 | 965 ; MIPS32: andi [[T4]],[[T4]],0x1 |
806 ; MIPS32: movn [[T4]],[[T0]],[[T8]] | 966 ; MIPS32: movn [[T4]],[[T0]],[[T8]] |
807 ; MIPS32: andi [[T9:.*]],a1,0x1 | 967 ; MIPS32: andi [[T9:.*]],a1,0x1 |
808 ; MIPS32: andi [[T1]],[[T1]],0x1 | 968 ; MIPS32: andi [[T1]],[[T1]],0x1 |
809 ; MIPS32: andi [[T5]],[[T5]],0x1 | 969 ; MIPS32: andi [[T5]],[[T5]],0x1 |
810 ; MIPS32: movn [[T5]],[[T1]],[[T9]] | 970 ; MIPS32: movn [[T5]],[[T1]],[[T9]] |
811 ; MIPS32: andi [[T10:.*]],a2,0x1 | 971 ; MIPS32: andi [[T10:.*]],a2,0x1 |
812 ; MIPS32: andi [[T2]],[[T2]],0x1 | 972 ; MIPS32: andi [[T2]],[[T2]],0x1 |
813 ; MIPS32: andi [[T6]],[[T6]],0x1 | 973 ; MIPS32: andi [[T6]],[[T6]],0x1 |
814 ; MIPS32: movn [[T6]],[[T2]],[[T10]] | 974 ; MIPS32: movn [[T6]],[[T2]],[[T10]] |
815 ; MIPS32: andi [[T11:.*]],a3,0x1 | 975 ; MIPS32: andi [[T11:.*]],a3,0x1 |
816 ; MIPS32: andi [[T3]],[[T3]],0x1 | 976 ; MIPS32: andi [[T3]],[[T3]],0x1 |
817 ; MIPS32: andi [[T7]],[[T7]],0x1 | 977 ; MIPS32: andi [[T7]],[[T7]],0x1 |
818 ; MIPS32: movn [[T7]],[[T3]],[[T11]] | 978 ; MIPS32: movn [[T7]],[[T3]],[[T11]] |
819 ; MIPS32: move v0,[[T4]] | 979 ; MIPS32: move v0,[[T4]] |
820 ; MIPS32: move v1,[[T5]] | 980 ; MIPS32: move v1,[[T5]] |
821 ; MIPS32: move a0,[[T6]] | 981 ; MIPS32: move a0,[[T6]] |
822 ; MIPS32: move a1,[[T7]] | 982 ; MIPS32: move a1,[[T7]] |
823 } | 983 } |
OLD | NEW |