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Issue 2468133002: [SubZero] Fix code generation for vector type (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 1 month ago
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1 ; This file checks support for comparing vector values with the icmp 1 ; This file checks support for comparing vector values with the icmp
2 ; instruction. 2 ; instruction.
3 3
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
6 6
7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ 7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ 8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
9 ; RUN: -i %s --args -O2 \ 9 ; RUN: -i %s --args -O2 \
10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \
11 ; RUN: --command FileCheck --check-prefix MIPS32 %s 11 ; RUN: --command FileCheck --check-prefix MIPS32 %s
12 12
13 ; Check that sext elimination occurs when the result of the comparison 13 ; Check that sext elimination occurs when the result of the comparison
14 ; instruction is already sign extended. Sign extension to 4 x i32 uses 14 ; instruction is already sign extended. Sign extension to 4 x i32 uses
15 ; the pslld instruction on x86. 15 ; the pslld instruction on x86.
16 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) { 16 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) {
17 entry: 17 entry:
18 %res.trunc = icmp eq <4 x i32> %a, %b 18 %res.trunc = icmp eq <4 x i32> %a, %b
19 %res = sext <4 x i1> %res.trunc to <4 x i32> 19 %res = sext <4 x i1> %res.trunc to <4 x i32>
20 ret <4 x i32> %res 20 ret <4 x i32> %res
21 ; CHECK-LABEL: test_sext_elimination 21 ; CHECK-LABEL: test_sext_elimination
22 ; CHECK: pcmpeqd 22 ; CHECK: pcmpeqd
23 ; CHECK-NOT: pslld 23 ; CHECK-NOT: pslld
24 24
25 ; MIPS32-LABEL: test_sext_elimination 25 ; MIPS32-LABEL: test_sext_elimination
26 ; MIPS32: lw [[B_E0:.*]], 26 ; MIPS32: lw [[T0:.*]],
27 ; MIPS32: lw [[B_E1:.*]], 27 ; MIPS32: lw [[T1:.*]],
28 ; MIPS32: lw [[B_E2:.*]], 28 ; MIPS32: lw [[T2:.*]],
29 ; MIPS32: lw [[B_E3:.*]], 29 ; MIPS32: lw [[T3:.*]],
30 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] 30 ; MIPS32: xor [[T4:.*]],a0,[[T0]]
31 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1 31 ; MIPS32: sltiu [[T4]],[[T4]],1
32 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] 32 ; MIPS32: xor [[T5:.*]],a1,[[T1]]
33 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1 33 ; MIPS32: sltiu [[T5]],[[T5]],1
34 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] 34 ; MIPS32: xor [[T6:.*]],a2,[[T2]]
35 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1 35 ; MIPS32: sltiu [[T6]],[[T6]],1
36 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] 36 ; MIPS32: xor [[T7:.*]],a3,[[T3]]
37 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1 37 ; MIPS32: sltiu [[T7]],[[T7]],1
38 ; MIPS32: andi [[R_E0]],[[R_E0]],0x1 38 ; MIPS32: andi [[T4]],[[T4]],0x1
39 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 39 ; MIPS32: sll [[T4]],[[T4]],0x1f
40 ; MIPS32: sra [[R_E0]],[[R_E0]],0x1f 40 ; MIPS32: sra [[T4]],[[T4]],0x1f
41 ; MIPS32: andi [[R_E1]],[[R_E1]],0x1 41 ; MIPS32: andi [[T5]],[[T5]],0x1
42 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 42 ; MIPS32: sll [[T5]],[[T5]],0x1f
43 ; MIPS32: sra [[R_E1]],[[R_E1]],0x1f 43 ; MIPS32: sra [[T5]],[[T5]],0x1f
44 ; MIPS32: andi [[R_E2]],[[R_E2]],0x1 44 ; MIPS32: andi [[T6]],[[T6]],0x1
45 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 45 ; MIPS32: sll [[T6]],[[T6]],0x1f
46 ; MIPS32: sra [[R_E2]],[[R_E2]],0x1f 46 ; MIPS32: sra [[T6]],[[T6]],0x1f
47 ; MIPS32: andi [[R_E3]],[[R_E3]],0x1 47 ; MIPS32: andi [[T7]],[[T7]],0x1
48 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 48 ; MIPS32: sll [[T7]],[[T7]],0x1f
49 ; MIPS32: sra [[R_E3]],[[R_E3]],0x1f 49 ; MIPS32: sra [[T7]],[[T7]],0x1f
50 ; MIPS32: move v0,[[R_E0]] 50 ; MIPS32: move v0,[[T4]]
51 ; MIPS32: move v1,[[R_E1]] 51 ; MIPS32: move v1,[[T5]]
52 ; MIPS32: move a0,[[R_E2]] 52 ; MIPS32: move a0,[[T6]]
53 ; MIPS32: move a1,[[R_E3]] 53 ; MIPS32: move a1,[[T7]]
54 } 54 }
55 55
56 define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) { 56 define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) {
57 entry: 57 entry:
58 %res = icmp eq <4 x i32> %a, %b 58 %res = icmp eq <4 x i32> %a, %b
59 ret <4 x i1> %res 59 ret <4 x i1> %res
60 ; CHECK-LABEL: test_icmp_v4i32_eq 60 ; CHECK-LABEL: test_icmp_v4i32_eq
61 ; CHECK: pcmpeqd 61 ; CHECK: pcmpeqd
62 62
63 ; MIPS32-LABEL: test_icmp_v4i32_eq 63 ; MIPS32-LABEL: test_icmp_v4i32_eq
64 ; MIPS32: lw [[B_E0:.*]], 64 ; MIPS32: lw [[T0:.*]],
65 ; MIPS32: lw [[B_E1:.*]], 65 ; MIPS32: lw [[T1:.*]],
66 ; MIPS32: lw [[B_E2:.*]], 66 ; MIPS32: lw [[T2:.*]],
67 ; MIPS32: lw [[B_E3:.*]], 67 ; MIPS32: lw [[T3:.*]],
68 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] 68 ; MIPS32: xor [[T4:.*]],a0,[[T0]]
69 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1 69 ; MIPS32: sltiu [[T4]],[[T4]],1
70 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] 70 ; MIPS32: xor [[T5:.*]],a1,[[T1]]
71 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1 71 ; MIPS32: sltiu [[T5]],[[T5]],1
72 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] 72 ; MIPS32: xor [[T6:.*]],a2,[[T2]]
73 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1 73 ; MIPS32: sltiu [[T6]],[[T6]],1
74 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] 74 ; MIPS32: xor [[T7:.*]],a3,[[T3]]
75 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1 75 ; MIPS32: sltiu [[T7]],[[T7]],1
76 ; MIPS32: move v0,[[R_E0]] 76 ; MIPS32: move v0,[[T4]]
77 ; MIPS32: move v1,[[R_E1]] 77 ; MIPS32: move v1,[[T5]]
78 ; MIPS32: move a0,[[R_E2]] 78 ; MIPS32: move a0,[[T6]]
79 ; MIPS32: move a1,[[R_E3]] 79 ; MIPS32: move a1,[[T7]]
80 } 80 }
81 81
82 define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) { 82 define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) {
83 entry: 83 entry:
84 %res = icmp ne <4 x i32> %a, %b 84 %res = icmp ne <4 x i32> %a, %b
85 ret <4 x i1> %res 85 ret <4 x i1> %res
86 ; CHECK-LABEL: test_icmp_v4i32_ne 86 ; CHECK-LABEL: test_icmp_v4i32_ne
87 ; CHECK: pcmpeqd 87 ; CHECK: pcmpeqd
88 ; CHECK: pxor 88 ; CHECK: pxor
89 89
90 ; MIPS32-LABEL: test_icmp_v4i32_ne 90 ; MIPS32-LABEL: test_icmp_v4i32_ne
91 ; MIPS32: lw [[B_E0:.*]], 91 ; MIPS32: lw [[T0:.*]],
92 ; MIPS32: lw [[B_E1:.*]], 92 ; MIPS32: lw [[T1:.*]],
93 ; MIPS32: lw [[B_E2:.*]], 93 ; MIPS32: lw [[T2:.*]],
94 ; MIPS32: lw [[B_E3:.*]], 94 ; MIPS32: lw [[T3:.*]],
95 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] 95 ; MIPS32: xor [[T4:.*]],a0,[[T0]]
96 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]] 96 ; MIPS32: sltu [[T4]],zero,[[T4]]
97 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] 97 ; MIPS32: xor [[T5:.*]],a1,[[T1]]
98 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]] 98 ; MIPS32: sltu [[T5]],zero,[[T5]]
99 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] 99 ; MIPS32: xor [[T6:.*]],a2,[[T2]]
100 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]] 100 ; MIPS32: sltu [[T6]],zero,[[T6]]
101 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] 101 ; MIPS32: xor [[T7:.*]],a3,[[T3]]
102 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]] 102 ; MIPS32: sltu [[T7]],zero,[[T7]]
103 ; MIPS32: move v0,[[R_E0]] 103 ; MIPS32: move v0,[[T4]]
104 ; MIPS32: move v1,[[R_E1]] 104 ; MIPS32: move v1,[[T5]]
105 ; MIPS32: move a0,[[R_E2]] 105 ; MIPS32: move a0,[[T6]]
106 ; MIPS32: move a1,[[R_E3]] 106 ; MIPS32: move a1,[[T7]]
107 } 107 }
108 108
109 define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) { 109 define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) {
110 entry: 110 entry:
111 %res = icmp sgt <4 x i32> %a, %b 111 %res = icmp sgt <4 x i32> %a, %b
112 ret <4 x i1> %res 112 ret <4 x i1> %res
113 ; CHECK: pcmpgtd 113 ; CHECK: pcmpgtd
114 114
115 ; MIPS32-LABEL: test_icmp_v4i32_sgt 115 ; MIPS32-LABEL: test_icmp_v4i32_sgt
116 ; MIPS32: lw [[B_E0:.*]], 116 ; MIPS32: lw [[T0:.*]],
117 ; MIPS32: lw [[B_E1:.*]], 117 ; MIPS32: lw [[T1:.*]],
118 ; MIPS32: lw [[B_E2:.*]], 118 ; MIPS32: lw [[T2:.*]],
119 ; MIPS32: lw [[B_E3:.*]], 119 ; MIPS32: lw [[T3:.*]],
120 ; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0 120 ; MIPS32: slt v0,[[T0]],[[T4:.*]]
121 ; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1 121 ; MIPS32: slt v1,[[T1]],[[T5:.*]]
122 ; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2 122 ; MIPS32: slt [[T2]],[[T2]],[[T6:.*]]
123 ; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3 123 ; MIPS32: slt [[T3]],[[T3]],[[T7:.*]]
124 ; MIPS32: move a0,[[T2]]
125 ; MIPS32: move a1,[[T3]]
124 } 126 }
125 127
126 define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) { 128 define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) {
127 entry: 129 entry:
128 %res = icmp sle <4 x i32> %a, %b 130 %res = icmp sle <4 x i32> %a, %b
129 ret <4 x i1> %res 131 ret <4 x i1> %res
130 ; CHECK-LABEL: test_icmp_v4i32_sle 132 ; CHECK-LABEL: test_icmp_v4i32_sle
131 ; CHECK: pcmpgtd 133 ; CHECK: pcmpgtd
132 ; CHECK: pxor 134 ; CHECK: pxor
133 135
134 ; MIPS32-LABEL: test_icmp_v4i32_sle 136 ; MIPS32-LABEL: test_icmp_v4i32_sle
135 ; MIPS32: lw [[B_E0:.*]], 137 ; MIPS32: lw [[T0:.*]],
136 ; MIPS32: lw [[B_E1:.*]], 138 ; MIPS32: lw [[T1:.*]],
137 ; MIPS32: lw [[B_E2:.*]], 139 ; MIPS32: lw [[T2:.*]],
138 ; MIPS32: lw [[B_E3:.*]], 140 ; MIPS32: lw [[T3:.*]],
139 ; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0 141 ; MIPS32: slt [[T0]],[[T0]],[[T4:.*]]
140 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 142 ; MIPS32: xori v0,[[T0]],0x1
141 ; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1 143 ; MIPS32: slt [[T1]],[[T1]],[[T5:.*]]
142 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 144 ; MIPS32: xori v1,[[T1]],0x1
143 ; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2 145 ; MIPS32: slt [[T2]],[[T2]],[[T6:.*]]
144 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 146 ; MIPS32: xori [[T2]],[[T2]],0x1
145 ; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3 147 ; MIPS32: slt [[T3]],[[T3]],[[T7:.*]]
146 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 148 ; MIPS32: xori [[T3]],[[T3]],0x1
149 ; MIPS32: move a0,[[T2]]
150 ; MIPS32: move a1,[[T3]]
147 } 151 }
148 152
149 define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) { 153 define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) {
150 entry: 154 entry:
151 %res = icmp slt <4 x i32> %a, %b 155 %res = icmp slt <4 x i32> %a, %b
152 ret <4 x i1> %res 156 ret <4 x i1> %res
153 ; CHECK-LABEL: test_icmp_v4i32_slt 157 ; CHECK-LABEL: test_icmp_v4i32_slt
154 ; CHECK: pcmpgtd 158 ; CHECK: pcmpgtd
155 159
156 ; MIPS32-LABEL: test_icmp_v4i32_slt 160 ; MIPS32-LABEL: test_icmp_v4i32_slt
157 ; MIPS32: lw [[B_E0:.*]], 161 ; MIPS32: lw [[T0:.*]],
158 ; MIPS32: lw [[B_E1:.*]], 162 ; MIPS32: lw [[T1:.*]],
159 ; MIPS32: lw [[B_E2:.*]], 163 ; MIPS32: lw [[T2:.*]],
160 ; MIPS32: lw [[B_E3:.*]], 164 ; MIPS32: lw [[T3:.*]],
161 ; MIPS32: slt [[R_E0:.*]],a0,[[B_E0]] 165 ; MIPS32: slt [[T4:.*]],a0,[[T0]]
162 ; MIPS32: slt [[R_E1:.*]],a1,[[B_E1]] 166 ; MIPS32: slt [[T5:.*]],a1,[[T1]]
163 ; MIPS32: slt [[R_E2:.*]],a2,[[B_E2]] 167 ; MIPS32: slt [[T6:.*]],a2,[[T2]]
164 ; MIPS32: slt [[R_E3:.*]],a3,[[B_E3]] 168 ; MIPS32: slt [[T7:.*]],a3,[[T3]]
169 ; MIPS32: move v0,[[T4]]
170 ; MIPS32: move v1,[[T5]]
171 ; MIPS32: move a0,[[T6]]
172 ; MIPS32: move a1,[[T7]]
165 } 173 }
166 174
167 define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) { 175 define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) {
168 entry: 176 entry:
169 %res = icmp uge <4 x i32> %a, %b 177 %res = icmp uge <4 x i32> %a, %b
170 ret <4 x i1> %res 178 ret <4 x i1> %res
171 ; CHECK-LABEL: test_icmp_v4i32_uge 179 ; CHECK-LABEL: test_icmp_v4i32_uge
172 ; CHECK: pxor 180 ; CHECK: pxor
173 ; CHECK: pcmpgtd 181 ; CHECK: pcmpgtd
174 ; CHECK: pxor 182 ; CHECK: pxor
175 183
176 ; MIPS32-LABEL: test_icmp_v4i32_uge 184 ; MIPS32-LABEL: test_icmp_v4i32_uge
177 ; MIPS32: lw [[B_E0:.*]], 185 ; MIPS32: lw [[T0:.*]],
178 ; MIPS32: lw [[B_E1:.*]], 186 ; MIPS32: lw [[T1:.*]],
179 ; MIPS32: lw [[B_E2:.*]], 187 ; MIPS32: lw [[T2:.*]],
180 ; MIPS32: lw [[B_E3:.*]], 188 ; MIPS32: lw [[T3:.*]],
181 ; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]] 189 ; MIPS32: sltu [[T4:.*]],a0,[[T0]]
182 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 190 ; MIPS32: xori [[T4]],[[T4]],0x1
183 ; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]] 191 ; MIPS32: sltu [[T5:.*]],a1,[[T1]]
184 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 192 ; MIPS32: xori [[T5]],[[T5]],0x1
185 ; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]] 193 ; MIPS32: sltu [[T6:.*]],a2,[[T2]]
186 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 194 ; MIPS32: xori [[T6]],[[T6]],0x1
187 ; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]] 195 ; MIPS32: sltu [[T7:.*]],a3,[[T3]]
188 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 196 ; MIPS32: xori [[T7]],[[T7]],0x1
197 ; MIPS32: move v0,[[T4]]
198 ; MIPS32: move v1,[[T5]]
199 ; MIPS32: move a0,[[T6]]
200 ; MIPS32: move a1,[[T7]]
189 } 201 }
190 202
191 define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) { 203 define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) {
192 entry: 204 entry:
193 %res = icmp ugt <4 x i32> %a, %b 205 %res = icmp ugt <4 x i32> %a, %b
194 ret <4 x i1> %res 206 ret <4 x i1> %res
195 ; CHECK-LABEL: test_icmp_v4i32_ugt 207 ; CHECK-LABEL: test_icmp_v4i32_ugt
196 ; CHECK: pxor 208 ; CHECK: pxor
197 ; CHECK: pcmpgtd 209 ; CHECK: pcmpgtd
198 210
199 ; MIPS32-LABEL: test_icmp_v4i32_ugt 211 ; MIPS32-LABEL: test_icmp_v4i32_ugt
200 ; MIPS32: lw [[B_E0:.*]], 212 ; MIPS32: lw [[T0:.*]],
201 ; MIPS32: lw [[B_E1:.*]], 213 ; MIPS32: lw [[T1:.*]],
202 ; MIPS32: lw [[B_E2:.*]], 214 ; MIPS32: lw [[T2:.*]],
203 ; MIPS32: lw [[B_E3:.*]], 215 ; MIPS32: lw [[T3:.*]],
204 ; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0 216 ; MIPS32: sltu v0,[[T0]],[[T4:.*]]
205 ; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1 217 ; MIPS32: sltu v1,[[T1]],[[T5:.*]]
206 ; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2 218 ; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]]
207 ; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3 219 ; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]]
220 ; MIPS32: move a0,[[T2]]
221 ; MIPS32: move a1,[[T3]]
208 } 222 }
209 223
210 define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) { 224 define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) {
211 entry: 225 entry:
212 %res = icmp ule <4 x i32> %a, %b 226 %res = icmp ule <4 x i32> %a, %b
213 ret <4 x i1> %res 227 ret <4 x i1> %res
214 ; CHECK-LABEL: test_icmp_v4i32_ule 228 ; CHECK-LABEL: test_icmp_v4i32_ule
215 ; CHECK: pxor 229 ; CHECK: pxor
216 ; CHECK: pcmpgtd 230 ; CHECK: pcmpgtd
217 ; CHECK: pxor 231 ; CHECK: pxor
218 232
219 ; MIPS32-LABEL: test_icmp_v4i32_ule 233 ; MIPS32-LABEL: test_icmp_v4i32_ule
220 ; MIPS32: lw [[B_E0:.*]], 234 ; MIPS32: lw [[T0:.*]],
221 ; MIPS32: lw [[B_E1:.*]], 235 ; MIPS32: lw [[T1:.*]],
222 ; MIPS32: lw [[B_E2:.*]], 236 ; MIPS32: lw [[T2:.*]],
223 ; MIPS32: lw [[B_E3:.*]], 237 ; MIPS32: lw [[T3:.*]],
224 ; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0 238 ; MIPS32: sltu [[T0]],[[T0]],[[T4:.*]]
225 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 239 ; MIPS32: xori v0,[[T0]],0x1
226 ; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1 240 ; MIPS32: sltu [[T1]],[[T1]],[[T5:.*]]
227 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 241 ; MIPS32: xori v1,[[T1]],0x1
228 ; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2 242 ; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]]
229 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 243 ; MIPS32: xori [[T2]],[[T2]],0x1
230 ; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3 244 ; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]]
231 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 245 ; MIPS32: xori [[T3]],[[T3]],0x1
246 ; MIPS32: move a0,[[T2]]
247 ; MIPS32: move a1,[[T3]]
232 } 248 }
233 249
234 define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) { 250 define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) {
235 entry: 251 entry:
236 %res = icmp ult <4 x i32> %a, %b 252 %res = icmp ult <4 x i32> %a, %b
237 ret <4 x i1> %res 253 ret <4 x i1> %res
238 ; CHECK-LABEL: test_icmp_v4i32_ult 254 ; CHECK-LABEL: test_icmp_v4i32_ult
239 ; CHECK: pxor 255 ; CHECK: pxor
240 ; CHECK: pcmpgtd 256 ; CHECK: pcmpgtd
241 257
242 ; MIPS32-LABEL: test_icmp_v4i32_ult 258 ; MIPS32-LABEL: test_icmp_v4i32_ult
243 ; MIPS32: lw [[B_E0:.*]], 259 ; MIPS32: lw [[T0:.*]],
244 ; MIPS32: lw [[B_E1:.*]], 260 ; MIPS32: lw [[T1:.*]],
245 ; MIPS32: lw [[B_E2:.*]], 261 ; MIPS32: lw [[T2:.*]],
246 ; MIPS32: lw [[B_E3:.*]], 262 ; MIPS32: lw [[T3:.*]],
247 ; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]] 263 ; MIPS32: sltu [[T4:.*]],a0,[[T0]]
248 ; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]] 264 ; MIPS32: sltu [[T5:.*]],a1,[[T1]]
249 ; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]] 265 ; MIPS32: sltu [[T6:.*]],a2,[[T2]]
250 ; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]] 266 ; MIPS32: sltu [[T7:.*]],a3,[[T3]]
267 ; MIPS32: move v0,[[T4]]
268 ; MIPS32: move v1,[[T5]]
269 ; MIPS32: move a0,[[T6]]
270 ; MIPS32: move a1,[[T7]]
251 } 271 }
252 272
253 define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) { 273 define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) {
254 entry: 274 entry:
255 %res = icmp eq <4 x i1> %a, %b 275 %res = icmp eq <4 x i1> %a, %b
256 ret <4 x i1> %res 276 ret <4 x i1> %res
257 ; CHECK-LABEL: test_icmp_v4i1_eq 277 ; CHECK-LABEL: test_icmp_v4i1_eq
258 ; CHECK: pcmpeqd 278 ; CHECK: pcmpeqd
259 279
260 ; MIPS32-LABEL: test_icmp_v4i1_eq 280 ; MIPS32-LABEL: test_icmp_v4i1_eq
261 ; MIPS32: lw [[B_E0:.*]], 281 ; MIPS32: lw [[T0:.*]],
262 ; MIPS32: lw [[B_E1:.*]], 282 ; MIPS32: lw [[T1:.*]],
263 ; MIPS32: lw [[B_E2:.*]], 283 ; MIPS32: lw [[T2:.*]],
264 ; MIPS32: lw [[B_E3:.*]], 284 ; MIPS32: lw [[T3:.*]],
265 ; MIPS32: andi [[R_E0:.*]],a0,0x1 285 ; MIPS32: andi [[T4:.*]],a0,0x1
266 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 286 ; MIPS32: andi [[T0]],[[T0]],0x1
267 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 287 ; MIPS32: sll [[T4]],[[T4]],0x1f
268 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 288 ; MIPS32: sll [[T0]],[[T0]],0x1f
269 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]] 289 ; MIPS32: xor [[T4]],[[T4]],[[T0]]
270 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1 290 ; MIPS32: sltiu [[T4]],[[T4]],1
271 ; MIPS32: andi [[R_E1:.*]],a1,0x1 291 ; MIPS32: andi [[T5:.*]],a1,0x1
272 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 292 ; MIPS32: andi [[T1]],[[T1]],0x1
273 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 293 ; MIPS32: sll [[T5]],[[T5]],0x1f
274 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 294 ; MIPS32: sll [[T1]],[[T1]],0x1f
275 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]] 295 ; MIPS32: xor [[T5]],[[T5]],[[T1]]
276 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1 296 ; MIPS32: sltiu [[T5]],[[T5]],1
277 ; MIPS32: andi [[R_E2:.*]],a2,0x1 297 ; MIPS32: andi [[T6:.*]],a2,0x1
278 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 298 ; MIPS32: andi [[T2]],[[T2]],0x1
279 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 299 ; MIPS32: sll [[T6]],[[T6]],0x1f
280 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 300 ; MIPS32: sll [[T2]],[[T2]],0x1f
281 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]] 301 ; MIPS32: xor [[T6]],[[T6]],[[T2]]
282 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1 302 ; MIPS32: sltiu [[T6]],[[T6]],1
283 ; MIPS32: andi [[R_E3:.*]],a3,0x1 303 ; MIPS32: andi [[T7:.*]],a3,0x1
284 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 304 ; MIPS32: andi [[T3]],[[T3]],0x1
285 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 305 ; MIPS32: sll [[T7]],[[T7]],0x1f
286 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 306 ; MIPS32: sll [[T3]],[[T3]],0x1f
287 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]] 307 ; MIPS32: xor [[T7]],[[T7]],[[T3]]
288 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1 308 ; MIPS32: sltiu [[T7]],[[T7]],1
289 ; MIPS32: move v0,[[R_E0]] 309 ; MIPS32: move v0,[[T4]]
290 ; MIPS32: move v1,[[R_E1]] 310 ; MIPS32: move v1,[[T5]]
291 ; MIPS32: move a0,[[R_E2]] 311 ; MIPS32: move a0,[[T6]]
292 ; MIPS32: move a1,[[R_E3]] 312 ; MIPS32: move a1,[[T7]]
293 } 313 }
294 314
295 define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) { 315 define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) {
296 entry: 316 entry:
297 %res = icmp ne <4 x i1> %a, %b 317 %res = icmp ne <4 x i1> %a, %b
298 ret <4 x i1> %res 318 ret <4 x i1> %res
299 ; CHECK-LABEL: test_icmp_v4i1_ne 319 ; CHECK-LABEL: test_icmp_v4i1_ne
300 ; CHECK: pcmpeqd 320 ; CHECK: pcmpeqd
301 ; CHECK: pxor 321 ; CHECK: pxor
302 322
303 ; MIPS32-LABEL: test_icmp_v4i1_ne 323 ; MIPS32-LABEL: test_icmp_v4i1_ne
304 ; MIPS32: lw [[B_E0:.*]], 324 ; MIPS32: lw [[T0:.*]],
305 ; MIPS32: lw [[B_E1:.*]], 325 ; MIPS32: lw [[T1:.*]],
306 ; MIPS32: lw [[B_E2:.*]], 326 ; MIPS32: lw [[T2:.*]],
307 ; MIPS32: lw [[B_E3:.*]], 327 ; MIPS32: lw [[T3:.*]],
308 ; MIPS32: andi [[R_E0:.*]],a0,0x1 328 ; MIPS32: andi [[T4:.*]],a0,0x1
309 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 329 ; MIPS32: andi [[T0]],[[T0]],0x1
310 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 330 ; MIPS32: sll [[T4]],[[T4]],0x1f
311 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 331 ; MIPS32: sll [[T0]],[[T0]],0x1f
312 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]] 332 ; MIPS32: xor [[T4]],[[T4]],[[T0]]
313 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]] 333 ; MIPS32: sltu [[T4]],zero,[[T4]]
314 ; MIPS32: andi [[R_E1:.*]],a1,0x1 334 ; MIPS32: andi [[T5:.*]],a1,0x1
315 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 335 ; MIPS32: andi [[T1]],[[T1]],0x1
316 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 336 ; MIPS32: sll [[T5]],[[T5]],0x1f
317 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 337 ; MIPS32: sll [[T1]],[[T1]],0x1f
318 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]] 338 ; MIPS32: xor [[T5]],[[T5]],[[T1]]
319 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]] 339 ; MIPS32: sltu [[T5]],zero,[[T5]]
320 ; MIPS32: andi [[R_E2:.*]],a2,0x1 340 ; MIPS32: andi [[T6:.*]],a2,0x1
321 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 341 ; MIPS32: andi [[T2]],[[T2]],0x1
322 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 342 ; MIPS32: sll [[T6]],[[T6]],0x1f
323 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 343 ; MIPS32: sll [[T2]],[[T2]],0x1f
324 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]] 344 ; MIPS32: xor [[T6]],[[T6]],[[T2]]
325 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]] 345 ; MIPS32: sltu [[T6]],zero,[[T6]]
326 ; MIPS32: andi [[R_E3:.*]],a3,0x1 346 ; MIPS32: andi [[T7:.*]],a3,0x1
327 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 347 ; MIPS32: andi [[T3]],[[T3]],0x1
328 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 348 ; MIPS32: sll [[T7]],[[T7]],0x1f
329 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 349 ; MIPS32: sll [[T3]],[[T3]],0x1f
330 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]] 350 ; MIPS32: xor [[T7]],[[T7]],[[T3]]
331 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]] 351 ; MIPS32: sltu [[T7]],zero,[[T7]]
332 ; MIPS32: move v0,[[R_E0]] 352 ; MIPS32: move v0,[[T4]]
333 ; MIPS32: move v1,[[R_E1]] 353 ; MIPS32: move v1,[[T5]]
334 ; MIPS32: move a0,[[R_E2]] 354 ; MIPS32: move a0,[[T6]]
335 ; MIPS32: move a1,[[R_E3]] 355 ; MIPS32: move a1,[[T7]]
336 } 356 }
337 357
338 define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) { 358 define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) {
339 entry: 359 entry:
340 %res = icmp sgt <4 x i1> %a, %b 360 %res = icmp sgt <4 x i1> %a, %b
341 ret <4 x i1> %res 361 ret <4 x i1> %res
342 ; CHECK-LABEL: test_icmp_v4i1_sgt 362 ; CHECK-LABEL: test_icmp_v4i1_sgt
343 ; CHECK: pcmpgtd 363 ; CHECK: pcmpgtd
344 364
345 ; MIPS32-LABEL: test_icmp_v4i1_sgt 365 ; MIPS32-LABEL: test_icmp_v4i1_sgt
346 ; MIPS32: lw [[B_E0:.*]], 366 ; MIPS32: lw [[T0:.*]],
347 ; MIPS32: lw [[B_E1:.*]], 367 ; MIPS32: lw [[T1:.*]],
348 ; MIPS32: lw [[B_E2:.*]], 368 ; MIPS32: lw [[T2:.*]],
349 ; MIPS32: lw [[B_E3:.*]], 369 ; MIPS32: lw [[T3:.*]],
350 ; MIPS32: andi [[T_E0:.*]],a0,0x1 370 ; MIPS32: andi [[T4:.*]],a0,0x1
351 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 371 ; MIPS32: andi [[T0]],[[T0]],0x1
352 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 372 ; MIPS32: sll [[T4]],[[T4]],0x1f
353 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 373 ; MIPS32: sll [[T0]],[[T0]],0x1f
354 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] 374 ; MIPS32: slt v0,[[T0]],[[T4]]
355 ; MIPS32: andi [[T_E1:.*]],a1,0x1 375 ; MIPS32: andi [[T5:.*]],a1,0x1
356 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 376 ; MIPS32: andi [[T1]],[[T1]],0x1
357 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 377 ; MIPS32: sll [[T5]],[[T5]],0x1f
358 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 378 ; MIPS32: sll [[T1]],[[T1]],0x1f
359 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] 379 ; MIPS32: slt v1,[[T1]],[[T5]]
360 ; MIPS32: andi [[T_E2:.*]],a2,0x1 380 ; MIPS32: andi [[T6:.*]],a2,0x1
361 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 381 ; MIPS32: andi [[T2]],[[T2]],0x1
362 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 382 ; MIPS32: sll [[T6]],[[T6]],0x1f
363 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 383 ; MIPS32: sll [[T2]],[[T2]],0x1f
364 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] 384 ; MIPS32: slt [[T2]],[[T2]],[[T6]]
365 ; MIPS32: andi [[T_E3:.*]],a3,0x1 385 ; MIPS32: andi [[T7:.*]],a3,0x1
366 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 386 ; MIPS32: andi [[T3]],[[T3]],0x1
367 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 387 ; MIPS32: sll [[T7]],[[T7]],0x1f
368 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 388 ; MIPS32: sll [[T3]],[[T3]],0x1f
369 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] 389 ; MIPS32: slt [[T3]],[[T3]],[[T7]]
390 ; MIPS32: move a0,[[T2]]
391 ; MIPS32: move a1,[[T3]]
370 } 392 }
371 393
372 define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) { 394 define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) {
373 entry: 395 entry:
374 %res = icmp sle <4 x i1> %a, %b 396 %res = icmp sle <4 x i1> %a, %b
375 ret <4 x i1> %res 397 ret <4 x i1> %res
376 ; CHECK-LABEL: test_icmp_v4i1_sle 398 ; CHECK-LABEL: test_icmp_v4i1_sle
377 ; CHECK: pcmpgtd 399 ; CHECK: pcmpgtd
378 ; CHECK: pxor 400 ; CHECK: pxor
379 401
380 ; MIPS32-LABEL: test_icmp_v4i1_sle 402 ; MIPS32-LABEL: test_icmp_v4i1_sle
381 ; MIPS32: lw [[B_E0:.*]], 403 ; MIPS32: lw [[T0:.*]],
382 ; MIPS32: lw [[B_E1:.*]], 404 ; MIPS32: lw [[T1:.*]],
383 ; MIPS32: lw [[B_E2:.*]], 405 ; MIPS32: lw [[T2:.*]],
384 ; MIPS32: lw [[B_E3:.*]], 406 ; MIPS32: lw [[T3:.*]],
385 ; MIPS32: andi [[T_E0:.*]],a0,0x1 407 ; MIPS32: andi [[T4:.*]],a0,0x1
386 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 408 ; MIPS32: andi [[T0]],[[T0]],0x1
387 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 409 ; MIPS32: sll [[T4]],[[T4]],0x1f
388 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 410 ; MIPS32: sll [[T0]],[[T0]],0x1f
389 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] 411 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
390 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 412 ; MIPS32: xori v0,[[T0]],0x1
391 ; MIPS32: andi [[T_E1:.*]],a1,0x1 413 ; MIPS32: andi [[T5:.*]],a1,0x1
392 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 414 ; MIPS32: andi [[T1]],[[T1]],0x1
393 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 415 ; MIPS32: sll [[T5]],[[T5]],0x1f
394 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 416 ; MIPS32: sll [[T1]],[[T1]],0x1f
395 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] 417 ; MIPS32: slt [[T1]],[[T1]],[[T5]]
396 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 418 ; MIPS32: xori v1,[[T1]],0x1
397 ; MIPS32: andi [[T_E2:.*]],a2,0x1 419 ; MIPS32: andi [[T6:.*]],a2,0x1
398 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 420 ; MIPS32: andi [[T2]],[[T2]],0x1
399 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 421 ; MIPS32: sll [[T6]],[[T6]],0x1f
400 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 422 ; MIPS32: sll [[T2]],[[T2]],0x1f
401 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] 423 ; MIPS32: slt [[T2]],[[T2]],[[T6]]
402 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 424 ; MIPS32: xori [[T2]],[[T2]],0x1
403 ; MIPS32: andi [[T_E3:.*]],a3,0x1 425 ; MIPS32: andi [[T7:.*]],a3,0x1
404 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 426 ; MIPS32: andi [[T3]],[[T3]],0x1
405 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 427 ; MIPS32: sll [[T7]],[[T7]],0x1f
406 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 428 ; MIPS32: sll [[T3]],[[T3]],0x1f
407 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] 429 ; MIPS32: slt [[T3]],[[T3]],[[T7]]
408 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 430 ; MIPS32: xori [[T3]],[[T3]],0x1
431 ; MIPS32: move a0,[[T2]]
432 ; MIPS32: move a1,[[T3]]
409 } 433 }
410 434
411 define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) { 435 define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) {
412 entry: 436 entry:
413 %res = icmp slt <4 x i1> %a, %b 437 %res = icmp slt <4 x i1> %a, %b
414 ret <4 x i1> %res 438 ret <4 x i1> %res
415 ; CHECK-LABEL: test_icmp_v4i1_slt 439 ; CHECK-LABEL: test_icmp_v4i1_slt
416 ; CHECK: pcmpgtd 440 ; CHECK: pcmpgtd
417 441
418 ; MIPS32-LABEL: test_icmp_v4i1_slt 442 ; MIPS32-LABEL: test_icmp_v4i1_slt
419 ; MIPS32: lw [[B_E0:.*]], 443 ; MIPS32: lw [[T0:.*]],
420 ; MIPS32: lw [[B_E1:.*]], 444 ; MIPS32: lw [[T1:.*]],
421 ; MIPS32: lw [[B_E2:.*]], 445 ; MIPS32: lw [[T2:.*]],
422 ; MIPS32: lw [[B_E3:.*]], 446 ; MIPS32: lw [[T3:.*]],
423 ; MIPS32: andi [[R_E0:.*]],a0,0x1 447 ; MIPS32: andi [[T4:.*]],a0,0x1
424 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 448 ; MIPS32: andi [[T0]],[[T0]],0x1
425 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 449 ; MIPS32: sll [[T4]],[[T4]],0x1f
426 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 450 ; MIPS32: sll [[T0]],[[T0]],0x1f
427 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] 451 ; MIPS32: slt [[T4]],[[T4]],[[T0]]
428 ; MIPS32: andi [[R_E1:.*]],a1,0x1 452 ; MIPS32: andi [[T5:.*]],a1,0x1
429 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 453 ; MIPS32: andi [[T1]],[[T1]],0x1
430 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 454 ; MIPS32: sll [[T5]],[[T5]],0x1f
431 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 455 ; MIPS32: sll [[T1]],[[T1]],0x1f
432 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] 456 ; MIPS32: slt [[T5]],[[T5]],[[T1]]
433 ; MIPS32: andi [[R_E2:.*]],a2,0x1 457 ; MIPS32: andi [[T6:.*]],a2,0x1
434 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 458 ; MIPS32: andi [[T2]],[[T2]],0x1
435 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 459 ; MIPS32: sll [[T6]],[[T6]],0x1f
436 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 460 ; MIPS32: sll [[T2]],[[T2]],0x1f
437 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] 461 ; MIPS32: slt [[T6]],[[T6]],[[T2]]
438 ; MIPS32: andi [[R_E3:.*]],a3,0x1 462 ; MIPS32: andi [[T7:.*]],a3,0x1
439 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 463 ; MIPS32: andi [[T3]],[[T3]],0x1
440 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 464 ; MIPS32: sll [[T7]],[[T7]],0x1f
441 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 465 ; MIPS32: sll [[T3]],[[T3]],0x1f
442 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] 466 ; MIPS32: slt [[T7]],[[T7]],[[T3]]
443 ; MIPS32: move v0,[[R_E0]] 467 ; MIPS32: move v0,[[T4]]
444 ; MIPS32: move v1,[[R_E1]] 468 ; MIPS32: move v1,[[T5]]
445 ; MIPS32: move a0,[[R_E2]] 469 ; MIPS32: move a0,[[T6]]
446 ; MIPS32: move a1,[[R_E3]] 470 ; MIPS32: move a1,[[T7]]
447 } 471 }
448 472
449 define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) { 473 define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) {
450 entry: 474 entry:
451 %res = icmp uge <4 x i1> %a, %b 475 %res = icmp uge <4 x i1> %a, %b
452 ret <4 x i1> %res 476 ret <4 x i1> %res
453 ; CHECK-LABEL: test_icmp_v4i1_uge 477 ; CHECK-LABEL: test_icmp_v4i1_uge
454 ; CHECK: pxor 478 ; CHECK: pxor
455 ; CHECK: pcmpgtd 479 ; CHECK: pcmpgtd
456 ; CHECK: pxor 480 ; CHECK: pxor
457 481
458 ; MIPS32-LABEL: test_icmp_v4i1_uge 482 ; MIPS32-LABEL: test_icmp_v4i1_uge
459 ; MIPS32: lw [[B_E0:.*]], 483 ; MIPS32: lw [[T0:.*]],
460 ; MIPS32: lw [[B_E1:.*]], 484 ; MIPS32: lw [[T1:.*]],
461 ; MIPS32: lw [[B_E2:.*]], 485 ; MIPS32: lw [[T2:.*]],
462 ; MIPS32: lw [[B_E3:.*]], 486 ; MIPS32: lw [[T3:.*]],
463 ; MIPS32: andi [[R_E0:.*]],a0,0x1 487 ; MIPS32: andi [[T4:.*]],a0,0x1
464 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 488 ; MIPS32: andi [[T0]],[[T0]],0x1
465 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 489 ; MIPS32: sll [[T4]],[[T4]],0x1f
466 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 490 ; MIPS32: sll [[T0]],[[T0]],0x1f
467 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] 491 ; MIPS32: sltu [[T4]],[[T4]],[[T0]]
468 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 492 ; MIPS32: xori [[T4]],[[T4]],0x1
469 ; MIPS32: andi [[R_E1:.*]],a1,0x1 493 ; MIPS32: andi [[T5:.*]],a1,0x1
470 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 494 ; MIPS32: andi [[T1]],[[T1]],0x1
471 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 495 ; MIPS32: sll [[T5]],[[T5]],0x1f
472 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 496 ; MIPS32: sll [[T1]],[[T1]],0x1f
473 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] 497 ; MIPS32: sltu [[T5]],[[T5]],[[T1]]
474 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 498 ; MIPS32: xori [[T5]],[[T5]],0x1
475 ; MIPS32: andi [[R_E2:.*]],a2,0x1 499 ; MIPS32: andi [[T6:.*]],a2,0x1
476 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 500 ; MIPS32: andi [[T2]],[[T2]],0x1
477 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 501 ; MIPS32: sll [[T6]],[[T6]],0x1f
478 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 502 ; MIPS32: sll [[T2]],[[T2]],0x1f
479 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] 503 ; MIPS32: sltu [[T6]],[[T6]],[[T2]]
480 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 504 ; MIPS32: xori [[T6]],[[T6]],0x1
481 ; MIPS32: andi [[R_E3:.*]],a3,0x1 505 ; MIPS32: andi [[T7:.*]],a3,0x1
482 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 506 ; MIPS32: andi [[T3]],[[T3]],0x1
483 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 507 ; MIPS32: sll [[T7]],[[T7]],0x1f
484 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 508 ; MIPS32: sll [[T3]],[[T3]],0x1f
485 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] 509 ; MIPS32: sltu [[T7]],[[T7]],[[T3]]
486 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 510 ; MIPS32: xori [[T7]],[[T7]],0x1
487 ; MIPS32: move v0,[[R_E0]] 511 ; MIPS32: move v0,[[T4]]
488 ; MIPS32: move v1,[[R_E1]] 512 ; MIPS32: move v1,[[T5]]
489 ; MIPS32: move a0,[[R_E2]] 513 ; MIPS32: move a0,[[T6]]
490 ; MIPS32: move a1,[[R_E3]] 514 ; MIPS32: move a1,[[T7]]
491 } 515 }
492 516
493 define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) { 517 define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) {
494 entry: 518 entry:
495 %res = icmp ugt <4 x i1> %a, %b 519 %res = icmp ugt <4 x i1> %a, %b
496 ret <4 x i1> %res 520 ret <4 x i1> %res
497 ; CHECK-LABEL: test_icmp_v4i1_ugt 521 ; CHECK-LABEL: test_icmp_v4i1_ugt
498 ; CHECK: pxor 522 ; CHECK: pxor
499 ; CHECK: pcmpgtd 523 ; CHECK: pcmpgtd
500 524
501 ; MIPS32-LABEL: test_icmp_v4i1_ugt 525 ; MIPS32-LABEL: test_icmp_v4i1_ugt
502 ; MIPS32: lw [[B_E0:.*]], 526 ; MIPS32: lw [[T0:.*]],
503 ; MIPS32: lw [[B_E1:.*]], 527 ; MIPS32: lw [[T1:.*]],
504 ; MIPS32: lw [[B_E2:.*]], 528 ; MIPS32: lw [[T2:.*]],
505 ; MIPS32: lw [[B_E3:.*]], 529 ; MIPS32: lw [[T3:.*]],
506 ; MIPS32: andi [[T_E0:.*]],a0,0x1 530 ; MIPS32: andi [[T4:.*]],a0,0x1
507 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 531 ; MIPS32: andi [[T0]],[[T0]],0x1
508 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 532 ; MIPS32: sll [[T4]],[[T4]],0x1f
509 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 533 ; MIPS32: sll [[T0]],[[T0]],0x1f
510 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] 534 ; MIPS32: sltu v0,[[T0]],[[T4]]
511 ; MIPS32: andi [[T_E1:.*]],a1,0x1 535 ; MIPS32: andi [[T5:.*]],a1,0x1
512 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 536 ; MIPS32: andi [[T1]],[[T1]],0x1
513 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 537 ; MIPS32: sll [[T5]],[[T5]],0x1f
514 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 538 ; MIPS32: sll [[T1]],[[T1]],0x1f
515 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] 539 ; MIPS32: sltu v1,[[T1]],[[T5]]
516 ; MIPS32: andi [[T_E2:.*]],a2,0x1 540 ; MIPS32: andi [[T6:.*]],a2,0x1
517 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 541 ; MIPS32: andi [[T2]],[[T2]],0x1
518 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 542 ; MIPS32: sll [[T6]],[[T6]],0x1f
519 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 543 ; MIPS32: sll [[T2]],[[T2]],0x1f
520 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] 544 ; MIPS32: sltu [[T2]],[[T2]],[[T6]]
521 ; MIPS32: andi [[T_E3:.*]],a3,0x1 545 ; MIPS32: andi [[T7:.*]],a3,0x1
522 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 546 ; MIPS32: andi [[T3]],[[T3]],0x1
523 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 547 ; MIPS32: sll [[T7]],[[T7]],0x1f
524 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 548 ; MIPS32: sll [[T3]],[[T3]],0x1f
525 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] 549 ; MIPS32: sltu [[T3]],[[T3]],[[T7]]
550 ; MIPS32: move a0,[[T2]]
551 ; MIPS32: move a1,[[T3]]
526 } 552 }
527 553
528 define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) { 554 define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) {
529 entry: 555 entry:
530 %res = icmp ule <4 x i1> %a, %b 556 %res = icmp ule <4 x i1> %a, %b
531 ret <4 x i1> %res 557 ret <4 x i1> %res
532 ; CHECK-LABEL: test_icmp_v4i1_ule 558 ; CHECK-LABEL: test_icmp_v4i1_ule
533 ; CHECK: pxor 559 ; CHECK: pxor
534 ; CHECK: pcmpgtd 560 ; CHECK: pcmpgtd
535 ; CHECK: pxor 561 ; CHECK: pxor
536 562
537 ; MIPS32-LABEL: test_icmp_v4i1_ule 563 ; MIPS32-LABEL: test_icmp_v4i1_ule
538 ; MIPS32: lw [[B_E0:.*]], 564 ; MIPS32: lw [[T0:.*]],
539 ; MIPS32: lw [[B_E1:.*]], 565 ; MIPS32: lw [[T1:.*]],
540 ; MIPS32: lw [[B_E2:.*]], 566 ; MIPS32: lw [[T2:.*]],
541 ; MIPS32: lw [[B_E3:.*]], 567 ; MIPS32: lw [[T3:.*]],
542 ; MIPS32: andi [[T_E0:.*]],a0,0x1 568 ; MIPS32: andi [[T4:.*]],a0,0x1
543 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 569 ; MIPS32: andi [[T0]],[[T0]],0x1
544 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 570 ; MIPS32: sll [[T4]],[[T4]],0x1f
545 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 571 ; MIPS32: sll [[T0]],[[T0]],0x1f
546 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] 572 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
547 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1 573 ; MIPS32: xori v0,[[T0]],0x1
548 ; MIPS32: andi [[T_E1:.*]],a1,0x1 574 ; MIPS32: andi [[T5:.*]],a1,0x1
549 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 575 ; MIPS32: andi [[T1]],[[T1]],0x1
550 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 576 ; MIPS32: sll [[T5]],[[T5]],0x1f
551 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 577 ; MIPS32: sll [[T1]],[[T1]],0x1f
552 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] 578 ; MIPS32: sltu [[T1]],[[T1]],[[T5]]
553 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1 579 ; MIPS32: xori v1,[[T1]],0x1
554 ; MIPS32: andi [[T_E2:.*]],a2,0x1 580 ; MIPS32: andi [[T6:.*]],a2,0x1
555 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 581 ; MIPS32: andi [[T2]],[[T2]],0x1
556 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 582 ; MIPS32: sll [[T6]],[[T6]],0x1f
557 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 583 ; MIPS32: sll [[T2]],[[T2]],0x1f
558 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] 584 ; MIPS32: sltu [[T2]],[[T2]],[[T6]]
559 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1 585 ; MIPS32: xori [[T2]],[[T2]],0x1
560 ; MIPS32: andi [[T_E3:.*]],a3,0x1 586 ; MIPS32: andi [[T7:.*]],a3,0x1
561 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 587 ; MIPS32: andi [[T3]],[[T3]],0x1
562 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 588 ; MIPS32: sll [[T7]],[[T7]],0x1f
563 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 589 ; MIPS32: sll [[T3]],[[T3]],0x1f
564 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] 590 ; MIPS32: sltu [[T3]],[[T3]],[[T7]]
565 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1 591 ; MIPS32: xori [[T3]],[[T3]],0x1
592 ; MIPS32: move a0,[[T2]]
593 ; MIPS32: move a1,[[T3]]
566 } 594 }
567 595
568 define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) { 596 define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) {
569 entry: 597 entry:
570 %res = icmp ult <4 x i1> %a, %b 598 %res = icmp ult <4 x i1> %a, %b
571 ret <4 x i1> %res 599 ret <4 x i1> %res
572 ; CHECK-LABEL: test_icmp_v4i1_ult 600 ; CHECK-LABEL: test_icmp_v4i1_ult
573 ; CHECK: pxor 601 ; CHECK: pxor
574 ; CHECK: pcmpgtd 602 ; CHECK: pcmpgtd
575 603
576 ; MIPS32-LABEL: test_icmp_v4i1_ult 604 ; MIPS32-LABEL: test_icmp_v4i1_ult
577 ; MIPS32: lw [[B_E0:.*]], 605 ; MIPS32: lw [[T0:.*]],
578 ; MIPS32: lw [[B_E1:.*]], 606 ; MIPS32: lw [[T1:.*]],
579 ; MIPS32: lw [[B_E2:.*]], 607 ; MIPS32: lw [[T2:.*]],
580 ; MIPS32: lw [[B_E3:.*]], 608 ; MIPS32: lw [[T3:.*]],
581 ; MIPS32: andi [[R_E0:.*]],a0,0x1 609 ; MIPS32: andi [[T4:.*]],a0,0x1
582 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 610 ; MIPS32: andi [[T0]],[[T0]],0x1
583 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f 611 ; MIPS32: sll [[T4]],[[T4]],0x1f
584 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f 612 ; MIPS32: sll [[T0]],[[T0]],0x1f
585 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] 613 ; MIPS32: sltu [[T4]],[[T4]],[[T0]]
586 ; MIPS32: andi [[R_E1:.*]],a1,0x1 614 ; MIPS32: andi [[T5:.*]],a1,0x1
587 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 615 ; MIPS32: andi [[T1]],[[T1]],0x1
588 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f 616 ; MIPS32: sll [[T5]],[[T5]],0x1f
589 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f 617 ; MIPS32: sll [[T1]],[[T1]],0x1f
590 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] 618 ; MIPS32: sltu [[T5]],[[T5]],[[T1]]
591 ; MIPS32: andi [[R_E2:.*]],a2,0x1 619 ; MIPS32: andi [[T6:.*]],a2,0x1
592 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 620 ; MIPS32: andi [[T2]],[[T2]],0x1
593 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f 621 ; MIPS32: sll [[T6]],[[T6]],0x1f
594 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f 622 ; MIPS32: sll [[T2]],[[T2]],0x1f
595 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] 623 ; MIPS32: sltu [[T6]],[[T6]],[[T2]]
596 ; MIPS32: andi [[R_E3:.*]],a3,0x1 624 ; MIPS32: andi [[T7:.*]],a3,0x1
597 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 625 ; MIPS32: andi [[T3]],[[T3]],0x1
598 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f 626 ; MIPS32: sll [[T7]],[[T7]],0x1f
599 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f 627 ; MIPS32: sll [[T3]],[[T3]],0x1f
600 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] 628 ; MIPS32: sltu [[T7]],[[T7]],[[T3]]
601 ; MIPS32: move v0,[[R_E0]] 629 ; MIPS32: move v0,[[T4]]
602 ; MIPS32: move v1,[[R_E1]] 630 ; MIPS32: move v1,[[T5]]
603 ; MIPS32: move a0,[[R_E2]] 631 ; MIPS32: move a0,[[T6]]
604 ; MIPS32: move a1,[[R_E3]] 632 ; MIPS32: move a1,[[T7]]
605 } 633 }
606 634
607 define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) { 635 define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) {
608 entry: 636 entry:
609 %res = icmp eq <8 x i16> %a, %b 637 %res = icmp eq <8 x i16> %a, %b
610 ret <8 x i1> %res 638 ret <8 x i1> %res
611 ; CHECK-LABEL: test_icmp_v8i16_eq 639 ; CHECK-LABEL: test_icmp_v8i16_eq
612 ; CHECK: pcmpeqw 640 ; CHECK: pcmpeqw
613 641
614 ; MIPS32-LABEL: test_icmp_v8i16_eq 642 ; MIPS32-LABEL: test_icmp_v8i16_eq
615 ; MIPS32: lw [[B_E0:.*]], 643 ; MIPS32: lw [[T0:.*]],
616 ; MIPS32: lw [[B_E1:.*]], 644 ; MIPS32: lw [[T1:.*]],
617 ; MIPS32: lw [[B_E2:.*]], 645 ; MIPS32: lw [[T2:.*]],
618 ; MIPS32: lw [[B_E3:.*]], 646 ; MIPS32: lw [[T3:.*]],
619 ; MIPS32: move [[T1_E0:.*]],zero 647 ; MIPS32: move [[T4:.*]],zero
620 ; MIPS32: move [[T1_E1:.*]],zero 648 ; MIPS32: move [[T5:.*]],zero
621 ; MIPS32: move [[T1_E2:.*]],zero 649 ; MIPS32: move [[T6:.*]],zero
622 ; MIPS32: move [[T1_E3:.*]],zero 650 ; MIPS32: move [[T7:.*]],zero
623 ; *** icmp a[0] and b[0] *** 651 ; MIPS32: move [[T8:.*]],a0
624 ; MIPS32: andi [[T2:.*]],a0,0xffff 652 ; MIPS32: andi [[T8]],[[T8]],0xffff
625 ; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff 653 ; MIPS32: move [[T9:.*]],[[T0]]
654 ; MIPS32: andi [[T9]],[[T9]],0xffff
655 ; MIPS32: sll [[T8]],[[T8]],0x10
656 ; MIPS32: sll [[T9]],[[T9]],0x10
657 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
658 ; MIPS32: sltiu [[T8]],[[T8]],1
659 ; MIPS32: andi [[T8]],[[T8]],0xffff
660 ; MIPS32: srl [[T4]],[[T4]],0x10
661 ; MIPS32: sll [[T4]],[[T4]],0x10
662 ; MIPS32: or [[T8]],[[T8]],[[T4]]
663 ; MIPS32: srl [[T10:.*]],a0,0x10
664 ; MIPS32: srl [[T0]],[[T0]],0x10
665 ; MIPS32: sll [[T10]],[[T10]],0x10
666 ; MIPS32: sll [[T0]],[[T0]],0x10
667 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
668 ; MIPS32: sltiu [[T10]],[[T10]],1
669 ; MIPS32: sll [[T10]],[[T10]],0x10
670 ; MIPS32: sll [[T8]],[[T8]],0x10
671 ; MIPS32: srl [[T8]],[[T8]],0x10
672 ; MIPS32: or [[T10]],[[T10]],[[T8]]
673 ; MIPS32: move [[T0]],a1
674 ; MIPS32: andi [[T0]],[[T0]],0xffff
675 ; MIPS32: move [[T4]],[[T1]]
676 ; MIPS32: andi [[T4]],[[T4]],0xffff
677 ; MIPS32: sll [[T0]],[[T0]],0x10
678 ; MIPS32: sll [[T4]],[[T4]],0x10
679 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
680 ; MIPS32: sltiu [[T0]],[[T0]],1
681 ; MIPS32: andi [[T0]],[[T0]],0xffff
682 ; MIPS32: srl [[T5]],[[T5]],0x10
683 ; MIPS32: sll [[T5]],[[T5]],0x10
684 ; MIPS32: or [[T0]],[[T0]],[[T5]]
685 ; MIPS32: srl [[T11:.*]],a1,0x10
686 ; MIPS32: srl [[T1]],[[T1]],0x10
687 ; MIPS32: sll [[T11]],[[T11]],0x10
688 ; MIPS32: sll [[T1]],[[T1]],0x10
689 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
690 ; MIPS32: sltiu [[T11]],[[T11]],1
691 ; MIPS32: sll [[T11]],[[T11]],0x10
692 ; MIPS32: sll [[T0]],[[T0]],0x10
693 ; MIPS32: srl [[T0]],[[T0]],0x10
694 ; MIPS32: or [[T11]],[[T11]],[[T0]]
695 ; MIPS32: move [[T0]],a2
696 ; MIPS32: andi [[T0]],[[T0]],0xffff
697 ; MIPS32: move [[T1]],[[T2]]
698 ; MIPS32: andi [[T1]],[[T1]],0xffff
699 ; MIPS32: sll [[T0]],[[T0]],0x10
700 ; MIPS32: sll [[T1]],[[T1]],0x10
701 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
702 ; MIPS32: sltiu [[T0]],[[T0]],1
703 ; MIPS32: andi [[T0]],[[T0]],0xffff
704 ; MIPS32: srl [[T6]],[[T6]],0x10
705 ; MIPS32: sll [[T6]],[[T6]],0x10
706 ; MIPS32: or [[T0]],[[T0]],[[T6]]
707 ; MIPS32: srl [[T12:.*]],a2,0x10
708 ; MIPS32: srl [[T2]],[[T2]],0x10
709 ; MIPS32: sll [[T12]],[[T12]],0x10
626 ; MIPS32: sll [[T2]],[[T2]],0x10 710 ; MIPS32: sll [[T2]],[[T2]],0x10
711 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
712 ; MIPS32: sltiu [[T12]],[[T12]],1
713 ; MIPS32: sll [[T12]],[[T12]],0x10
714 ; MIPS32: sll [[T0]],[[T0]],0x10
715 ; MIPS32: srl [[T0]],[[T0]],0x10
716 ; MIPS32: or [[T12]],[[T12]],[[T0]]
717 ; MIPS32: move [[T0]],a3
718 ; MIPS32: andi [[T0]],[[T0]],0xffff
719 ; MIPS32: move [[T1]],[[T3]]
720 ; MIPS32: andi [[T1]],[[T1]],0xffff
721 ; MIPS32: sll [[T0]],[[T0]],0x10
722 ; MIPS32: sll [[T1]],[[T1]],0x10
723 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
724 ; MIPS32: sltiu [[T0]],[[T0]],1
725 ; MIPS32: andi [[T0]],[[T0]],0xffff
726 ; MIPS32: srl [[T7]],[[T7]],0x10
727 ; MIPS32: sll [[T7]],[[T7]],0x10
728 ; MIPS32: or [[T0]],[[T0]],[[T7]]
729 ; MIPS32: srl [[T13:.*]],a3,0x10
730 ; MIPS32: srl [[T3]],[[T3]],0x10
731 ; MIPS32: sll [[T13]],[[T13]],0x10
627 ; MIPS32: sll [[T3]],[[T3]],0x10 732 ; MIPS32: sll [[T3]],[[T3]],0x10
628 ; MIPS32: xor [[T2]],[[T2]],[[T3]] 733 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
629 ; MIPS32: sltiu [[T2]],[[T2]],1 734 ; MIPS32: sltiu [[T13]],[[T13]],1
630 ; MIPS32: andi [[T2]],[[T2]],0xffff 735 ; MIPS32: sll [[T13]],[[T13]],0x10
631 ; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10 736 ; MIPS32: sll [[T0]],[[T0]],0x10
632 ; MIPS32: sll [[T4]],[[T4]],0x10 737 ; MIPS32: srl [[T0]],[[T0]],0x10
633 ; MIPS32: or [[T2]],[[T2]],[[T4]] 738 ; MIPS32: or [[T13]],[[T13]],[[T0]]
634 ; *** icmp a[1] and b[1] *** 739 ; MIPS32: move v0,[[T10]]
635 ; MIPS32: srl [[R_E0:.*]],a0,0x10 740 ; MIPS32: move v1,[[T11]]
636 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 741 ; MIPS32: move a0,[[T12]]
637 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10 742 ; MIPS32: move a1,[[T13]]
638 ; MIPS32: sll [[T5]],[[T5]],0x10
639 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
640 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1
641 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
642 ; MIPS32: sll [[T2]],[[T2]],0x10
643 ; MIPS32: srl [[T2]],[[T2]],0x10
644 ; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
645 ; *** icmp a[2] and b[2] ***
646 ; MIPS32: andi [[T2:.*]],a1,0xffff
647 ; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
648 ; MIPS32: sll [[T2]],[[T2]],0x10
649 ; MIPS32: sll [[T3]],[[T3]],0x10
650 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
651 ; MIPS32: sltiu [[T2]],[[T2]],1
652 ; MIPS32: andi [[T2]],[[T2]],0xffff
653 ; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
654 ; MIPS32: sll [[T4]],[[T4]],0x10
655 ; MIPS32: or [[T2]],[[T2]],[[T4]]
656 ; *** icmp a[3] and b[3] ***
657 ; MIPS32: srl [[R_E1:.*]],a1,0x10
658 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
659 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
660 ; MIPS32: sll [[T5]],[[T5]],0x10
661 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
662 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1
663 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
664 ; MIPS32: sll [[T2]],[[T2]],0x10
665 ; MIPS32: srl [[T2]],[[T2]],0x10
666 ; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
667 ; *** icmp a[4] and b[4] ***
668 ; MIPS32: andi [[T2:.*]],a2,0xffff
669 ; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
670 ; MIPS32: sll [[T2]],[[T2]],0x10
671 ; MIPS32: sll [[T3]],[[T3]],0x10
672 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
673 ; MIPS32: sltiu [[T2]],[[T2]],1
674 ; MIPS32: andi [[T2]],[[T2]],0xffff
675 ; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
676 ; MIPS32: sll [[T4]],[[T4]],0x10
677 ; MIPS32: or [[T2]],[[T2]],[[T4]]
678 ; *** icmp a[5] and b[5] ***
679 ; MIPS32: srl [[R_E2:.*]],a2,0x10
680 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
681 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
682 ; MIPS32: sll [[T5]],[[T5]],0x10
683 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
684 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1
685 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
686 ; MIPS32: sll [[T2]],[[T2]],0x10
687 ; MIPS32: srl [[T2]],[[T2]],0x10
688 ; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
689 ; *** icmp a[6] and b[6] ***
690 ; MIPS32: andi [[T2:.*]],a3,0xffff
691 ; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
692 ; MIPS32: sll [[T2]],[[T2]],0x10
693 ; MIPS32: sll [[T3]],[[T3]],0x10
694 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
695 ; MIPS32: sltiu [[T2]],[[T2]],1
696 ; MIPS32: andi [[T2]],[[T2]],0xffff
697 ; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
698 ; MIPS32: sll [[T5]],[[T5]],0x10
699 ; MIPS32: or [[T2]],[[T2]],[[T5]]
700 ; *** icmp a[7] and b[7] ***
701 ; MIPS32: srl [[R_E3:.*]],a3,0x10
702 ; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
703 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
704 ; MIPS32: sll [[T6]],[[T6]],0x10
705 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
706 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1
707 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
708 ; MIPS32: sll [[T2]],[[T2]],0x10
709 ; MIPS32: srl [[T2]],[[T2]],0x10
710 ; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
711 ; *** move result to $2:$3:$4:$5 ***
712 ; MIPS32: move v0,[[R_E0]]
713 ; MIPS32: move v1,[[R_E1]]
714 ; MIPS32: move a0,[[R_E2]]
715 ; MIPS32: move a1,[[R_E3]]
716 } 743 }
717 744
718 define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) { 745 define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) {
719 entry: 746 entry:
720 %res = icmp ne <8 x i16> %a, %b 747 %res = icmp ne <8 x i16> %a, %b
721 ret <8 x i1> %res 748 ret <8 x i1> %res
722 ; CHECK-LABEL: test_icmp_v8i16_ne 749 ; CHECK-LABEL: test_icmp_v8i16_ne
723 ; CHECK: pcmpeqw 750 ; CHECK: pcmpeqw
724 ; CHECK: pxor 751 ; CHECK: pxor
725 752
726 ; MIPS32-LABEL: test_icmp_v8i16_ne 753 ; MIPS32-LABEL: test_icmp_v8i16_ne
727 ; MIPS32: lw [[B_E0:.*]], 754 ; MIPS32: lw [[T0:.*]],
728 ; MIPS32: lw [[B_E1:.*]], 755 ; MIPS32: lw [[T1:.*]],
729 ; MIPS32: lw [[B_E2:.*]], 756 ; MIPS32: lw [[T2:.*]],
730 ; MIPS32: lw [[B_E3:.*]], 757 ; MIPS32: lw [[T3:.*]],
731 ; MIPS32: move [[T1_E0:.*]],zero 758 ; MIPS32: move [[T4:.*]],zero
732 ; MIPS32: move [[T1_E1:.*]],zero 759 ; MIPS32: move [[T5:.*]],zero
733 ; MIPS32: move [[T1_E2:.*]],zero 760 ; MIPS32: move [[T6:.*]],zero
734 ; MIPS32: move [[T1_E3:.*]],zero 761 ; MIPS32: move [[T7:.*]],zero
735 ; *** icmp a[0] and b[0] *** 762 ; MIPS32: move [[T8:.*]],a0
736 ; MIPS32: andi [[T2:.*]],a0,0xffff 763 ; MIPS32: andi [[T8]],[[T8]],0xffff
737 ; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff 764 ; MIPS32: move [[T9:.*]],[[T0]]
765 ; MIPS32: andi [[T9]],[[T9]],0xffff
766 ; MIPS32: sll [[T8]],[[T8]],0x10
767 ; MIPS32: sll [[T9]],[[T9]],0x10
768 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
769 ; MIPS32: sltu [[T8]],zero,[[T8]]
770 ; MIPS32: andi [[T8]],[[T8]],0xffff
771 ; MIPS32: srl [[T4]],[[T4]],0x10
772 ; MIPS32: sll [[T4]],[[T4]],0x10
773 ; MIPS32: or [[T8]],[[T8]],[[T4]]
774 ; MIPS32: srl [[T10:.*]],a0,0x10
775 ; MIPS32: srl [[T0]],[[T0]],0x10
776 ; MIPS32: sll [[T10]],[[T10]],0x10
777 ; MIPS32: sll [[T0]],[[T0]],0x10
778 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
779 ; MIPS32: sltu [[T10]],zero,[[T10]]
780 ; MIPS32: sll [[T10]],[[T10]],0x10
781 ; MIPS32: sll [[T8]],[[T8]],0x10
782 ; MIPS32: srl [[T8]],[[T8]],0x10
783 ; MIPS32: or [[T10]],[[T10]],[[T8]]
784 ; MIPS32: move [[T0]],a1
785 ; MIPS32: andi [[T0]],[[T0]],0xffff
786 ; MIPS32: move [[T4]],[[T1]]
787 ; MIPS32: andi [[T4]],[[T4]],0xffff
788 ; MIPS32: sll [[T0]],[[T0]],0x10
789 ; MIPS32: sll [[T4]],[[T4]],0x10
790 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
791 ; MIPS32: sltu [[T0]],zero,[[T0]]
792 ; MIPS32: andi [[T0]],[[T0]],0xffff
793 ; MIPS32: srl [[T5]],[[T5]],0x10
794 ; MIPS32: sll [[T5]],[[T5]],0x10
795 ; MIPS32: or [[T0]],[[T0]],[[T5]]
796 ; MIPS32: srl [[T11:.*]],a1,0x10
797 ; MIPS32: srl [[T1]],[[T1]],0x10
798 ; MIPS32: sll [[T11]],[[T11]],0x10
799 ; MIPS32: sll [[T1]],[[T1]],0x10
800 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
801 ; MIPS32: sltu [[T11]],zero,[[T11]]
802 ; MIPS32: sll [[T11]],[[T11]],0x10
803 ; MIPS32: sll [[T0]],[[T0]],0x10
804 ; MIPS32: srl [[T0]],[[T0]],0x10
805 ; MIPS32: or [[T11]],[[T11]],[[T0]]
806 ; MIPS32: move [[T0]],a2
807 ; MIPS32: andi [[T0]],[[T0]],0xffff
808 ; MIPS32: move [[T1]],[[T2]]
809 ; MIPS32: andi [[T1]],[[T1]],0xffff
810 ; MIPS32: sll [[T0]],[[T0]],0x10
811 ; MIPS32: sll [[T1]],[[T1]],0x10
812 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
813 ; MIPS32: sltu [[T0]],zero,[[T0]]
814 ; MIPS32: andi [[T0]],[[T0]],0xffff
815 ; MIPS32: srl [[T6]],[[T6]],0x10
816 ; MIPS32: sll [[T6]],[[T6]],0x10
817 ; MIPS32: or [[T0]],[[T0]],[[T6]]
818 ; MIPS32: srl [[T12:.*]],a2,0x10
819 ; MIPS32: srl [[T2]],[[T2]],0x10
820 ; MIPS32: sll [[T12]],[[T12]],0x10
738 ; MIPS32: sll [[T2]],[[T2]],0x10 821 ; MIPS32: sll [[T2]],[[T2]],0x10
822 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
823 ; MIPS32: sltu [[T12]],zero,[[T12]]
824 ; MIPS32: sll [[T12]],[[T12]],0x10
825 ; MIPS32: sll [[T0]],[[T0]],0x10
826 ; MIPS32: srl [[T0]],[[T0]],0x10
827 ; MIPS32: or [[T12]],[[T12]],[[T0]]
828 ; MIPS32: move [[T0]],a3
829 ; MIPS32: andi [[T0]],[[T0]],0xffff
830 ; MIPS32: move [[T1]],[[T3]]
831 ; MIPS32: andi [[T1]],[[T1]],0xffff
832 ; MIPS32: sll [[T0]],[[T0]],0x10
833 ; MIPS32: sll [[T1]],[[T1]],0x10
834 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
835 ; MIPS32: sltu [[T0]],zero,[[T0]]
836 ; MIPS32: andi [[T0]],[[T0]],0xffff
837 ; MIPS32: srl [[T7]],[[T7]],0x10
838 ; MIPS32: sll [[T7]],[[T7]],0x10
839 ; MIPS32: or [[T0]],[[T0]],[[T7]]
840 ; MIPS32: srl [[T13:.*]],a3,0x10
841 ; MIPS32: srl [[T3]],[[T3]],0x10
842 ; MIPS32: sll [[T13]],[[T13]],0x10
739 ; MIPS32: sll [[T3]],[[T3]],0x10 843 ; MIPS32: sll [[T3]],[[T3]],0x10
740 ; MIPS32: xor [[T2]],[[T2]],[[T3]] 844 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
741 ; MIPS32: sltu [[T2]],zero,[[T2]] 845 ; MIPS32: sltu [[T13]],zero,[[T13]]
742 ; MIPS32: andi [[T2]],[[T2]],0xffff 846 ; MIPS32: sll [[T13]],[[T13]],0x10
743 ; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10 847 ; MIPS32: sll [[T0]],[[T0]],0x10
744 ; MIPS32: sll [[T4]],[[T4]],0x10 848 ; MIPS32: srl [[T0]],[[T0]],0x10
745 ; MIPS32: or [[T2]],[[T2]],[[T4]] 849 ; MIPS32: or [[T13]],[[T13]],[[T0]]
746 ; *** icmp a[1] and b[1] *** 850 ; MIPS32: move v0,[[T10]]
747 ; MIPS32: srl [[R_E0:.*]],a0,0x10 851 ; MIPS32: move v1,[[T11]]
748 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 852 ; MIPS32: move a0,[[T12]]
749 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10 853 ; MIPS32: move a1,[[T13]]
750 ; MIPS32: sll [[T5]],[[T5]],0x10
751 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
752 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
753 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
754 ; MIPS32: sll [[T2]],[[T2]],0x10
755 ; MIPS32: srl [[T2]],[[T2]],0x10
756 ; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
757 ; *** icmp a[2] and b[2] ***
758 ; MIPS32: andi [[T2:.*]],a1,0xffff
759 ; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
760 ; MIPS32: sll [[T2]],[[T2]],0x10
761 ; MIPS32: sll [[T3]],[[T3]],0x10
762 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
763 ; MIPS32: sltu [[T2]],zero,[[T2]]
764 ; MIPS32: andi [[T2]],[[T2]],0xffff
765 ; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
766 ; MIPS32: sll [[T4]],[[T4]],0x10
767 ; MIPS32: or [[T2]],[[T2]],[[T4]]
768 ; *** icmp a[3] and b[3] ***
769 ; MIPS32: srl [[R_E1:.*]],a1,0x10
770 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
771 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
772 ; MIPS32: sll [[T5]],[[T5]],0x10
773 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
774 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
775 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
776 ; MIPS32: sll [[T2]],[[T2]],0x10
777 ; MIPS32: srl [[T2]],[[T2]],0x10
778 ; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
779 ; *** icmp a[4] and b[4] ***
780 ; MIPS32: andi [[T2:.*]],a2,0xffff
781 ; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
782 ; MIPS32: sll [[T2]],[[T2]],0x10
783 ; MIPS32: sll [[T3]],[[T3]],0x10
784 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
785 ; MIPS32: sltu [[T2]],zero,[[T2]]
786 ; MIPS32: andi [[T2]],[[T2]],0xffff
787 ; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
788 ; MIPS32: sll [[T4]],[[T4]],0x10
789 ; MIPS32: or [[T2]],[[T2]],[[T4]]
790 ; *** icmp a[5] and b[5] ***
791 ; MIPS32: srl [[R_E2:.*]],a2,0x10
792 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
793 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
794 ; MIPS32: sll [[T5]],[[T5]],0x10
795 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
796 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
797 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
798 ; MIPS32: sll [[T2]],[[T2]],0x10
799 ; MIPS32: srl [[T2]],[[T2]],0x10
800 ; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
801 ; *** icmp a[6] and b[6] ***
802 ; MIPS32: andi [[T2:.*]],a3,0xffff
803 ; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
804 ; MIPS32: sll [[T2]],[[T2]],0x10
805 ; MIPS32: sll [[T3]],[[T3]],0x10
806 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
807 ; MIPS32: sltu [[T2]],zero,[[T2]]
808 ; MIPS32: andi [[T2]],[[T2]],0xffff
809 ; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
810 ; MIPS32: sll [[T5]],[[T5]],0x10
811 ; MIPS32: or [[T2]],[[T2]],[[T5]]
812 ; *** icmp a[7] and b[7] ***
813 ; MIPS32: srl [[R_E3:.*]],a3,0x10
814 ; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
815 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
816 ; MIPS32: sll [[T6]],[[T6]],0x10
817 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
818 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
819 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
820 ; MIPS32: sll [[T2]],[[T2]],0x10
821 ; MIPS32: srl [[T2]],[[T2]],0x10
822 ; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
823 ; *** move result to $2:$3:$4:$5 ***
824 ; MIPS32: move v0,[[R_E0]]
825 ; MIPS32: move v1,[[R_E1]]
826 ; MIPS32: move a0,[[R_E2]]
827 ; MIPS32: move a1,[[R_E3]]
828 } 854 }
829 855
830 define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) { 856 define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) {
831 entry: 857 entry:
832 %res = icmp sgt <8 x i16> %a, %b 858 %res = icmp sgt <8 x i16> %a, %b
833 ret <8 x i1> %res 859 ret <8 x i1> %res
834 ; CHECK-LABEL: test_icmp_v8i16_sgt 860 ; CHECK-LABEL: test_icmp_v8i16_sgt
835 ; CHECK: pcmpgtw 861 ; CHECK: pcmpgtw
836 862
837 ; MIPS32-LABEL: test_icmp_v8i16_sgt 863 ; MIPS32-LABEL: test_icmp_v8i16_sgt
838 ; MIPS32: lw [[B_E0:.*]], 864 ; MIPS32: lw [[T0:.*]],
839 ; MIPS32: lw [[B_E1:.*]], 865 ; MIPS32: lw [[T1:.*]],
840 ; MIPS32: lw [[B_E2:.*]], 866 ; MIPS32: lw [[T2:.*]],
841 ; MIPS32: lw [[B_E3:.*]], 867 ; MIPS32: lw [[T3:.*]],
842 ; MIPS32: move [[T1_E0:.*]],zero 868 ; MIPS32: move [[T4:.*]],zero
843 ; MIPS32: move [[T1_E1:.*]],zero 869 ; MIPS32: move [[T5:.*]],zero
844 ; MIPS32: move [[T1_E2:.*]],zero 870 ; MIPS32: move [[T6:.*]],zero
845 ; MIPS32: move [[T1_E3:.*]],zero 871 ; MIPS32: move [[T7:.*]],zero
846 ; MIPS32: andi [[T1:.*]],a0,0xffff 872 ; MIPS32: move [[T8:.*]],a0
847 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 873 ; MIPS32: andi [[T8]],[[T8]],0xffff
874 ; MIPS32: move [[T9:.*]],[[T0]]
875 ; MIPS32: andi [[T9]],[[T9]],0xffff
876 ; MIPS32: sll [[T8]],[[T8]],0x10
877 ; MIPS32: sll [[T9]],[[T9]],0x10
878 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
879 ; MIPS32: andi [[T9]],[[T9]],0xffff
880 ; MIPS32: srl [[T4]],[[T4]],0x10
881 ; MIPS32: sll [[T4]],[[T4]],0x10
882 ; MIPS32: or [[T9]],[[T9]],[[T4]]
883 ; MIPS32: srl [[T10:.*]],a0,0x10
884 ; MIPS32: srl [[T0]],[[T0]],0x10
885 ; MIPS32: sll [[T10]],[[T10]],0x10
886 ; MIPS32: sll [[T0]],[[T0]],0x10
887 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
888 ; MIPS32: sll [[T0]],[[T0]],0x10
889 ; MIPS32: sll [[T9]],[[T9]],0x10
890 ; MIPS32: srl [[T9]],[[T9]],0x10
891 ; MIPS32: or v0,[[T0]],[[T9]]
892 ; MIPS32: move [[T10]],a1
893 ; MIPS32: andi [[T10]],[[T10]],0xffff
894 ; MIPS32: move [[T4]],[[T1]]
895 ; MIPS32: andi [[T4]],[[T4]],0xffff
896 ; MIPS32: sll [[T10]],[[T10]],0x10
897 ; MIPS32: sll [[T4]],[[T4]],0x10
898 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
899 ; MIPS32: andi [[T4]],[[T4]],0xffff
900 ; MIPS32: srl [[T5]],[[T5]],0x10
901 ; MIPS32: sll [[T5]],[[T5]],0x10
902 ; MIPS32: or [[T4]],[[T4]],[[T5]]
903 ; MIPS32: srl [[T11:.*]],a1,0x10
904 ; MIPS32: srl [[T1]],[[T1]],0x10
905 ; MIPS32: sll [[T11]],[[T11]],0x10
848 ; MIPS32: sll [[T1]],[[T1]],0x10 906 ; MIPS32: sll [[T1]],[[T1]],0x10
849 ; MIPS32: sll [[T2]],[[T2]],0x10 907 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
850 ; MIPS32: slt [[T2]],[[T2]],[[T1]] 908 ; MIPS32: sll [[T1]],[[T1]],0x10
851 ; MIPS32: andi [[T2]],[[T2]],0xffff
852 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
853 ; MIPS32: sll [[T3]],[[T3]],0x10
854 ; MIPS32: or [[T2]],[[T2]],[[T3]]
855 ; MIPS32: srl [[T4:.*]],a0,0x10
856 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
857 ; MIPS32: sll [[T4]],[[T4]],0x10 909 ; MIPS32: sll [[T4]],[[T4]],0x10
858 ; MIPS32: sll [[T5]],[[T5]],0x10 910 ; MIPS32: srl [[T4]],[[T4]],0x10
859 ; MIPS32: slt [[T5]],[[T5]],[[T4]] 911 ; MIPS32: or v1,[[T1]],[[T4]]
860 ; MIPS32: sll [[T5]],[[T5]],0x10 912 ; MIPS32: move [[T10]],a2
861 ; MIPS32: sll [[T2]],[[T2]],0x10 913 ; MIPS32: andi [[T10]],[[T10]],0xffff
862 ; MIPS32: srl [[T2]],[[T2]],0x10 914 ; MIPS32: move [[T11]],[[T2]]
863 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]] 915 ; MIPS32: andi [[T11]],[[T11]],0xffff
864 ; MIPS32: andi [[T4]],a1,0xffff
865 ; MIPS32: andi [[T3]],[[B_E1]],0xffff
866 ; MIPS32: sll [[T4]],[[T4]],0x10
867 ; MIPS32: sll [[T3]],[[T3]],0x10
868 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
869 ; MIPS32: andi [[T3]],[[T3]],0xffff
870 ; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
871 ; MIPS32: sll [[T6]],[[T6]],0x10
872 ; MIPS32: or [[T3]],[[T3]],[[T6]]
873 ; MIPS32: srl [[T7:.*]],a1,0x10
874 ; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
875 ; MIPS32: sll [[T7]],[[T7]],0x10
876 ; MIPS32: sll [[T8]],[[T8]],0x10
877 ; MIPS32: slt [[T8]],[[T8]],[[T7]]
878 ; MIPS32: sll [[T8]],[[T8]],0x10
879 ; MIPS32: sll [[T3]],[[T3]],0x10
880 ; MIPS32: srl [[T3]],[[T3]],0x10
881 ; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
882 ; MIPS32: andi [[T4]],a2,0xffff
883 ; MIPS32: andi [[T7]],[[B_E2]],0xffff
884 ; MIPS32: sll [[T4]],[[T4]],0x10
885 ; MIPS32: sll [[T7]],[[T7]],0x10
886 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
887 ; MIPS32: andi [[T7]],[[T7]],0xffff
888 ; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
889 ; MIPS32: sll [[T9]],[[T9]],0x10
890 ; MIPS32: or [[T7]],[[T7]],[[T9]]
891 ; MIPS32: srl [[T10:.*]],a2,0x10
892 ; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
893 ; MIPS32: sll [[T10]],[[T10]],0x10 916 ; MIPS32: sll [[T10]],[[T10]],0x10
894 ; MIPS32: sll [[T11]],[[T11]],0x10 917 ; MIPS32: sll [[T11]],[[T11]],0x10
895 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 918 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
919 ; MIPS32: andi [[T11]],[[T11]],0xffff
920 ; MIPS32: srl [[T6]],[[T6]],0x10
921 ; MIPS32: sll [[T6]],[[T6]],0x10
922 ; MIPS32: or [[T11]],[[T11]],[[T6]]
923 ; MIPS32: srl [[T12:.*]],a2,0x10
924 ; MIPS32: srl [[T2]],[[T2]],0x10
925 ; MIPS32: sll [[T12]],[[T12]],0x10
926 ; MIPS32: sll [[T2]],[[T2]],0x10
927 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
928 ; MIPS32: sll [[T2]],[[T2]],0x10
896 ; MIPS32: sll [[T11]],[[T11]],0x10 929 ; MIPS32: sll [[T11]],[[T11]],0x10
930 ; MIPS32: srl [[T11]],[[T11]],0x10
931 ; MIPS32: or [[T2]],[[T2]],[[T11]]
932 ; MIPS32: move [[T10]],a3
933 ; MIPS32: andi [[T10]],[[T10]],0xffff
934 ; MIPS32: move [[T11]],[[T3]]
935 ; MIPS32: andi [[T11]],[[T11]],0xffff
936 ; MIPS32: sll [[T10]],[[T10]],0x10
937 ; MIPS32: sll [[T11]],[[T11]],0x10
938 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
939 ; MIPS32: andi [[T11]],[[T11]],0xffff
940 ; MIPS32: srl [[T7]],[[T7]],0x10
897 ; MIPS32: sll [[T7]],[[T7]],0x10 941 ; MIPS32: sll [[T7]],[[T7]],0x10
898 ; MIPS32: srl [[T7]],[[T7]],0x10 942 ; MIPS32: or [[T11]],[[T11]],[[T7]]
899 ; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
900 ; MIPS32: andi [[T4]],a3,0xffff
901 ; MIPS32: andi [[T7]],[[B_E3]],0xffff
902 ; MIPS32: sll [[T4]],[[T4]],0x10
903 ; MIPS32: sll [[T7]],[[T7]],0x10
904 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
905 ; MIPS32: andi [[T7]],[[T7]],0xffff
906 ; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
907 ; MIPS32: sll [[T12]],[[T12]],0x10
908 ; MIPS32: or [[T7]],[[T7]],[[T12]]
909 ; MIPS32: srl [[T13:.*]],a3,0x10 943 ; MIPS32: srl [[T13:.*]],a3,0x10
910 ; MIPS32: srl [[T14:.*]],[[B_E3]],0x10 944 ; MIPS32: srl [[T3]],[[T3]],0x10
911 ; MIPS32: sll [[T13]],[[T13]],0x10 945 ; MIPS32: sll [[T13]],[[T13]],0x10
912 ; MIPS32: sll [[T14]],[[T14]],0x10 946 ; MIPS32: sll [[T3]],[[T3]],0x10
913 ; MIPS32: slt [[T14]],[[T14]],[[T13]] 947 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
914 ; MIPS32: sll [[T14]],[[T14]],0x10 948 ; MIPS32: sll [[T3]],[[T3]],0x10
915 ; MIPS32: sll [[T7]],[[T7]],0x10 949 ; MIPS32: sll [[T11]],[[T11]],0x10
916 ; MIPS32: srl [[T7]],[[T7]],0x10 950 ; MIPS32: srl [[T11]],[[T11]],0x10
917 ; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]] 951 ; MIPS32: or [[T3]],[[T3]],[[T11]]
952 ; MIPS32: move a0,[[T2]]
953 ; MIPS32: move a1,[[T3]]
918 } 954 }
919 955
920 define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) { 956 define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) {
921 entry: 957 entry:
922 %res = icmp sle <8 x i16> %a, %b 958 %res = icmp sle <8 x i16> %a, %b
923 ret <8 x i1> %res 959 ret <8 x i1> %res
924 ; CHECK-LABEL: test_icmp_v8i16_sle 960 ; CHECK-LABEL: test_icmp_v8i16_sle
925 ; CHECK: pcmpgtw 961 ; CHECK: pcmpgtw
926 ; CHECK: pxor 962 ; CHECK: pxor
927 963
928 ; MIPS32-LABEL: test_icmp_v8i16_sle 964 ; MIPS32-LABEL: test_icmp_v8i16_sle
929 ; MIPS32: lw [[B_E0:.*]], 965 ; MIPS32: lw [[T0:.*]],
930 ; MIPS32: lw [[B_E1:.*]], 966 ; MIPS32: lw [[T1:.*]],
931 ; MIPS32: lw [[B_E2:.*]], 967 ; MIPS32: lw [[T2:.*]],
932 ; MIPS32: lw [[B_E3:.*]], 968 ; MIPS32: lw [[T3:.*]],
933 ; MIPS32: move [[T1_E0:.*]],zero 969 ; MIPS32: move [[T4:.*]],zero
934 ; MIPS32: move [[T1_E1:.*]],zero 970 ; MIPS32: move [[T5:.*]],zero
935 ; MIPS32: move [[T1_E2:.*]],zero 971 ; MIPS32: move [[T6:.*]],zero
936 ; MIPS32: move [[T1_E3:.*]],zero 972 ; MIPS32: move [[T7:.*]],zero
937 ; MIPS32: andi [[T1:.*]],a0,0xffff 973 ; MIPS32: move [[T8:.*]],a0
938 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 974 ; MIPS32: andi [[T8]],[[T8]],0xffff
975 ; MIPS32: move [[T9:.*]],[[T0]]
976 ; MIPS32: andi [[T9]],[[T9]],0xffff
977 ; MIPS32: sll [[T8]],[[T8]],0x10
978 ; MIPS32: sll [[T9]],[[T9]],0x10
979 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
980 ; MIPS32: xori [[T9]],[[T9]],0x1
981 ; MIPS32: andi [[T9]],[[T9]],0xffff
982 ; MIPS32: srl [[T4]],[[T4]],0x10
983 ; MIPS32: sll [[T4]],[[T4]],0x10
984 ; MIPS32: or [[T9]],[[T9]],[[T4]]
985 ; MIPS32: srl [[T10:.*]],a0,0x10
986 ; MIPS32: srl [[T0]],[[T0]],0x10
987 ; MIPS32: sll [[T10]],[[T10]],0x10
988 ; MIPS32: sll [[T0]],[[T0]],0x10
989 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
990 ; MIPS32: xori [[T0]],[[T0]],0x1
991 ; MIPS32: sll [[T0]],[[T0]],0x10
992 ; MIPS32: sll [[T9]],[[T9]],0x10
993 ; MIPS32: srl [[T9]],[[T9]],0x10
994 ; MIPS32: or v0,[[T0]],[[T9]]
995 ; MIPS32: move [[T10]],a1
996 ; MIPS32: andi [[T10]],[[T10]],0xffff
997 ; MIPS32: move [[T4]],[[T1]]
998 ; MIPS32: andi [[T4]],[[T4]],0xffff
999 ; MIPS32: sll [[T10]],[[T10]],0x10
1000 ; MIPS32: sll [[T4]],[[T4]],0x10
1001 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
1002 ; MIPS32: xori [[T4]],[[T4]],0x1
1003 ; MIPS32: andi [[T4]],[[T4]],0xffff
1004 ; MIPS32: srl [[T5]],[[T5]],0x10
1005 ; MIPS32: sll [[T5]],[[T5]],0x10
1006 ; MIPS32: or [[T4]],[[T4]],[[T5]]
1007 ; MIPS32: srl [[T11:.*]],a1,0x10
1008 ; MIPS32: srl [[T1]],[[T1]],0x10
1009 ; MIPS32: sll [[T11]],[[T11]],0x10
939 ; MIPS32: sll [[T1]],[[T1]],0x10 1010 ; MIPS32: sll [[T1]],[[T1]],0x10
940 ; MIPS32: sll [[T2]],[[T2]],0x10 1011 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
941 ; MIPS32: slt [[T2]],[[T2]],[[T1]] 1012 ; MIPS32: xori [[T1]],[[T1]],0x1
942 ; MIPS32: xori [[T2]],[[T2]],0x1 1013 ; MIPS32: sll [[T1]],[[T1]],0x10
943 ; MIPS32: andi [[T2]],[[T2]],0xffff
944 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
945 ; MIPS32: sll [[T3]],[[T3]],0x10
946 ; MIPS32: or [[T2]],[[T2]],[[T3]]
947 ; MIPS32: srl [[T4:.*]],a0,0x10
948 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
949 ; MIPS32: sll [[T4]],[[T4]],0x10 1014 ; MIPS32: sll [[T4]],[[T4]],0x10
950 ; MIPS32: sll [[T5]],[[T5]],0x10 1015 ; MIPS32: srl [[T4]],[[T4]],0x10
951 ; MIPS32: slt [[T5]],[[T5]],[[T4]] 1016 ; MIPS32: or v1,[[T1]],[[T4]]
952 ; MIPS32: xori [[T5]],[[T5]],0x1 1017 ; MIPS32: move [[T10]],a2
953 ; MIPS32: sll [[T5]],[[T5]],0x10 1018 ; MIPS32: andi [[T10]],[[T10]],0xffff
954 ; MIPS32: sll [[T2]],[[T2]],0x10 1019 ; MIPS32: move [[T11]],[[T2]]
955 ; MIPS32: srl [[T2]],[[T2]],0x10 1020 ; MIPS32: andi [[T11]],[[T11]],0xffff
956 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
957 ; MIPS32: andi [[T4]],a1,0xffff
958 ; MIPS32: andi [[T3]],[[B_E1]],0xffff
959 ; MIPS32: sll [[T4]],[[T4]],0x10
960 ; MIPS32: sll [[T3]],[[T3]],0x10
961 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
962 ; MIPS32: xori [[T3]],[[T3]],0x1
963 ; MIPS32: andi [[T3]],[[T3]],0xffff
964 ; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
965 ; MIPS32: sll [[T6]],[[T6]],0x10
966 ; MIPS32: or [[T3]],[[T3]],[[T6]]
967 ; MIPS32: srl [[T7:.*]],a1,0x10
968 ; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
969 ; MIPS32: sll [[T7]],[[T7]],0x10
970 ; MIPS32: sll [[T8]],[[T8]],0x10
971 ; MIPS32: slt [[T8]],[[T8]],[[T7]]
972 ; MIPS32: xori [[T8]],[[T8]],0x1
973 ; MIPS32: sll [[T8]],[[T8]],0x10
974 ; MIPS32: sll [[T3]],[[T3]],0x10
975 ; MIPS32: srl [[T3]],[[T3]],0x10
976 ; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
977 ; MIPS32: andi [[T4]],a2,0xffff
978 ; MIPS32: andi [[T7]],[[B_E2]],0xffff
979 ; MIPS32: sll [[T4]],[[T4]],0x10
980 ; MIPS32: sll [[T7]],[[T7]],0x10
981 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
982 ; MIPS32: xori [[T7]],[[T7]],0x1
983 ; MIPS32: andi [[T7]],[[T7]],0xffff
984 ; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
985 ; MIPS32: sll [[T9]],[[T9]],0x10
986 ; MIPS32: or [[T7]],[[T7]],[[T9]]
987 ; MIPS32: srl [[T10:.*]],a2,0x10
988 ; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
989 ; MIPS32: sll [[T10]],[[T10]],0x10 1021 ; MIPS32: sll [[T10]],[[T10]],0x10
990 ; MIPS32: sll [[T11]],[[T11]],0x10 1022 ; MIPS32: sll [[T11]],[[T11]],0x10
991 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 1023 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
992 ; MIPS32: xori [[T11]],[[T11]],0x1 1024 ; MIPS32: xori [[T11]],[[T11]],0x1
1025 ; MIPS32: andi [[T11]],[[T11]],0xffff
1026 ; MIPS32: srl [[T6]],[[T6]],0x10
1027 ; MIPS32: sll [[T6]],[[T6]],0x10
1028 ; MIPS32: or [[T11]],[[T11]],[[T6]]
1029 ; MIPS32: srl [[T12:.*]],a2,0x10
1030 ; MIPS32: srl [[T2]],[[T2]],0x10
1031 ; MIPS32: sll [[T12]],[[T12]],0x10
1032 ; MIPS32: sll [[T2]],[[T2]],0x10
1033 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
1034 ; MIPS32: xori [[T2]],[[T2]],0x1
1035 ; MIPS32: sll [[T2]],[[T2]],0x10
993 ; MIPS32: sll [[T11]],[[T11]],0x10 1036 ; MIPS32: sll [[T11]],[[T11]],0x10
1037 ; MIPS32: srl [[T11]],[[T11]],0x10
1038 ; MIPS32: or [[T2]],[[T2]],[[T11]]
1039 ; MIPS32: move [[T10]],a3
1040 ; MIPS32: andi [[T10]],[[T10]],0xffff
1041 ; MIPS32: move [[T11]],[[T3]]
1042 ; MIPS32: andi [[T11]],[[T11]],0xffff
1043 ; MIPS32: sll [[T10]],[[T10]],0x10
1044 ; MIPS32: sll [[T11]],[[T11]],0x10
1045 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
1046 ; MIPS32: xori [[T11]],[[T11]],0x1
1047 ; MIPS32: andi [[T11]],[[T11]],0xffff
1048 ; MIPS32: srl [[T7]],[[T7]],0x10
994 ; MIPS32: sll [[T7]],[[T7]],0x10 1049 ; MIPS32: sll [[T7]],[[T7]],0x10
995 ; MIPS32: srl [[T7]],[[T7]],0x10 1050 ; MIPS32: or [[T11]],[[T11]],[[T7]]
996 ; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
997 ; MIPS32: andi [[T4]],a3,0xffff
998 ; MIPS32: andi [[T7]],[[B_E3]],0xffff
999 ; MIPS32: sll [[T4]],[[T4]],0x10
1000 ; MIPS32: sll [[T7]],[[T7]],0x10
1001 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
1002 ; MIPS32: xori [[T7]],[[T7]],0x1
1003 ; MIPS32: andi [[T7]],[[T7]],0xffff
1004 ; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
1005 ; MIPS32: sll [[T12]],[[T12]],0x10
1006 ; MIPS32: or [[T7]],[[T7]],[[T12]]
1007 ; MIPS32: srl [[T13:.*]],a3,0x10 1051 ; MIPS32: srl [[T13:.*]],a3,0x10
1008 ; MIPS32: srl [[T14:.*]],[[B_E3]],0x10 1052 ; MIPS32: srl [[T3]],[[T3]],0x10
1009 ; MIPS32: sll [[T13]],[[T13]],0x10 1053 ; MIPS32: sll [[T13]],[[T13]],0x10
1010 ; MIPS32: sll [[T14]],[[T14]],0x10 1054 ; MIPS32: sll [[T3]],[[T3]],0x10
1011 ; MIPS32: slt [[T14]],[[T14]],[[T13]] 1055 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
1012 ; MIPS32: xori [[T14]],[[T14]],0x1 1056 ; MIPS32: xori [[T3]],[[T3]],0x1
1013 ; MIPS32: sll [[T14]],[[T14]],0x10 1057 ; MIPS32: sll [[T3]],[[T3]],0x10
1014 ; MIPS32: sll [[T7]],[[T7]],0x10 1058 ; MIPS32: sll [[T11]],[[T11]],0x10
1015 ; MIPS32: srl [[T7]],[[T7]],0x10 1059 ; MIPS32: srl [[T11]],[[T11]],0x10
1016 ; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]] 1060 ; MIPS32: or [[T3]],[[T3]],[[T11]]
1061 ; MIPS32: move a0,[[T2]]
1062 ; MIPS32: move a1,[[T3]]
1017 } 1063 }
1018 1064
1019 define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) { 1065 define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) {
1020 entry: 1066 entry:
1021 %res = icmp slt <8 x i16> %a, %b 1067 %res = icmp slt <8 x i16> %a, %b
1022 ret <8 x i1> %res 1068 ret <8 x i1> %res
1023 ; CHECK-LABEL: test_icmp_v8i16_slt 1069 ; CHECK-LABEL: test_icmp_v8i16_slt
1024 ; CHECK: pcmpgtw 1070 ; CHECK: pcmpgtw
1025 1071
1026 ; MIPS32-LABEL: test_icmp_v8i16_slt 1072 ; MIPS32-LABEL: test_icmp_v8i16_slt
1027 ; MIPS32: lw [[B_E0:.*]], 1073 ; MIPS32: lw [[T0:.*]],
1028 ; MIPS32: lw [[B_E1:.*]], 1074 ; MIPS32: lw [[T1:.*]],
1029 ; MIPS32: lw [[B_E2:.*]], 1075 ; MIPS32: lw [[T2:.*]],
1030 ; MIPS32: lw [[B_E3:.*]], 1076 ; MIPS32: lw [[T3:.*]],
1031 ; MIPS32: move [[T1_E0:.*]],zero 1077 ; MIPS32: move [[T4:.*]],zero
1032 ; MIPS32: move [[T1_E1:.*]],zero 1078 ; MIPS32: move [[T5:.*]],zero
1033 ; MIPS32: move [[T1_E2:.*]],zero 1079 ; MIPS32: move [[T6:.*]],zero
1034 ; MIPS32: move [[T1_E3:.*]],zero 1080 ; MIPS32: move [[T7:.*]],zero
1035 ; MIPS32: andi [[T1:.*]],a0,0xffff 1081 ; MIPS32: move [[T8:.*]],a0
1036 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1082 ; MIPS32: andi [[T8]],[[T8]],0xffff
1083 ; MIPS32: move [[T9:.*]],[[T0]]
1084 ; MIPS32: andi [[T9]],[[T9]],0xffff
1085 ; MIPS32: sll [[T8]],[[T8]],0x10
1086 ; MIPS32: sll [[T9]],[[T9]],0x10
1087 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
1088 ; MIPS32: andi [[T8]],[[T8]],0xffff
1089 ; MIPS32: srl [[T4]],[[T4]],0x10
1090 ; MIPS32: sll [[T4]],[[T4]],0x10
1091 ; MIPS32: or [[T8]],[[T8]],[[T4]]
1092 ; MIPS32: srl [[T10:.*]],a0,0x10
1093 ; MIPS32: srl [[T0]],[[T0]],0x10
1094 ; MIPS32: sll [[T10]],[[T10]],0x10
1095 ; MIPS32: sll [[T0]],[[T0]],0x10
1096 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
1097 ; MIPS32: sll [[T10]],[[T10]],0x10
1098 ; MIPS32: sll [[T8]],[[T8]],0x10
1099 ; MIPS32: srl [[T8]],[[T8]],0x10
1100 ; MIPS32: or [[T10]],[[T10]],[[T8]]
1101 ; MIPS32: move [[T0]],a1
1102 ; MIPS32: andi [[T0]],[[T0]],0xffff
1103 ; MIPS32: move [[T4]],[[T1]]
1104 ; MIPS32: andi [[T4]],[[T4]],0xffff
1105 ; MIPS32: sll [[T0]],[[T0]],0x10
1106 ; MIPS32: sll [[T4]],[[T4]],0x10
1107 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
1108 ; MIPS32: andi [[T0]],[[T0]],0xffff
1109 ; MIPS32: srl [[T5]],[[T5]],0x10
1110 ; MIPS32: sll [[T5]],[[T5]],0x10
1111 ; MIPS32: or [[T0]],[[T0]],[[T5]]
1112 ; MIPS32: srl [[T11:.*]],a1,0x10
1113 ; MIPS32: srl [[T1]],[[T1]],0x10
1114 ; MIPS32: sll [[T11]],[[T11]],0x10
1037 ; MIPS32: sll [[T1]],[[T1]],0x10 1115 ; MIPS32: sll [[T1]],[[T1]],0x10
1116 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
1117 ; MIPS32: sll [[T11]],[[T11]],0x10
1118 ; MIPS32: sll [[T0]],[[T0]],0x10
1119 ; MIPS32: srl [[T0]],[[T0]],0x10
1120 ; MIPS32: or [[T11]],[[T11]],[[T0]]
1121 ; MIPS32: move [[T0]],a2
1122 ; MIPS32: andi [[T0]],[[T0]],0xffff
1123 ; MIPS32: move [[T1]],[[T2]]
1124 ; MIPS32: andi [[T1]],[[T1]],0xffff
1125 ; MIPS32: sll [[T0]],[[T0]],0x10
1126 ; MIPS32: sll [[T1]],[[T1]],0x10
1127 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
1128 ; MIPS32: andi [[T0]],[[T0]],0xffff
1129 ; MIPS32: srl [[T6]],[[T6]],0x10
1130 ; MIPS32: sll [[T6]],[[T6]],0x10
1131 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1132 ; MIPS32: srl [[T12:.*]],a2,0x10
1133 ; MIPS32: srl [[T2]],[[T2]],0x10
1134 ; MIPS32: sll [[T12]],[[T12]],0x10
1038 ; MIPS32: sll [[T2]],[[T2]],0x10 1135 ; MIPS32: sll [[T2]],[[T2]],0x10
1039 ; MIPS32: slt [[T1]],[[T1]],[[T2]] 1136 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
1137 ; MIPS32: sll [[T12]],[[T12]],0x10
1138 ; MIPS32: sll [[T0]],[[T0]],0x10
1139 ; MIPS32: srl [[T0]],[[T0]],0x10
1140 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1141 ; MIPS32: move [[T0]],a3
1142 ; MIPS32: andi [[T0]],[[T0]],0xffff
1143 ; MIPS32: move [[T1]],[[T3]]
1040 ; MIPS32: andi [[T1]],[[T1]],0xffff 1144 ; MIPS32: andi [[T1]],[[T1]],0xffff
1041 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1145 ; MIPS32: sll [[T0]],[[T0]],0x10
1146 ; MIPS32: sll [[T1]],[[T1]],0x10
1147 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
1148 ; MIPS32: andi [[T0]],[[T0]],0xffff
1149 ; MIPS32: srl [[T7]],[[T7]],0x10
1150 ; MIPS32: sll [[T7]],[[T7]],0x10
1151 ; MIPS32: or [[T0]],[[T0]],[[T7]]
1152 ; MIPS32: srl [[T13:.*]],a3,0x10
1153 ; MIPS32: srl [[T3]],[[T3]],0x10
1154 ; MIPS32: sll [[T13]],[[T13]],0x10
1042 ; MIPS32: sll [[T3]],[[T3]],0x10 1155 ; MIPS32: sll [[T3]],[[T3]],0x10
1043 ; MIPS32: or [[T1]],[[T1]],[[T3]] 1156 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
1044 ; MIPS32: srl [[T4:.*]],a0,0x10 1157 ; MIPS32: sll [[T13]],[[T13]],0x10
1045 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 1158 ; MIPS32: sll [[T0]],[[T0]],0x10
1046 ; MIPS32: sll [[T4]],[[T4]],0x10 1159 ; MIPS32: srl [[T0]],[[T0]],0x10
1047 ; MIPS32: sll [[T5]],[[T5]],0x10 1160 ; MIPS32: or [[T13]],[[T13]],[[T0]]
1048 ; MIPS32: slt [[T4]],[[T4]],[[T5]] 1161 ; MIPS32: move v0,[[T10]]
1049 ; MIPS32: sll [[T4]],[[T4]],0x10 1162 ; MIPS32: move v1,[[T11]]
1050 ; MIPS32: sll [[T1]],[[T1]],0x10 1163 ; MIPS32: move a0,[[T12]]
1051 ; MIPS32: srl [[T1]],[[T1]],0x10 1164 ; MIPS32: move a1,[[T13]]
1052 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1053 ; MIPS32: andi [[T1:.*]],a1,0xffff
1054 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1055 ; MIPS32: sll [[T1]],[[T1]],0x10
1056 ; MIPS32: sll [[T2]],[[T2]],0x10
1057 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1058 ; MIPS32: andi [[T1]],[[T1]],0xffff
1059 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1060 ; MIPS32: sll [[T3]],[[T3]],0x10
1061 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1062 ; MIPS32: srl [[T4:.*]],a1,0x10
1063 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1064 ; MIPS32: sll [[T4]],[[T4]],0x10
1065 ; MIPS32: sll [[T5]],[[T5]],0x10
1066 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1067 ; MIPS32: sll [[T4]],[[T4]],0x10
1068 ; MIPS32: sll [[T1]],[[T1]],0x10
1069 ; MIPS32: srl [[T1]],[[T1]],0x10
1070 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1071 ; MIPS32: andi [[T1:.*]],a2,0xffff
1072 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1073 ; MIPS32: sll [[T1]],[[T1]],0x10
1074 ; MIPS32: sll [[T2]],[[T2]],0x10
1075 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1076 ; MIPS32: andi [[T1]],[[T1]],0xffff
1077 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1078 ; MIPS32: sll [[T3]],[[T3]],0x10
1079 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1080 ; MIPS32: srl [[T4:.*]],a2,0x10
1081 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1082 ; MIPS32: sll [[T4]],[[T4]],0x10
1083 ; MIPS32: sll [[T5]],[[T5]],0x10
1084 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1085 ; MIPS32: sll [[T4]],[[T4]],0x10
1086 ; MIPS32: sll [[T1]],[[T1]],0x10
1087 ; MIPS32: srl [[T1]],[[T1]],0x10
1088 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1089 ; MIPS32: andi [[T1:.*]],a3,0xffff
1090 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1091 ; MIPS32: sll [[T1]],[[T1]],0x10
1092 ; MIPS32: sll [[T2]],[[T2]],0x10
1093 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1094 ; MIPS32: andi [[T1]],[[T1]],0xffff
1095 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1096 ; MIPS32: sll [[T3]],[[T3]],0x10
1097 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1098 ; MIPS32: srl [[T4:.*]],a3,0x10
1099 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1100 ; MIPS32: sll [[T4]],[[T4]],0x10
1101 ; MIPS32: sll [[T5]],[[T5]],0x10
1102 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1103 ; MIPS32: sll [[T4]],[[T4]],0x10
1104 ; MIPS32: sll [[T1]],[[T1]],0x10
1105 ; MIPS32: srl [[T1]],[[T1]],0x10
1106 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1107 } 1165 }
1108 1166
1109 define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) { 1167 define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) {
1110 entry: 1168 entry:
1111 %res = icmp uge <8 x i16> %a, %b 1169 %res = icmp uge <8 x i16> %a, %b
1112 ret <8 x i1> %res 1170 ret <8 x i1> %res
1113 ; CHECK-LABEL: test_icmp_v8i16_uge 1171 ; CHECK-LABEL: test_icmp_v8i16_uge
1114 ; CHECK: pxor 1172 ; CHECK: pxor
1115 ; CHECK: pcmpgtw 1173 ; CHECK: pcmpgtw
1116 ; CHECK: pxor 1174 ; CHECK: pxor
1117 1175
1118 ; MIPS32-LABEL: test_icmp_v8i16_uge 1176 ; MIPS32-LABEL: test_icmp_v8i16_uge
1119 ; MIPS32: lw [[B_E0:.*]], 1177 ; MIPS32: lw [[T0:.*]],
1120 ; MIPS32: lw [[B_E1:.*]], 1178 ; MIPS32: lw [[T1:.*]],
1121 ; MIPS32: lw [[B_E2:.*]], 1179 ; MIPS32: lw [[T2:.*]],
1122 ; MIPS32: lw [[B_E3:.*]], 1180 ; MIPS32: lw [[T3:.*]],
1123 ; MIPS32: move [[T1_E0:.*]],zero 1181 ; MIPS32: move [[T4:.*]],zero
1124 ; MIPS32: move [[T1_E1:.*]],zero 1182 ; MIPS32: move [[T5:.*]],zero
1125 ; MIPS32: move [[T1_E2:.*]],zero 1183 ; MIPS32: move [[T6:.*]],zero
1126 ; MIPS32: move [[T1_E3:.*]],zero 1184 ; MIPS32: move [[T7:.*]],zero
1127 ; MIPS32: andi [[T1:.*]],a0,0xffff 1185 ; MIPS32: move [[T8:.*]],a0
1128 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1186 ; MIPS32: andi [[T8]],[[T8]],0xffff
1187 ; MIPS32: move [[T9:.*]],[[T0]]
1188 ; MIPS32: andi [[T9]],[[T9]],0xffff
1189 ; MIPS32: sll [[T8]],[[T8]],0x10
1190 ; MIPS32: sll [[T9]],[[T9]],0x10
1191 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
1192 ; MIPS32: xori [[T8]],[[T8]],0x1
1193 ; MIPS32: andi [[T8]],[[T8]],0xffff
1194 ; MIPS32: srl [[T4]],[[T4]],0x10
1195 ; MIPS32: sll [[T4]],[[T4]],0x10
1196 ; MIPS32: or [[T8]],[[T8]],[[T4]]
1197 ; MIPS32: srl [[T10:.*]],a0,0x10
1198 ; MIPS32: srl [[T0]],[[T0]],0x10
1199 ; MIPS32: sll [[T10]],[[T10]],0x10
1200 ; MIPS32: sll [[T0]],[[T0]],0x10
1201 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
1202 ; MIPS32: xori [[T10]],[[T10]],0x1
1203 ; MIPS32: sll [[T10]],[[T10]],0x10
1204 ; MIPS32: sll [[T8]],[[T8]],0x10
1205 ; MIPS32: srl [[T8]],[[T8]],0x10
1206 ; MIPS32: or [[T10]],[[T10]],[[T8]]
1207 ; MIPS32: move [[T0]],a1
1208 ; MIPS32: andi [[T0]],[[T0]],0xffff
1209 ; MIPS32: move [[T4]],[[T1]]
1210 ; MIPS32: andi [[T4]],[[T4]],0xffff
1211 ; MIPS32: sll [[T0]],[[T0]],0x10
1212 ; MIPS32: sll [[T4]],[[T4]],0x10
1213 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
1214 ; MIPS32: xori [[T0]],[[T0]],0x1
1215 ; MIPS32: andi [[T0]],[[T0]],0xffff
1216 ; MIPS32: srl [[T5]],[[T5]],0x10
1217 ; MIPS32: sll [[T5]],[[T5]],0x10
1218 ; MIPS32: or [[T0]],[[T0]],[[T5]]
1219 ; MIPS32: srl [[T11:.*]],a1,0x10
1220 ; MIPS32: srl [[T1]],[[T1]],0x10
1221 ; MIPS32: sll [[T11]],[[T11]],0x10
1129 ; MIPS32: sll [[T1]],[[T1]],0x10 1222 ; MIPS32: sll [[T1]],[[T1]],0x10
1223 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
1224 ; MIPS32: xori [[T11]],[[T11]],0x1
1225 ; MIPS32: sll [[T11]],[[T11]],0x10
1226 ; MIPS32: sll [[T0]],[[T0]],0x10
1227 ; MIPS32: srl [[T0]],[[T0]],0x10
1228 ; MIPS32: or [[T11]],[[T11]],[[T0]]
1229 ; MIPS32: move [[T0]],a2
1230 ; MIPS32: andi [[T0]],[[T0]],0xffff
1231 ; MIPS32: move [[T1]],[[T2]]
1232 ; MIPS32: andi [[T1]],[[T1]],0xffff
1233 ; MIPS32: sll [[T0]],[[T0]],0x10
1234 ; MIPS32: sll [[T1]],[[T1]],0x10
1235 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
1236 ; MIPS32: xori [[T0]],[[T0]],0x1
1237 ; MIPS32: andi [[T0]],[[T0]],0xffff
1238 ; MIPS32: srl [[T6]],[[T6]],0x10
1239 ; MIPS32: sll [[T6]],[[T6]],0x10
1240 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1241 ; MIPS32: srl [[T12:.*]],a2,0x10
1242 ; MIPS32: srl [[T2]],[[T2]],0x10
1243 ; MIPS32: sll [[T12]],[[T12]],0x10
1130 ; MIPS32: sll [[T2]],[[T2]],0x10 1244 ; MIPS32: sll [[T2]],[[T2]],0x10
1131 ; MIPS32: sltu [[T1]],[[T1]],[[T2]] 1245 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
1132 ; MIPS32: xori [[T1]],[[T1]],0x1 1246 ; MIPS32: xori [[T12]],[[T12]],0x1
1247 ; MIPS32: sll [[T12]],[[T12]],0x10
1248 ; MIPS32: sll [[T0]],[[T0]],0x10
1249 ; MIPS32: srl [[T0]],[[T0]],0x10
1250 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1251 ; MIPS32: move [[T0]],a3
1252 ; MIPS32: andi [[T0]],[[T0]],0xffff
1253 ; MIPS32: move [[T1]],[[T3]]
1133 ; MIPS32: andi [[T1]],[[T1]],0xffff 1254 ; MIPS32: andi [[T1]],[[T1]],0xffff
1134 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1255 ; MIPS32: sll [[T0]],[[T0]],0x10
1256 ; MIPS32: sll [[T1]],[[T1]],0x10
1257 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
1258 ; MIPS32: xori [[T0]],[[T0]],0x1
1259 ; MIPS32: andi [[T0]],[[T0]],0xffff
1260 ; MIPS32: srl [[T7]],[[T7]],0x10
1261 ; MIPS32: sll [[T7]],[[T7]],0x10
1262 ; MIPS32: or [[T0]],[[T0]],[[T7]]
1263 ; MIPS32: srl [[T13:.*]],a3,0x10
1264 ; MIPS32: srl [[T3]],[[T3]],0x10
1265 ; MIPS32: sll [[T13]],[[T13]],0x10
1135 ; MIPS32: sll [[T3]],[[T3]],0x10 1266 ; MIPS32: sll [[T3]],[[T3]],0x10
1136 ; MIPS32: or [[T1]],[[T1]],[[T3]] 1267 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
1137 ; MIPS32: srl [[T4:.*]],a0,0x10 1268 ; MIPS32: xori [[T13]],[[T13]],0x1
1138 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 1269 ; MIPS32: sll [[T13]],[[T13]],0x10
1139 ; MIPS32: sll [[T4]],[[T4]],0x10 1270 ; MIPS32: sll [[T0]],[[T0]],0x10
1140 ; MIPS32: sll [[T5]],[[T5]],0x10 1271 ; MIPS32: srl [[T0]],[[T0]],0x10
1141 ; MIPS32: sltu [[T4]],[[T4]],[[T5]] 1272 ; MIPS32: or [[T13]],[[T13]],[[T0]]
1142 ; MIPS32: xori [[T4]],[[T4]],0x1 1273 ; MIPS32: move v0,[[T10]]
1143 ; MIPS32: sll [[T4]],[[T4]],0x10 1274 ; MIPS32: move v1,[[T11]]
1144 ; MIPS32: sll [[T1]],[[T1]],0x10 1275 ; MIPS32: move a0,[[T12]]
1145 ; MIPS32: srl [[T1]],[[T1]],0x10 1276 ; MIPS32: move a1,[[T13]]
1146 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1147 ; MIPS32: andi [[T1:.*]],a1,0xffff
1148 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1149 ; MIPS32: sll [[T1]],[[T1]],0x10
1150 ; MIPS32: sll [[T2]],[[T2]],0x10
1151 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1152 ; MIPS32: xori [[T1]],[[T1]],0x1
1153 ; MIPS32: andi [[T1]],[[T1]],0xffff
1154 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1155 ; MIPS32: sll [[T3]],[[T3]],0x10
1156 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1157 ; MIPS32: srl [[T4:.*]],a1,0x10
1158 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1159 ; MIPS32: sll [[T4]],[[T4]],0x10
1160 ; MIPS32: sll [[T5]],[[T5]],0x10
1161 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1162 ; MIPS32: xori [[T4]],[[T4]],0x1
1163 ; MIPS32: sll [[T4]],[[T4]],0x10
1164 ; MIPS32: sll [[T1]],[[T1]],0x10
1165 ; MIPS32: srl [[T1]],[[T1]],0x10
1166 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1167 ; MIPS32: andi [[T1:.*]],a2,0xffff
1168 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1169 ; MIPS32: sll [[T1]],[[T1]],0x10
1170 ; MIPS32: sll [[T2]],[[T2]],0x10
1171 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1172 ; MIPS32: xori [[T1]],[[T1]],0x1
1173 ; MIPS32: andi [[T1]],[[T1]],0xffff
1174 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1175 ; MIPS32: sll [[T3]],[[T3]],0x10
1176 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1177 ; MIPS32: srl [[T4:.*]],a2,0x10
1178 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1179 ; MIPS32: sll [[T4]],[[T4]],0x10
1180 ; MIPS32: sll [[T5]],[[T5]],0x10
1181 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1182 ; MIPS32: xori [[T4]],[[T4]],0x1
1183 ; MIPS32: sll [[T4]],[[T4]],0x10
1184 ; MIPS32: sll [[T1]],[[T1]],0x10
1185 ; MIPS32: srl [[T1]],[[T1]],0x10
1186 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1187 ; MIPS32: andi [[T1:.*]],a3,0xffff
1188 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1189 ; MIPS32: sll [[T1]],[[T1]],0x10
1190 ; MIPS32: sll [[T2]],[[T2]],0x10
1191 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1192 ; MIPS32: xori [[T1]],[[T1]],0x1
1193 ; MIPS32: andi [[T1]],[[T1]],0xffff
1194 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1195 ; MIPS32: sll [[T3]],[[T3]],0x10
1196 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1197 ; MIPS32: srl [[T4:.*]],a3,0x10
1198 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1199 ; MIPS32: sll [[T4]],[[T4]],0x10
1200 ; MIPS32: sll [[T5]],[[T5]],0x10
1201 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1202 ; MIPS32: xori [[T4]],[[T4]],0x1
1203 ; MIPS32: sll [[T4]],[[T4]],0x10
1204 ; MIPS32: sll [[T1]],[[T1]],0x10
1205 ; MIPS32: srl [[T1]],[[T1]],0x10
1206 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1207 ; MIPS32: move v0,[[R_E0]]
1208 ; MIPS32: move v1,[[R_E1]]
1209 ; MIPS32: move a0,[[R_E2]]
1210 ; MIPS32: move a1,[[R_E3]]
1211 } 1277 }
1212 1278
1213 define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) { 1279 define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) {
1214 entry: 1280 entry:
1215 %res = icmp ugt <8 x i16> %a, %b 1281 %res = icmp ugt <8 x i16> %a, %b
1216 ret <8 x i1> %res 1282 ret <8 x i1> %res
1217 ; CHECK-LABEL: test_icmp_v8i16_ugt 1283 ; CHECK-LABEL: test_icmp_v8i16_ugt
1218 ; CHECK: pxor 1284 ; CHECK: pxor
1219 ; CHECK: pcmpgtw 1285 ; CHECK: pcmpgtw
1220 1286
1221 ; MIPS32-LABEL: test_icmp_v8i16_ugt 1287 ; MIPS32-LABEL: test_icmp_v8i16_ugt
1222 ; MIPS32: lw [[B_E0:.*]], 1288 ; MIPS32: lw [[T0:.*]],
1223 ; MIPS32: lw [[B_E1:.*]], 1289 ; MIPS32: lw [[T1:.*]],
1224 ; MIPS32: lw [[B_E2:.*]], 1290 ; MIPS32: lw [[T2:.*]],
1225 ; MIPS32: lw [[B_E3:.*]], 1291 ; MIPS32: lw [[T3:.*]],
1226 ; MIPS32: move [[T1_E0:.*]],zero 1292 ; MIPS32: move [[T4:.*]],zero
1227 ; MIPS32: move [[T1_E1:.*]],zero 1293 ; MIPS32: move [[T5:.*]],zero
1228 ; MIPS32: move [[T1_E2:.*]],zero 1294 ; MIPS32: move [[T6:.*]],zero
1229 ; MIPS32: move [[T1_E3:.*]],zero 1295 ; MIPS32: move [[T7:.*]],zero
1230 ; MIPS32: andi [[T1:.*]],a0,0xffff 1296 ; MIPS32: move [[T8:.*]],a0
1231 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1297 ; MIPS32: andi [[T8]],[[T8]],0xffff
1298 ; MIPS32: move [[T9:.*]],[[T0]]
1299 ; MIPS32: andi [[T9]],[[T9]],0xffff
1300 ; MIPS32: sll [[T8]],[[T8]],0x10
1301 ; MIPS32: sll [[T9]],[[T9]],0x10
1302 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
1303 ; MIPS32: andi [[T9]],[[T9]],0xffff
1304 ; MIPS32: srl [[T4]],[[T4]],0x10
1305 ; MIPS32: sll [[T4]],[[T4]],0x10
1306 ; MIPS32: or [[T9]],[[T9]],[[T4]]
1307 ; MIPS32: srl [[T10:.*]],a0,0x10
1308 ; MIPS32: srl [[T0]],[[T0]],0x10
1309 ; MIPS32: sll [[T10]],[[T10]],0x10
1310 ; MIPS32: sll [[T0]],[[T0]],0x10
1311 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
1312 ; MIPS32: sll [[T0]],[[T0]],0x10
1313 ; MIPS32: sll [[T9]],[[T9]],0x10
1314 ; MIPS32: srl [[T9]],[[T9]],0x10
1315 ; MIPS32: or v0,[[T0]],[[T9]]
1316 ; MIPS32: move [[T10]],a1
1317 ; MIPS32: andi [[T10]],[[T10]],0xffff
1318 ; MIPS32: move [[T4]],[[T1]]
1319 ; MIPS32: andi [[T4]],[[T4]],0xffff
1320 ; MIPS32: sll [[T10]],[[T10]],0x10
1321 ; MIPS32: sll [[T4]],[[T4]],0x10
1322 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
1323 ; MIPS32: andi [[T4]],[[T4]],0xffff
1324 ; MIPS32: srl [[T5]],[[T5]],0x10
1325 ; MIPS32: sll [[T5]],[[T5]],0x10
1326 ; MIPS32: or [[T4]],[[T4]],[[T5]]
1327 ; MIPS32: srl [[T11:.*]],a1,0x10
1328 ; MIPS32: srl [[T1]],[[T1]],0x10
1329 ; MIPS32: sll [[T11]],[[T11]],0x10
1232 ; MIPS32: sll [[T1]],[[T1]],0x10 1330 ; MIPS32: sll [[T1]],[[T1]],0x10
1331 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
1332 ; MIPS32: sll [[T1]],[[T1]],0x10
1333 ; MIPS32: sll [[T4]],[[T4]],0x10
1334 ; MIPS32: srl [[T4]],[[T4]],0x10
1335 ; MIPS32: or v1,[[T1]],[[T4]]
1336 ; MIPS32: move [[T10]],a2
1337 ; MIPS32: andi [[T10]],[[T10]],0xffff
1338 ; MIPS32: move [[T11]],[[T2]]
1339 ; MIPS32: andi [[T11]],[[T11]],0xffff
1340 ; MIPS32: sll [[T10]],[[T10]],0x10
1341 ; MIPS32: sll [[T11]],[[T11]],0x10
1342 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
1343 ; MIPS32: andi [[T11]],[[T11]],0xffff
1344 ; MIPS32: srl [[T6]],[[T6]],0x10
1345 ; MIPS32: sll [[T6]],[[T6]],0x10
1346 ; MIPS32: or [[T11]],[[T11]],[[T6]]
1347 ; MIPS32: srl [[T12:.*]],a2,0x10
1348 ; MIPS32: srl [[T2]],[[T2]],0x10
1349 ; MIPS32: sll [[T12]],[[T12]],0x10
1233 ; MIPS32: sll [[T2]],[[T2]],0x10 1350 ; MIPS32: sll [[T2]],[[T2]],0x10
1234 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 1351 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
1235 ; MIPS32: andi [[T2]],[[T2]],0xffff 1352 ; MIPS32: sll [[T2]],[[T2]],0x10
1236 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1353 ; MIPS32: sll [[T11]],[[T11]],0x10
1354 ; MIPS32: srl [[T11]],[[T11]],0x10
1355 ; MIPS32: or [[T2]],[[T2]],[[T11]]
1356 ; MIPS32: move [[T10]],a3
1357 ; MIPS32: andi [[T10]],[[T10]],0xffff
1358 ; MIPS32: move [[T11]],[[T3]]
1359 ; MIPS32: andi [[T11]],[[T11]],0xffff
1360 ; MIPS32: sll [[T10]],[[T10]],0x10
1361 ; MIPS32: sll [[T11]],[[T11]],0x10
1362 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
1363 ; MIPS32: andi [[T11]],[[T11]],0xffff
1364 ; MIPS32: srl [[T7]],[[T7]],0x10
1365 ; MIPS32: sll [[T7]],[[T7]],0x10
1366 ; MIPS32: or [[T11]],[[T11]],[[T7]]
1367 ; MIPS32: srl [[T13:.*]],a3,0x10
1368 ; MIPS32: srl [[T3]],[[T3]],0x10
1369 ; MIPS32: sll [[T13]],[[T13]],0x10
1237 ; MIPS32: sll [[T3]],[[T3]],0x10 1370 ; MIPS32: sll [[T3]],[[T3]],0x10
1238 ; MIPS32: or [[T2]],[[T2]],[[T3]] 1371 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
1239 ; MIPS32: srl [[T4:.*]],a0,0x10
1240 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1241 ; MIPS32: sll [[T4]],[[T4]],0x10
1242 ; MIPS32: sll [[T5]],[[T5]],0x10
1243 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1244 ; MIPS32: sll [[T5]],[[T5]],0x10
1245 ; MIPS32: sll [[T2]],[[T2]],0x10
1246 ; MIPS32: srl [[T2]],[[T2]],0x10
1247 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
1248 ; MIPS32: andi [[T1:.*]],a1,0xffff
1249 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1250 ; MIPS32: sll [[T1]],[[T1]],0x10
1251 ; MIPS32: sll [[T2]],[[T2]],0x10
1252 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1253 ; MIPS32: andi [[T2]],[[T2]],0xffff
1254 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1255 ; MIPS32: sll [[T3]],[[T3]],0x10 1372 ; MIPS32: sll [[T3]],[[T3]],0x10
1256 ; MIPS32: or [[T2]],[[T2]],[[T3]] 1373 ; MIPS32: sll [[T11]],[[T11]],0x10
1257 ; MIPS32: srl [[T4:.*]],a1,0x10 1374 ; MIPS32: srl [[T11]],[[T11]],0x10
1258 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 1375 ; MIPS32: or [[T3]],[[T3]],[[T11]]
1259 ; MIPS32: sll [[T4]],[[T4]],0x10 1376 ; MIPS32: move a0,[[T2]]
1260 ; MIPS32: sll [[T5]],[[T5]],0x10 1377 ; MIPS32: move a1,[[T3]]
1261 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1262 ; MIPS32: sll [[T5]],[[T5]],0x10
1263 ; MIPS32: sll [[T2]],[[T2]],0x10
1264 ; MIPS32: srl [[T2]],[[T2]],0x10
1265 ; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
1266 ; MIPS32: andi [[T1:.*]],a2,0xffff
1267 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1268 ; MIPS32: sll [[T1]],[[T1]],0x10
1269 ; MIPS32: sll [[T2]],[[T2]],0x10
1270 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1271 ; MIPS32: andi [[T2]],[[T2]],0xffff
1272 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1273 ; MIPS32: sll [[T3]],[[T3]],0x10
1274 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1275 ; MIPS32: srl [[T4:.*]],a2,0x10
1276 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1277 ; MIPS32: sll [[T4]],[[T4]],0x10
1278 ; MIPS32: sll [[T5]],[[T5]],0x10
1279 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1280 ; MIPS32: sll [[T5]],[[T5]],0x10
1281 ; MIPS32: sll [[T2]],[[T2]],0x10
1282 ; MIPS32: srl [[T2]],[[T2]],0x10
1283 ; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
1284 ; MIPS32: andi [[T1:.*]],a3,0xffff
1285 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1286 ; MIPS32: sll [[T1]],[[T1]],0x10
1287 ; MIPS32: sll [[T2]],[[T2]],0x10
1288 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1289 ; MIPS32: andi [[T2]],[[T2]],0xffff
1290 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1291 ; MIPS32: sll [[T3]],[[T3]],0x10
1292 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1293 ; MIPS32: srl [[T4:.*]],a3,0x10
1294 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1295 ; MIPS32: sll [[T4]],[[T4]],0x10
1296 ; MIPS32: sll [[T5]],[[T5]],0x10
1297 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1298 ; MIPS32: sll [[T5]],[[T5]],0x10
1299 ; MIPS32: sll [[T2]],[[T2]],0x10
1300 ; MIPS32: srl [[T2]],[[T2]],0x10
1301 ; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
1302
1303 } 1378 }
1304 1379
1305 define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) { 1380 define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) {
1306 entry: 1381 entry:
1307 %res = icmp ule <8 x i16> %a, %b 1382 %res = icmp ule <8 x i16> %a, %b
1308 ret <8 x i1> %res 1383 ret <8 x i1> %res
1309 ; CHECK-LABEL: test_icmp_v8i16_ule 1384 ; CHECK-LABEL: test_icmp_v8i16_ule
1310 ; CHECK: pxor 1385 ; CHECK: pxor
1311 ; CHECK: pcmpgtw 1386 ; CHECK: pcmpgtw
1312 ; CHECK: pxor 1387 ; CHECK: pxor
1313 1388
1314 ; MIPS32-LABEL: test_icmp_v8i16_ule 1389 ; MIPS32-LABEL: test_icmp_v8i16_ule
1315 ; MIPS32: lw [[B_E0:.*]], 1390 ; MIPS32: lw [[T0:.*]],
1316 ; MIPS32: lw [[B_E1:.*]], 1391 ; MIPS32: lw [[T1:.*]],
1317 ; MIPS32: lw [[B_E2:.*]], 1392 ; MIPS32: lw [[T2:.*]],
1318 ; MIPS32: lw [[B_E3:.*]], 1393 ; MIPS32: lw [[T3:.*]],
1319 ; MIPS32: move [[T1_E0:.*]],zero 1394 ; MIPS32: move [[T4:.*]],zero
1320 ; MIPS32: move [[T1_E1:.*]],zero 1395 ; MIPS32: move [[T5:.*]],zero
1321 ; MIPS32: move [[T1_E2:.*]],zero 1396 ; MIPS32: move [[T6:.*]],zero
1322 ; MIPS32: move [[T1_E3:.*]],zero 1397 ; MIPS32: move [[T7:.*]],zero
1323 ; MIPS32: andi [[T1:.*]],a0,0xffff 1398 ; MIPS32: move [[T8:.*]],a0
1324 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1399 ; MIPS32: andi [[T8]],[[T8]],0xffff
1400 ; MIPS32: move [[T9:.*]],[[T0]]
1401 ; MIPS32: andi [[T9]],[[T9]],0xffff
1402 ; MIPS32: sll [[T8]],[[T8]],0x10
1403 ; MIPS32: sll [[T9]],[[T9]],0x10
1404 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
1405 ; MIPS32: xori [[T9]],[[T9]],0x1
1406 ; MIPS32: andi [[T9]],[[T9]],0xffff
1407 ; MIPS32: srl [[T4]],[[T4]],0x10
1408 ; MIPS32: sll [[T4]],[[T4]],0x10
1409 ; MIPS32: or [[T9]],[[T9]],[[T4]]
1410 ; MIPS32: srl [[T10:.*]],a0,0x10
1411 ; MIPS32: srl [[T0]],[[T0]],0x10
1412 ; MIPS32: sll [[T10]],[[T10]],0x10
1413 ; MIPS32: sll [[T0]],[[T0]],0x10
1414 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
1415 ; MIPS32: xori [[T0]],[[T0]],0x1
1416 ; MIPS32: sll [[T0]],[[T0]],0x10
1417 ; MIPS32: sll [[T9]],[[T9]],0x10
1418 ; MIPS32: srl [[T9]],[[T9]],0x10
1419 ; MIPS32: or v0,[[T0]],[[T9]]
1420 ; MIPS32: move [[T10]],a1
1421 ; MIPS32: andi [[T10]],[[T10]],0xffff
1422 ; MIPS32: move [[T4]],[[T1]]
1423 ; MIPS32: andi [[T4]],[[T4]],0xffff
1424 ; MIPS32: sll [[T10]],[[T10]],0x10
1425 ; MIPS32: sll [[T4]],[[T4]],0x10
1426 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
1427 ; MIPS32: xori [[T4]],[[T4]],0x1
1428 ; MIPS32: andi [[T4]],[[T4]],0xffff
1429 ; MIPS32: srl [[T5]],[[T5]],0x10
1430 ; MIPS32: sll [[T5]],[[T5]],0x10
1431 ; MIPS32: or [[T4]],[[T4]],[[T5]]
1432 ; MIPS32: srl [[T11:.*]],a1,0x10
1433 ; MIPS32: srl [[T1]],[[T1]],0x10
1434 ; MIPS32: sll [[T11]],[[T11]],0x10
1325 ; MIPS32: sll [[T1]],[[T1]],0x10 1435 ; MIPS32: sll [[T1]],[[T1]],0x10
1436 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
1437 ; MIPS32: xori [[T1]],[[T1]],0x1
1438 ; MIPS32: sll [[T1]],[[T1]],0x10
1439 ; MIPS32: sll [[T4]],[[T4]],0x10
1440 ; MIPS32: srl [[T4]],[[T4]],0x10
1441 ; MIPS32: or v1,[[T1]],[[T4]]
1442 ; MIPS32: move [[T10]],a2
1443 ; MIPS32: andi [[T10]],[[T10]],0xffff
1444 ; MIPS32: move [[T11]],[[T2]]
1445 ; MIPS32: andi [[T11]],[[T11]],0xffff
1446 ; MIPS32: sll [[T10]],[[T10]],0x10
1447 ; MIPS32: sll [[T11]],[[T11]],0x10
1448 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
1449 ; MIPS32: xori [[T11]],[[T11]],0x1
1450 ; MIPS32: andi [[T11]],[[T11]],0xffff
1451 ; MIPS32: srl [[T6]],[[T6]],0x10
1452 ; MIPS32: sll [[T6]],[[T6]],0x10
1453 ; MIPS32: or [[T11]],[[T11]],[[T6]]
1454 ; MIPS32: srl [[T12:.*]],a2,0x10
1455 ; MIPS32: srl [[T2]],[[T2]],0x10
1456 ; MIPS32: sll [[T12]],[[T12]],0x10
1326 ; MIPS32: sll [[T2]],[[T2]],0x10 1457 ; MIPS32: sll [[T2]],[[T2]],0x10
1327 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 1458 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
1328 ; MIPS32: xori [[T2]],[[T2]],0x1 1459 ; MIPS32: xori [[T2]],[[T2]],0x1
1329 ; MIPS32: andi [[T2]],[[T2]],0xffff 1460 ; MIPS32: sll [[T2]],[[T2]],0x10
1330 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1461 ; MIPS32: sll [[T11]],[[T11]],0x10
1462 ; MIPS32: srl [[T11]],[[T11]],0x10
1463 ; MIPS32: or [[T2]],[[T2]],[[T11]]
1464 ; MIPS32: move [[T10]],a3
1465 ; MIPS32: andi [[T10]],[[T10]],0xffff
1466 ; MIPS32: move [[T11]],[[T3]]
1467 ; MIPS32: andi [[T11]],[[T11]],0xffff
1468 ; MIPS32: sll [[T10]],[[T10]],0x10
1469 ; MIPS32: sll [[T11]],[[T11]],0x10
1470 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
1471 ; MIPS32: xori [[T11]],[[T11]],0x1
1472 ; MIPS32: andi [[T11]],[[T11]],0xffff
1473 ; MIPS32: srl [[T7]],[[T7]],0x10
1474 ; MIPS32: sll [[T7]],[[T7]],0x10
1475 ; MIPS32: or [[T11]],[[T11]],[[T7]]
1476 ; MIPS32: srl [[T13:.*]],a3,0x10
1477 ; MIPS32: srl [[T3]],[[T3]],0x10
1478 ; MIPS32: sll [[T13]],[[T13]],0x10
1331 ; MIPS32: sll [[T3]],[[T3]],0x10 1479 ; MIPS32: sll [[T3]],[[T3]],0x10
1332 ; MIPS32: or [[T2]],[[T2]],[[T3]] 1480 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
1333 ; MIPS32: srl [[T4:.*]],a0,0x10 1481 ; MIPS32: xori [[T3]],[[T3]],0x1
1334 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1335 ; MIPS32: sll [[T4]],[[T4]],0x10
1336 ; MIPS32: sll [[T5]],[[T5]],0x10
1337 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1338 ; MIPS32: xori [[T5]],[[T5]],0x1
1339 ; MIPS32: sll [[T5]],[[T5]],0x10
1340 ; MIPS32: sll [[T2]],[[T2]],0x10
1341 ; MIPS32: srl [[T2]],[[T2]],0x10
1342 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
1343 ; MIPS32: andi [[T1:.*]],a1,0xffff
1344 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1345 ; MIPS32: sll [[T1]],[[T1]],0x10
1346 ; MIPS32: sll [[T2]],[[T2]],0x10
1347 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1348 ; MIPS32: xori [[T2]],[[T2]],0x1
1349 ; MIPS32: andi [[T2]],[[T2]],0xffff
1350 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1351 ; MIPS32: sll [[T3]],[[T3]],0x10 1482 ; MIPS32: sll [[T3]],[[T3]],0x10
1352 ; MIPS32: or [[T2]],[[T2]],[[T3]] 1483 ; MIPS32: sll [[T11]],[[T11]],0x10
1353 ; MIPS32: srl [[T4:.*]],a1,0x10 1484 ; MIPS32: srl [[T11]],[[T11]],0x10
1354 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 1485 ; MIPS32: or [[T3]],[[T3]],[[T11]]
1355 ; MIPS32: sll [[T4]],[[T4]],0x10 1486 ; MIPS32: move a0,[[T2]]
1356 ; MIPS32: sll [[T5]],[[T5]],0x10 1487 ; MIPS32: move a1,[[T3]]
1357 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1358 ; MIPS32: xori [[T5]],[[T5]],0x1
1359 ; MIPS32: sll [[T5]],[[T5]],0x10
1360 ; MIPS32: sll [[T2]],[[T2]],0x10
1361 ; MIPS32: srl [[T2]],[[T2]],0x10
1362 ; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
1363 ; MIPS32: andi [[T1:.*]],a2,0xffff
1364 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1365 ; MIPS32: sll [[T1]],[[T1]],0x10
1366 ; MIPS32: sll [[T2]],[[T2]],0x10
1367 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1368 ; MIPS32: xori [[T2]],[[T2]],0x1
1369 ; MIPS32: andi [[T2]],[[T2]],0xffff
1370 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1371 ; MIPS32: sll [[T3]],[[T3]],0x10
1372 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1373 ; MIPS32: srl [[T4:.*]],a2,0x10
1374 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1375 ; MIPS32: sll [[T4]],[[T4]],0x10
1376 ; MIPS32: sll [[T5]],[[T5]],0x10
1377 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1378 ; MIPS32: xori [[T5]],[[T5]],0x1
1379 ; MIPS32: sll [[T5]],[[T5]],0x10
1380 ; MIPS32: sll [[T2]],[[T2]],0x10
1381 ; MIPS32: srl [[T2]],[[T2]],0x10
1382 ; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
1383 ; MIPS32: andi [[T1:.*]],a3,0xffff
1384 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1385 ; MIPS32: sll [[T1]],[[T1]],0x10
1386 ; MIPS32: sll [[T2]],[[T2]],0x10
1387 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1388 ; MIPS32: xori [[T2]],[[T2]],0x1
1389 ; MIPS32: andi [[T2]],[[T2]],0xffff
1390 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1391 ; MIPS32: sll [[T3]],[[T3]],0x10
1392 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1393 ; MIPS32: srl [[T4:.*]],a3,0x10
1394 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1395 ; MIPS32: sll [[T4]],[[T4]],0x10
1396 ; MIPS32: sll [[T5]],[[T5]],0x10
1397 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1398 ; MIPS32: xori [[T5]],[[T5]],0x1
1399 ; MIPS32: sll [[T5]],[[T5]],0x10
1400 ; MIPS32: sll [[T2]],[[T2]],0x10
1401 ; MIPS32: srl [[T2]],[[T2]],0x10
1402 ; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
1403 } 1488 }
1404 1489
1405 define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) { 1490 define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) {
1406 entry: 1491 entry:
1407 %res = icmp ult <8 x i16> %a, %b 1492 %res = icmp ult <8 x i16> %a, %b
1408 ret <8 x i1> %res 1493 ret <8 x i1> %res
1409 ; CHECK-LABEL: test_icmp_v8i16_ult 1494 ; CHECK-LABEL: test_icmp_v8i16_ult
1410 ; CHECK: pxor 1495 ; CHECK: pxor
1411 ; CHECK: pcmpgtw 1496 ; CHECK: pcmpgtw
1412 1497
1413 ; MIPS32-LABEL: test_icmp_v8i16_ult 1498 ; MIPS32-LABEL: test_icmp_v8i16_ult
1414 ; MIPS32: lw [[B_E0:.*]], 1499 ; MIPS32: lw [[T0:.*]],
1415 ; MIPS32: lw [[B_E1:.*]], 1500 ; MIPS32: lw [[T1:.*]],
1416 ; MIPS32: lw [[B_E2:.*]], 1501 ; MIPS32: lw [[T2:.*]],
1417 ; MIPS32: lw [[B_E3:.*]], 1502 ; MIPS32: lw [[T3:.*]],
1418 ; MIPS32: move [[T1_E0:.*]],zero 1503 ; MIPS32: move [[T4:.*]],zero
1419 ; MIPS32: move [[T1_E1:.*]],zero 1504 ; MIPS32: move [[T5:.*]],zero
1420 ; MIPS32: move [[T1_E2:.*]],zero 1505 ; MIPS32: move [[T6:.*]],zero
1421 ; MIPS32: move [[T1_E3:.*]],zero 1506 ; MIPS32: move [[T7:.*]],zero
1422 ; MIPS32: andi [[T1:.*]],a0,0xffff 1507 ; MIPS32: move [[T8:.*]],a0
1423 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1508 ; MIPS32: andi [[T8]],[[T8]],0xffff
1509 ; MIPS32: move [[T9:.*]],[[T0]]
1510 ; MIPS32: andi [[T9]],[[T9]],0xffff
1511 ; MIPS32: sll [[T8]],[[T8]],0x10
1512 ; MIPS32: sll [[T9]],[[T9]],0x10
1513 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
1514 ; MIPS32: andi [[T8]],[[T8]],0xffff
1515 ; MIPS32: srl [[T4]],[[T4]],0x10
1516 ; MIPS32: sll [[T4]],[[T4]],0x10
1517 ; MIPS32: or [[T8]],[[T8]],[[T4]]
1518 ; MIPS32: srl [[T10:.*]],a0,0x10
1519 ; MIPS32: srl [[T0]],[[T0]],0x10
1520 ; MIPS32: sll [[T10]],[[T10]],0x10
1521 ; MIPS32: sll [[T0]],[[T0]],0x10
1522 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
1523 ; MIPS32: sll [[T10]],[[T10]],0x10
1524 ; MIPS32: sll [[T8]],[[T8]],0x10
1525 ; MIPS32: srl [[T8]],[[T8]],0x10
1526 ; MIPS32: or [[T10]],[[T10]],[[T8]]
1527 ; MIPS32: move [[T0]],a1
1528 ; MIPS32: andi [[T0]],[[T0]],0xffff
1529 ; MIPS32: move [[T4]],[[T1]]
1530 ; MIPS32: andi [[T4]],[[T4]],0xffff
1531 ; MIPS32: sll [[T0]],[[T0]],0x10
1532 ; MIPS32: sll [[T4]],[[T4]],0x10
1533 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
1534 ; MIPS32: andi [[T0]],[[T0]],0xffff
1535 ; MIPS32: srl [[T5]],[[T5]],0x10
1536 ; MIPS32: sll [[T5]],[[T5]],0x10
1537 ; MIPS32: or [[T0]],[[T0]],[[T5]]
1538 ; MIPS32: srl [[T11:.*]],a1,0x10
1539 ; MIPS32: srl [[T1]],[[T1]],0x10
1540 ; MIPS32: sll [[T11]],[[T11]],0x10
1424 ; MIPS32: sll [[T1]],[[T1]],0x10 1541 ; MIPS32: sll [[T1]],[[T1]],0x10
1542 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
1543 ; MIPS32: sll [[T11]],[[T11]],0x10
1544 ; MIPS32: sll [[T0]],[[T0]],0x10
1545 ; MIPS32: srl [[T0]],[[T0]],0x10
1546 ; MIPS32: or [[T11]],[[T11]],[[T0]]
1547 ; MIPS32: move [[T0]],a2
1548 ; MIPS32: andi [[T0]],[[T0]],0xffff
1549 ; MIPS32: move [[T1]],[[T2]]
1550 ; MIPS32: andi [[T1]],[[T1]],0xffff
1551 ; MIPS32: sll [[T0]],[[T0]],0x10
1552 ; MIPS32: sll [[T1]],[[T1]],0x10
1553 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
1554 ; MIPS32: andi [[T0]],[[T0]],0xffff
1555 ; MIPS32: srl [[T6]],[[T6]],0x10
1556 ; MIPS32: sll [[T6]],[[T6]],0x10
1557 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1558 ; MIPS32: srl [[T12:.*]],a2,0x10
1559 ; MIPS32: srl [[T2]],[[T2]],0x10
1560 ; MIPS32: sll [[T12]],[[T12]],0x10
1425 ; MIPS32: sll [[T2]],[[T2]],0x10 1561 ; MIPS32: sll [[T2]],[[T2]],0x10
1426 ; MIPS32: sltu [[T1]],[[T1]],[[T2]] 1562 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
1563 ; MIPS32: sll [[T12]],[[T12]],0x10
1564 ; MIPS32: sll [[T0]],[[T0]],0x10
1565 ; MIPS32: srl [[T0]],[[T0]],0x10
1566 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1567 ; MIPS32: move [[T0]],a3
1568 ; MIPS32: andi [[T0]],[[T0]],0xffff
1569 ; MIPS32: move [[T1]],[[T3]]
1427 ; MIPS32: andi [[T1]],[[T1]],0xffff 1570 ; MIPS32: andi [[T1]],[[T1]],0xffff
1428 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1571 ; MIPS32: sll [[T0]],[[T0]],0x10
1572 ; MIPS32: sll [[T1]],[[T1]],0x10
1573 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
1574 ; MIPS32: andi [[T0]],[[T0]],0xffff
1575 ; MIPS32: srl [[T7]],[[T7]],0x10
1576 ; MIPS32: sll [[T7]],[[T7]],0x10
1577 ; MIPS32: or [[T0]],[[T0]],[[T7]]
1578 ; MIPS32: srl [[T13:.*]],a3,0x10
1579 ; MIPS32: srl [[T3]],[[T3]],0x10
1580 ; MIPS32: sll [[T13]],[[T13]],0x10
1429 ; MIPS32: sll [[T3]],[[T3]],0x10 1581 ; MIPS32: sll [[T3]],[[T3]],0x10
1430 ; MIPS32: or [[T1]],[[T1]],[[T3]] 1582 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
1431 ; MIPS32: srl [[T4:.*]],a0,0x10 1583 ; MIPS32: sll [[T13]],[[T13]],0x10
1432 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 1584 ; MIPS32: sll [[T0]],[[T0]],0x10
1433 ; MIPS32: sll [[T4]],[[T4]],0x10 1585 ; MIPS32: srl [[T0]],[[T0]],0x10
1434 ; MIPS32: sll [[T5]],[[T5]],0x10 1586 ; MIPS32: or [[T13]],[[T13]],[[T0]]
1435 ; MIPS32: sltu [[T4]],[[T4]],[[T5]] 1587 ; MIPS32: move v0,[[T10]]
1436 ; MIPS32: sll [[T4]],[[T4]],0x10 1588 ; MIPS32: move v1,[[T11]]
1437 ; MIPS32: sll [[T1]],[[T1]],0x10 1589 ; MIPS32: move a0,[[T12]]
1438 ; MIPS32: srl [[T1]],[[T1]],0x10 1590 ; MIPS32: move a1,[[T13]]
1439 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1440 ; MIPS32: andi [[T1:.*]],a1,0xffff
1441 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1442 ; MIPS32: sll [[T1]],[[T1]],0x10
1443 ; MIPS32: sll [[T2]],[[T2]],0x10
1444 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1445 ; MIPS32: andi [[T1]],[[T1]],0xffff
1446 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1447 ; MIPS32: sll [[T3]],[[T3]],0x10
1448 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1449 ; MIPS32: srl [[T4:.*]],a1,0x10
1450 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1451 ; MIPS32: sll [[T4]],[[T4]],0x10
1452 ; MIPS32: sll [[T5]],[[T5]],0x10
1453 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1454 ; MIPS32: sll [[T4]],[[T4]],0x10
1455 ; MIPS32: sll [[T1]],[[T1]],0x10
1456 ; MIPS32: srl [[T1]],[[T1]],0x10
1457 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1458 ; MIPS32: andi [[T1:.*]],a2,0xffff
1459 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1460 ; MIPS32: sll [[T1]],[[T1]],0x10
1461 ; MIPS32: sll [[T2]],[[T2]],0x10
1462 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1463 ; MIPS32: andi [[T1]],[[T1]],0xffff
1464 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1465 ; MIPS32: sll [[T3]],[[T3]],0x10
1466 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1467 ; MIPS32: srl [[T4:.*]],a2,0x10
1468 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1469 ; MIPS32: sll [[T4]],[[T4]],0x10
1470 ; MIPS32: sll [[T5]],[[T5]],0x10
1471 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1472 ; MIPS32: sll [[T4]],[[T4]],0x10
1473 ; MIPS32: sll [[T1]],[[T1]],0x10
1474 ; MIPS32: srl [[T1]],[[T1]],0x10
1475 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1476 ; MIPS32: andi [[T1:.*]],a3,0xffff
1477 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1478 ; MIPS32: sll [[T1]],[[T1]],0x10
1479 ; MIPS32: sll [[T2]],[[T2]],0x10
1480 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1481 ; MIPS32: andi [[T1]],[[T1]],0xffff
1482 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1483 ; MIPS32: sll [[T3]],[[T3]],0x10
1484 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1485 ; MIPS32: srl [[T4:.*]],a3,0x10
1486 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1487 ; MIPS32: sll [[T4]],[[T4]],0x10
1488 ; MIPS32: sll [[T5]],[[T5]],0x10
1489 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1490 ; MIPS32: sll [[T4]],[[T4]],0x10
1491 ; MIPS32: sll [[T1]],[[T1]],0x10
1492 ; MIPS32: srl [[T1]],[[T1]],0x10
1493 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1494 ; MIPS32: move v0,[[R_E0]]
1495 ; MIPS32: move v1,[[R_E1]]
1496 ; MIPS32: move a0,[[R_E2]]
1497 ; MIPS32: move a1,[[R_E3]]
1498 } 1591 }
1499 1592
1500 define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) { 1593 define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) {
1501 entry: 1594 entry:
1502 %res = icmp eq <8 x i1> %a, %b 1595 %res = icmp eq <8 x i1> %a, %b
1503 ret <8 x i1> %res 1596 ret <8 x i1> %res
1504 ; CHECK-LABEL: test_icmp_v8i1_eq 1597 ; CHECK-LABEL: test_icmp_v8i1_eq
1505 ; CHECK: pcmpeqw 1598 ; CHECK: pcmpeqw
1506 1599
1507 ; MIPS32-LABEL: test_icmp_v8i1_eq 1600 ; MIPS32-LABEL: test_icmp_v8i1_eq
1508 ; MIPS32: lw [[B_E0:.*]], 1601 ; MIPS32: lw [[T0:.*]],
1509 ; MIPS32: lw [[B_E1:.*]], 1602 ; MIPS32: lw [[T1:.*]],
1510 ; MIPS32: lw [[B_E2:.*]], 1603 ; MIPS32: lw [[T2:.*]],
1511 ; MIPS32: lw [[B_E3:.*]], 1604 ; MIPS32: lw [[T3:.*]],
1512 ; MIPS32: move [[T1_E0:.*]],zero 1605 ; MIPS32: move [[T4:.*]],zero
1513 ; MIPS32: move [[T1_E1:.*]],zero 1606 ; MIPS32: move [[T5:.*]],zero
1514 ; MIPS32: move [[T1_E2:.*]],zero 1607 ; MIPS32: move [[T6:.*]],zero
1515 ; MIPS32: move [[T1_E3:.*]],zero 1608 ; MIPS32: move [[T7:.*]],zero
1516 ; MIPS32: andi [[T1:.*]],a0,0xffff 1609 ; MIPS32: move [[T8:.*]],a0
1610 ; MIPS32: andi [[T8]],[[T8]],0xffff
1611 ; MIPS32: andi [[T8]],[[T8]],0x1
1612 ; MIPS32: move [[T9:.*]],[[T0]]
1613 ; MIPS32: andi [[T9]],[[T9]],0xffff
1614 ; MIPS32: andi [[T9]],[[T9]],0x1
1615 ; MIPS32: sll [[T8]],[[T8]],0x1f
1616 ; MIPS32: sll [[T9]],[[T9]],0x1f
1617 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
1618 ; MIPS32: sltiu [[T8]],[[T8]],1
1619 ; MIPS32: andi [[T8]],[[T8]],0xffff
1620 ; MIPS32: srl [[T4]],[[T4]],0x10
1621 ; MIPS32: sll [[T4]],[[T4]],0x10
1622 ; MIPS32: or [[T8]],[[T8]],[[T4]]
1623 ; MIPS32: srl [[T10:.*]],a0,0x10
1624 ; MIPS32: andi [[T10]],[[T10]],0x1
1625 ; MIPS32: srl [[T0]],[[T0]],0x10
1626 ; MIPS32: andi [[T0]],[[T0]],0x1
1627 ; MIPS32: sll [[T10]],[[T10]],0x1f
1628 ; MIPS32: sll [[T0]],[[T0]],0x1f
1629 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
1630 ; MIPS32: sltiu [[T10]],[[T10]],1
1631 ; MIPS32: sll [[T10]],[[T10]],0x10
1632 ; MIPS32: sll [[T8]],[[T8]],0x10
1633 ; MIPS32: srl [[T8]],[[T8]],0x10
1634 ; MIPS32: or [[T10]],[[T10]],[[T8]]
1635 ; MIPS32: move [[T0]],a1
1636 ; MIPS32: andi [[T0]],[[T0]],0xffff
1637 ; MIPS32: andi [[T0]],[[T0]],0x1
1638 ; MIPS32: move [[T4]],[[T1]]
1639 ; MIPS32: andi [[T4]],[[T4]],0xffff
1640 ; MIPS32: andi [[T4]],[[T4]],0x1
1641 ; MIPS32: sll [[T0]],[[T0]],0x1f
1642 ; MIPS32: sll [[T4]],[[T4]],0x1f
1643 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
1644 ; MIPS32: sltiu [[T0]],[[T0]],1
1645 ; MIPS32: andi [[T0]],[[T0]],0xffff
1646 ; MIPS32: srl [[T5]],[[T5]],0x10
1647 ; MIPS32: sll [[T5]],[[T5]],0x10
1648 ; MIPS32: or [[T0]],[[T0]],[[T5]]
1649 ; MIPS32: srl [[T11:.*]],a1,0x10
1650 ; MIPS32: andi [[T11]],[[T11]],0x1
1651 ; MIPS32: srl [[T1]],[[T1]],0x10
1517 ; MIPS32: andi [[T1]],[[T1]],0x1 1652 ; MIPS32: andi [[T1]],[[T1]],0x1
1518 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1653 ; MIPS32: sll [[T11]],[[T11]],0x1f
1654 ; MIPS32: sll [[T1]],[[T1]],0x1f
1655 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
1656 ; MIPS32: sltiu [[T11]],[[T11]],1
1657 ; MIPS32: sll [[T11]],[[T11]],0x10
1658 ; MIPS32: sll [[T0]],[[T0]],0x10
1659 ; MIPS32: srl [[T0]],[[T0]],0x10
1660 ; MIPS32: or [[T11]],[[T11]],[[T0]]
1661 ; MIPS32: move [[T0]],a2
1662 ; MIPS32: andi [[T0]],[[T0]],0xffff
1663 ; MIPS32: andi [[T0]],[[T0]],0x1
1664 ; MIPS32: move [[T1]],[[T2]]
1665 ; MIPS32: andi [[T1]],[[T1]],0xffff
1666 ; MIPS32: andi [[T1]],[[T1]],0x1
1667 ; MIPS32: sll [[T0]],[[T0]],0x1f
1668 ; MIPS32: sll [[T1]],[[T1]],0x1f
1669 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
1670 ; MIPS32: sltiu [[T0]],[[T0]],1
1671 ; MIPS32: andi [[T0]],[[T0]],0xffff
1672 ; MIPS32: srl [[T6]],[[T6]],0x10
1673 ; MIPS32: sll [[T6]],[[T6]],0x10
1674 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1675 ; MIPS32: srl [[T12:.*]],a2,0x10
1676 ; MIPS32: andi [[T12]],[[T12]],0x1
1677 ; MIPS32: srl [[T2]],[[T2]],0x10
1519 ; MIPS32: andi [[T2]],[[T2]],0x1 1678 ; MIPS32: andi [[T2]],[[T2]],0x1
1679 ; MIPS32: sll [[T12]],[[T12]],0x1f
1680 ; MIPS32: sll [[T2]],[[T2]],0x1f
1681 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
1682 ; MIPS32: sltiu [[T12]],[[T12]],1
1683 ; MIPS32: sll [[T12]],[[T12]],0x10
1684 ; MIPS32: sll [[T0]],[[T0]],0x10
1685 ; MIPS32: srl [[T0]],[[T0]],0x10
1686 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1687 ; MIPS32: move [[T0]],a3
1688 ; MIPS32: andi [[T0]],[[T0]],0xffff
1689 ; MIPS32: andi [[T0]],[[T0]],0x1
1690 ; MIPS32: move [[T1]],[[T3]]
1691 ; MIPS32: andi [[T1]],[[T1]],0xffff
1692 ; MIPS32: andi [[T1]],[[T1]],0x1
1693 ; MIPS32: sll [[T0]],[[T0]],0x1f
1520 ; MIPS32: sll [[T1]],[[T1]],0x1f 1694 ; MIPS32: sll [[T1]],[[T1]],0x1f
1521 ; MIPS32: sll [[T2]],[[T2]],0x1f 1695 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
1522 ; MIPS32: xor [[T1]],[[T1]],[[T2]] 1696 ; MIPS32: sltiu [[T0]],[[T0]],1
1523 ; MIPS32: sltiu [[T1]],[[T1]],1 1697 ; MIPS32: andi [[T0]],[[T0]],0xffff
1524 ; MIPS32: andi [[T1]],[[T1]],0xffff 1698 ; MIPS32: srl [[T7]],[[T7]],0x10
1525 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1699 ; MIPS32: sll [[T7]],[[T7]],0x10
1526 ; MIPS32: sll [[T3]],[[T3]],0x10 1700 ; MIPS32: or [[T0]],[[T0]],[[T7]]
1527 ; MIPS32: or [[T1]],[[T1]],[[T3]] 1701 ; MIPS32: srl [[T13:.*]],a3,0x10
1528 ; MIPS32: srl [[T4:.*]],a0,0x10 1702 ; MIPS32: andi [[T13]],[[T13]],0x1
1529 ; MIPS32: andi [[T4]],[[T4]],0x1 1703 ; MIPS32: srl [[T3]],[[T3]],0x10
1530 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 1704 ; MIPS32: andi [[T3]],[[T3]],0x1
1531 ; MIPS32: andi [[T5]],[[T5]],0x1 1705 ; MIPS32: sll [[T13]],[[T13]],0x1f
1532 ; MIPS32: sll [[T4]],[[T4]],0x1f 1706 ; MIPS32: sll [[T3]],[[T3]],0x1f
1533 ; MIPS32: sll [[T5]],[[T5]],0x1f 1707 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
1534 ; MIPS32: xor [[T4]],[[T4]],[[T5]] 1708 ; MIPS32: sltiu [[T13]],[[T13]],1
1535 ; MIPS32: sltiu [[T4]],[[T4]],1 1709 ; MIPS32: sll [[T13]],[[T13]],0x10
1536 ; MIPS32: sll [[T4]],[[T4]],0x10 1710 ; MIPS32: sll [[T0]],[[T0]],0x10
1537 ; MIPS32: sll [[T1]],[[T1]],0x10 1711 ; MIPS32: srl [[T0]],[[T0]],0x10
1538 ; MIPS32: srl [[T1]],[[T1]],0x10 1712 ; MIPS32: or [[T13]],[[T13]],[[T0]]
1539 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] 1713 ; MIPS32: move v0,[[T10]]
1540 ; MIPS32: andi [[T1:.*]],a1,0xffff 1714 ; MIPS32: move v1,[[T11]]
1541 ; MIPS32: andi [[T1]],[[T1]],0x1 1715 ; MIPS32: move a0,[[T12]]
1542 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff 1716 ; MIPS32: move a1,[[T13]]
1543 ; MIPS32: andi [[T2]],[[T2]],0x1
1544 ; MIPS32: sll [[T1]],[[T1]],0x1f
1545 ; MIPS32: sll [[T2]],[[T2]],0x1f
1546 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1547 ; MIPS32: sltiu [[T1]],[[T1]],1
1548 ; MIPS32: andi [[T1]],[[T1]],0xffff
1549 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1550 ; MIPS32: sll [[T3]],[[T3]],0x10
1551 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1552 ; MIPS32: srl [[T4:.*]],a1,0x10
1553 ; MIPS32: andi [[T4]],[[T4]],0x1
1554 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1555 ; MIPS32: andi [[T5]],[[T5]],0x1
1556 ; MIPS32: sll [[T4]],[[T4]],0x1f
1557 ; MIPS32: sll [[T5]],[[T5]],0x1f
1558 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1559 ; MIPS32: sltiu [[T4]],[[T4]],1
1560 ; MIPS32: sll [[T4]],[[T4]],0x10
1561 ; MIPS32: sll [[T1]],[[T1]],0x10
1562 ; MIPS32: srl [[T1]],[[T1]],0x10
1563 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1564 ; MIPS32: andi [[T1:.*]],a2,0xffff
1565 ; MIPS32: andi [[T1]],[[T1]],0x1
1566 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1567 ; MIPS32: andi [[T2]],[[T2]],0x1
1568 ; MIPS32: sll [[T1]],[[T1]],0x1f
1569 ; MIPS32: sll [[T2]],[[T2]],0x1f
1570 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1571 ; MIPS32: sltiu [[T1]],[[T1]],1
1572 ; MIPS32: andi [[T1]],[[T1]],0xffff
1573 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1574 ; MIPS32: sll [[T3]],[[T3]],0x10
1575 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1576 ; MIPS32: srl [[T4:.*]],a2,0x10
1577 ; MIPS32: andi [[T4]],[[T4]],0x1
1578 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1579 ; MIPS32: andi [[T5]],[[T5]],0x1
1580 ; MIPS32: sll [[T4]],[[T4]],0x1f
1581 ; MIPS32: sll [[T5]],[[T5]],0x1f
1582 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1583 ; MIPS32: sltiu [[T4]],[[T4]],1
1584 ; MIPS32: sll [[T4]],[[T4]],0x10
1585 ; MIPS32: sll [[T1]],[[T1]],0x10
1586 ; MIPS32: srl [[T1]],[[T1]],0x10
1587 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1588 ; MIPS32: andi [[T1:.*]],a3,0xffff
1589 ; MIPS32: andi [[T1]],[[T1]],0x1
1590 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1591 ; MIPS32: andi [[T2]],[[T2]],0x1
1592 ; MIPS32: sll [[T1]],[[T1]],0x1f
1593 ; MIPS32: sll [[T2]],[[T2]],0x1f
1594 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1595 ; MIPS32: sltiu [[T1]],[[T1]],1
1596 ; MIPS32: andi [[T1]],[[T1]],0xffff
1597 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1598 ; MIPS32: sll [[T3]],[[T3]],0x10
1599 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1600 ; MIPS32: srl [[T4:.*]],a3,0x10
1601 ; MIPS32: andi [[T4]],[[T4]],0x1
1602 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1603 ; MIPS32: andi [[T5]],[[T5]],0x1
1604 ; MIPS32: sll [[T4]],[[T4]],0x1f
1605 ; MIPS32: sll [[T5]],[[T5]],0x1f
1606 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1607 ; MIPS32: sltiu [[T4]],[[T4]],1
1608 ; MIPS32: sll [[T4]],[[T4]],0x10
1609 ; MIPS32: sll [[T1]],[[T1]],0x10
1610 ; MIPS32: srl [[T1]],[[T1]],0x10
1611 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1612 ; MIPS32: move v0,[[R_E0]]
1613 ; MIPS32: move v1,[[R_E1]]
1614 ; MIPS32: move a0,[[R_E2]]
1615 ; MIPS32: move a1,[[R_E3]]
1616 } 1717 }
1617 1718
1618 define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) { 1719 define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) {
1619 entry: 1720 entry:
1620 %res = icmp ne <8 x i1> %a, %b 1721 %res = icmp ne <8 x i1> %a, %b
1621 ret <8 x i1> %res 1722 ret <8 x i1> %res
1622 ; CHECK-LABEL: test_icmp_v8i1_ne 1723 ; CHECK-LABEL: test_icmp_v8i1_ne
1623 ; CHECK: pcmpeqw 1724 ; CHECK: pcmpeqw
1624 ; CHECK: pxor 1725 ; CHECK: pxor
1625 1726
1626 ; MIPS32-LABEL: test_icmp_v8i1_ne 1727 ; MIPS32-LABEL: test_icmp_v8i1_ne
1627 ; MIPS32: lw [[B_E0:.*]], 1728 ; MIPS32: lw [[T0:.*]],
1628 ; MIPS32: lw [[B_E1:.*]], 1729 ; MIPS32: lw [[T1:.*]],
1629 ; MIPS32: lw [[B_E2:.*]], 1730 ; MIPS32: lw [[T2:.*]],
1630 ; MIPS32: lw [[B_E3:.*]], 1731 ; MIPS32: lw [[T3:.*]],
1631 ; MIPS32: move [[T1_E0:.*]],zero 1732 ; MIPS32: move [[T4:.*]],zero
1632 ; MIPS32: move [[T1_E1:.*]],zero 1733 ; MIPS32: move [[T5:.*]],zero
1633 ; MIPS32: move [[T1_E2:.*]],zero 1734 ; MIPS32: move [[T6:.*]],zero
1634 ; MIPS32: move [[T1_E3:.*]],zero 1735 ; MIPS32: move [[T7:.*]],zero
1635 ; MIPS32: andi [[T1:.*]],a0,0xffff 1736 ; MIPS32: move [[T8:.*]],a0
1737 ; MIPS32: andi [[T8]],[[T8]],0xffff
1738 ; MIPS32: andi [[T8]],[[T8]],0x1
1739 ; MIPS32: move [[T9:.*]],[[T0]]
1740 ; MIPS32: andi [[T9]],[[T9]],0xffff
1741 ; MIPS32: andi [[T9]],[[T9]],0x1
1742 ; MIPS32: sll [[T8]],[[T8]],0x1f
1743 ; MIPS32: sll [[T9]],[[T9]],0x1f
1744 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
1745 ; MIPS32: sltu [[T8]],zero,[[T8]]
1746 ; MIPS32: andi [[T8]],[[T8]],0xffff
1747 ; MIPS32: srl [[T4]],[[T4]],0x10
1748 ; MIPS32: sll [[T4]],[[T4]],0x10
1749 ; MIPS32: or [[T8]],[[T8]],[[T4]]
1750 ; MIPS32: srl [[T10:.*]],a0,0x10
1751 ; MIPS32: andi [[T10]],[[T10]],0x1
1752 ; MIPS32: srl [[T0]],[[T0]],0x10
1753 ; MIPS32: andi [[T0]],[[T0]],0x1
1754 ; MIPS32: sll [[T10]],[[T10]],0x1f
1755 ; MIPS32: sll [[T0]],[[T0]],0x1f
1756 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
1757 ; MIPS32: sltu [[T10]],zero,[[T10]]
1758 ; MIPS32: sll [[T10]],[[T10]],0x10
1759 ; MIPS32: sll [[T8]],[[T8]],0x10
1760 ; MIPS32: srl [[T8]],[[T8]],0x10
1761 ; MIPS32: or [[T10]],[[T10]],[[T8]]
1762 ; MIPS32: move [[T0]],a1
1763 ; MIPS32: andi [[T0]],[[T0]],0xffff
1764 ; MIPS32: andi [[T0]],[[T0]],0x1
1765 ; MIPS32: move [[T4]],[[T1]]
1766 ; MIPS32: andi [[T4]],[[T4]],0xffff
1767 ; MIPS32: andi [[T4]],[[T4]],0x1
1768 ; MIPS32: sll [[T0]],[[T0]],0x1f
1769 ; MIPS32: sll [[T4]],[[T4]],0x1f
1770 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
1771 ; MIPS32: sltu [[T0]],zero,[[T0]]
1772 ; MIPS32: andi [[T0]],[[T0]],0xffff
1773 ; MIPS32: srl [[T5]],[[T5]],0x10
1774 ; MIPS32: sll [[T5]],[[T5]],0x10
1775 ; MIPS32: or [[T0]],[[T0]],[[T5]]
1776 ; MIPS32: srl [[T11:.*]],a1,0x10
1777 ; MIPS32: andi [[T11]],[[T11]],0x1
1778 ; MIPS32: srl [[T1]],[[T1]],0x10
1636 ; MIPS32: andi [[T1]],[[T1]],0x1 1779 ; MIPS32: andi [[T1]],[[T1]],0x1
1637 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff 1780 ; MIPS32: sll [[T11]],[[T11]],0x1f
1781 ; MIPS32: sll [[T1]],[[T1]],0x1f
1782 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
1783 ; MIPS32: sltu [[T11]],zero,[[T11]]
1784 ; MIPS32: sll [[T11]],[[T11]],0x10
1785 ; MIPS32: sll [[T0]],[[T0]],0x10
1786 ; MIPS32: srl [[T0]],[[T0]],0x10
1787 ; MIPS32: or [[T11]],[[T11]],[[T0]]
1788 ; MIPS32: move [[T0]],a2
1789 ; MIPS32: andi [[T0]],[[T0]],0xffff
1790 ; MIPS32: andi [[T0]],[[T0]],0x1
1791 ; MIPS32: move [[T1]],[[T2]]
1792 ; MIPS32: andi [[T1]],[[T1]],0xffff
1793 ; MIPS32: andi [[T1]],[[T1]],0x1
1794 ; MIPS32: sll [[T0]],[[T0]],0x1f
1795 ; MIPS32: sll [[T1]],[[T1]],0x1f
1796 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
1797 ; MIPS32: sltu [[T0]],zero,[[T0]]
1798 ; MIPS32: andi [[T0]],[[T0]],0xffff
1799 ; MIPS32: srl [[T6]],[[T6]],0x10
1800 ; MIPS32: sll [[T6]],[[T6]],0x10
1801 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1802 ; MIPS32: srl [[T12:.*]],a2,0x10
1803 ; MIPS32: andi [[T12]],[[T12]],0x1
1804 ; MIPS32: srl [[T2]],[[T2]],0x10
1638 ; MIPS32: andi [[T2]],[[T2]],0x1 1805 ; MIPS32: andi [[T2]],[[T2]],0x1
1806 ; MIPS32: sll [[T12]],[[T12]],0x1f
1807 ; MIPS32: sll [[T2]],[[T2]],0x1f
1808 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
1809 ; MIPS32: sltu [[T12]],zero,[[T12]]
1810 ; MIPS32: sll [[T12]],[[T12]],0x10
1811 ; MIPS32: sll [[T0]],[[T0]],0x10
1812 ; MIPS32: srl [[T0]],[[T0]],0x10
1813 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1814 ; MIPS32: move [[T0]],a3
1815 ; MIPS32: andi [[T0]],[[T0]],0xffff
1816 ; MIPS32: andi [[T0]],[[T0]],0x1
1817 ; MIPS32: move [[T1]],[[T3]]
1818 ; MIPS32: andi [[T1]],[[T1]],0xffff
1819 ; MIPS32: andi [[T1]],[[T1]],0x1
1820 ; MIPS32: sll [[T0]],[[T0]],0x1f
1639 ; MIPS32: sll [[T1]],[[T1]],0x1f 1821 ; MIPS32: sll [[T1]],[[T1]],0x1f
1640 ; MIPS32: sll [[T2]],[[T2]],0x1f 1822 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
1641 ; MIPS32: xor [[T1]],[[T1]],[[T2]] 1823 ; MIPS32: sltu [[T0]],zero,[[T0]]
1642 ; MIPS32: sltu [[T1]],zero,[[T1]] 1824 ; MIPS32: andi [[T0]],[[T0]],0xffff
1643 ; MIPS32: andi [[T1]],[[T1]],0xffff 1825 ; MIPS32: srl [[T7]],[[T7]],0x10
1644 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 1826 ; MIPS32: sll [[T7]],[[T7]],0x10
1645 ; MIPS32: sll [[T3]],[[T3]],0x10 1827 ; MIPS32: or [[T0]],[[T0]],[[T7]]
1646 ; MIPS32: or [[T1]],[[T1]],[[T3]] 1828 ; MIPS32: srl [[T13:.*]],a3,0x10
1647 ; MIPS32: srl [[T4:.*]],a0,0x10 1829 ; MIPS32: andi [[T13]],[[T13]],0x1
1648 ; MIPS32: andi [[T4]],[[T4]],0x1 1830 ; MIPS32: srl [[T3]],[[T3]],0x10
1649 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 1831 ; MIPS32: andi [[T3]],[[T3]],0x1
1650 ; MIPS32: andi [[T5]],[[T5]],0x1 1832 ; MIPS32: sll [[T13]],[[T13]],0x1f
1651 ; MIPS32: sll [[T4]],[[T4]],0x1f 1833 ; MIPS32: sll [[T3]],[[T3]],0x1f
1652 ; MIPS32: sll [[T5]],[[T5]],0x1f 1834 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
1653 ; MIPS32: xor [[T4]],[[T4]],[[T5]] 1835 ; MIPS32: sltu [[T13]],zero,[[T13]]
1654 ; MIPS32: sltu [[T4]],zero,[[T4]] 1836 ; MIPS32: sll [[T13]],[[T13]],0x10
1655 ; MIPS32: sll [[T4]],[[T4]],0x10 1837 ; MIPS32: sll [[T0]],[[T0]],0x10
1656 ; MIPS32: sll [[T1]],[[T1]],0x10 1838 ; MIPS32: srl [[T0]],[[T0]],0x10
1657 ; MIPS32: srl [[T1]],[[T1]],0x10 1839 ; MIPS32: or [[T13]],[[T13]],[[T0]]
1658 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] 1840 ; MIPS32: move v0,[[T10]]
1659 ; MIPS32: andi [[T1:.*]],a1,0xffff 1841 ; MIPS32: move v1,[[T11]]
1660 ; MIPS32: andi [[T1]],[[T1]],0x1 1842 ; MIPS32: move a0,[[T12]]
1661 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff 1843 ; MIPS32: move a1,[[T13]]
1662 ; MIPS32: andi [[T2]],[[T2]],0x1
1663 ; MIPS32: sll [[T1]],[[T1]],0x1f
1664 ; MIPS32: sll [[T2]],[[T2]],0x1f
1665 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1666 ; MIPS32: sltu [[T1]],zero,[[T1]]
1667 ; MIPS32: andi [[T1]],[[T1]],0xffff
1668 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1669 ; MIPS32: sll [[T3]],[[T3]],0x10
1670 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1671 ; MIPS32: srl [[T4:.*]],a1,0x10
1672 ; MIPS32: andi [[T4]],[[T4]],0x1
1673 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1674 ; MIPS32: andi [[T5]],[[T5]],0x1
1675 ; MIPS32: sll [[T4]],[[T4]],0x1f
1676 ; MIPS32: sll [[T5]],[[T5]],0x1f
1677 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1678 ; MIPS32: sltu [[T4]],zero,[[T4]]
1679 ; MIPS32: sll [[T4]],[[T4]],0x10
1680 ; MIPS32: sll [[T1]],[[T1]],0x10
1681 ; MIPS32: srl [[T1]],[[T1]],0x10
1682 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1683 ; MIPS32: andi [[T1:.*]],a2,0xffff
1684 ; MIPS32: andi [[T1]],[[T1]],0x1
1685 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1686 ; MIPS32: andi [[T2]],[[T2]],0x1
1687 ; MIPS32: sll [[T1]],[[T1]],0x1f
1688 ; MIPS32: sll [[T2]],[[T2]],0x1f
1689 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1690 ; MIPS32: sltu [[T1]],zero,[[T1]]
1691 ; MIPS32: andi [[T1]],[[T1]],0xffff
1692 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1693 ; MIPS32: sll [[T3]],[[T3]],0x10
1694 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1695 ; MIPS32: srl [[T4:.*]],a2,0x10
1696 ; MIPS32: andi [[T4]],[[T4]],0x1
1697 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1698 ; MIPS32: andi [[T5]],[[T5]],0x1
1699 ; MIPS32: sll [[T4]],[[T4]],0x1f
1700 ; MIPS32: sll [[T5]],[[T5]],0x1f
1701 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1702 ; MIPS32: sltu [[T4]],zero,[[T4]]
1703 ; MIPS32: sll [[T4]],[[T4]],0x10
1704 ; MIPS32: sll [[T1]],[[T1]],0x10
1705 ; MIPS32: srl [[T1]],[[T1]],0x10
1706 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1707 ; MIPS32: andi [[T1:.*]],a3,0xffff
1708 ; MIPS32: andi [[T1]],[[T1]],0x1
1709 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1710 ; MIPS32: andi [[T2]],[[T2]],0x1
1711 ; MIPS32: sll [[T1]],[[T1]],0x1f
1712 ; MIPS32: sll [[T2]],[[T2]],0x1f
1713 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1714 ; MIPS32: sltu [[T1]],zero,[[T1]]
1715 ; MIPS32: andi [[T1]],[[T1]],0xffff
1716 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1717 ; MIPS32: sll [[T3]],[[T3]],0x10
1718 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1719 ; MIPS32: srl [[T4:.*]],a3,0x10
1720 ; MIPS32: andi [[T4]],[[T4]],0x1
1721 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1722 ; MIPS32: andi [[T5]],[[T5]],0x1
1723 ; MIPS32: sll [[T4]],[[T4]],0x1f
1724 ; MIPS32: sll [[T5]],[[T5]],0x1f
1725 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1726 ; MIPS32: sltu [[T4]],zero,[[T4]]
1727 ; MIPS32: sll [[T4]],[[T4]],0x10
1728 ; MIPS32: sll [[T1]],[[T1]],0x10
1729 ; MIPS32: srl [[T1]],[[T1]],0x10
1730 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1731 ; MIPS32: move v0,[[R_E0]]
1732 ; MIPS32: move v1,[[R_E1]]
1733 ; MIPS32: move a0,[[R_E2]]
1734 ; MIPS32: move a1,[[R_E3]]
1735 } 1844 }
1736 1845
1737 define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) { 1846 define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) {
1738 entry: 1847 entry:
1739 %res = icmp sgt <8 x i1> %a, %b 1848 %res = icmp sgt <8 x i1> %a, %b
1740 ret <8 x i1> %res 1849 ret <8 x i1> %res
1741 ; CHECK-LABEL: test_icmp_v8i1_sgt 1850 ; CHECK-LABEL: test_icmp_v8i1_sgt
1742 ; CHECK: pcmpgtw 1851 ; CHECK: pcmpgtw
1743 1852
1744 ; MIPS32-LABEL: test_icmp_v8i1_sgt 1853 ; MIPS32-LABEL: test_icmp_v8i1_sgt
1745 ; MIPS32: lw [[BV_E0:.*]], 1854 ; MIPS32: lw [[T0:.*]],
1746 ; MIPS32: lw [[BV_E1:.*]], 1855 ; MIPS32: lw [[T1:.*]],
1747 ; MIPS32: lw [[BV_E2:.*]], 1856 ; MIPS32: lw [[T2:.*]],
1748 ; MIPS32: lw [[BV_E3:.*]], 1857 ; MIPS32: lw [[T3:.*]],
1749 ; MIPS32: move [[TV_E0:.*]],zero 1858 ; MIPS32: move [[T4:.*]],zero
1750 ; MIPS32: move [[TV_E1:.*]],zero 1859 ; MIPS32: move [[T5:.*]],zero
1751 ; MIPS32: move [[TV_E2:.*]],zero 1860 ; MIPS32: move [[T6:.*]],zero
1752 ; MIPS32: move [[TV_E3:.*]],zero 1861 ; MIPS32: move [[T7:.*]],zero
1753 ; MIPS32: andi [[T0:.*]],a0,0xffff 1862 ; MIPS32: move [[T8:.*]],a0
1863 ; MIPS32: andi [[T8]],[[T8]],0xffff
1864 ; MIPS32: andi [[T8]],[[T8]],0x1
1865 ; MIPS32: move [[T9:.*]],[[T0]]
1866 ; MIPS32: andi [[T9]],[[T9]],0xffff
1867 ; MIPS32: andi [[T9]],[[T9]],0x1
1868 ; MIPS32: sll [[T8]],[[T8]],0x1f
1869 ; MIPS32: sll [[T9]],[[T9]],0x1f
1870 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
1871 ; MIPS32: andi [[T9]],[[T9]],0xffff
1872 ; MIPS32: srl [[T4]],[[T4]],0x10
1873 ; MIPS32: sll [[T4]],[[T4]],0x10
1874 ; MIPS32: or [[T9]],[[T9]],[[T4]]
1875 ; MIPS32: srl [[T10:.*]],a0,0x10
1876 ; MIPS32: andi [[T10]],[[T10]],0x1
1877 ; MIPS32: srl [[T0]],[[T0]],0x10
1754 ; MIPS32: andi [[T0]],[[T0]],0x1 1878 ; MIPS32: andi [[T0]],[[T0]],0x1
1755 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 1879 ; MIPS32: sll [[T10]],[[T10]],0x1f
1880 ; MIPS32: sll [[T0]],[[T0]],0x1f
1881 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
1882 ; MIPS32: sll [[T0]],[[T0]],0x10
1883 ; MIPS32: sll [[T9]],[[T9]],0x10
1884 ; MIPS32: srl [[T9]],[[T9]],0x10
1885 ; MIPS32: or v0,[[T0]],[[T9]]
1886 ; MIPS32: move [[T10]],a1
1887 ; MIPS32: andi [[T10]],[[T10]],0xffff
1888 ; MIPS32: andi [[T10]],[[T10]],0x1
1889 ; MIPS32: move [[T4]],[[T1]]
1890 ; MIPS32: andi [[T4]],[[T4]],0xffff
1891 ; MIPS32: andi [[T4]],[[T4]],0x1
1892 ; MIPS32: sll [[T10]],[[T10]],0x1f
1893 ; MIPS32: sll [[T4]],[[T4]],0x1f
1894 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
1895 ; MIPS32: andi [[T4]],[[T4]],0xffff
1896 ; MIPS32: srl [[T5]],[[T5]],0x10
1897 ; MIPS32: sll [[T5]],[[T5]],0x10
1898 ; MIPS32: or [[T4]],[[T4]],[[T5]]
1899 ; MIPS32: srl [[T11:.*]],a1,0x10
1900 ; MIPS32: andi [[T11]],[[T11]],0x1
1901 ; MIPS32: srl [[T1]],[[T1]],0x10
1756 ; MIPS32: andi [[T1]],[[T1]],0x1 1902 ; MIPS32: andi [[T1]],[[T1]],0x1
1757 ; MIPS32: sll [[T0]],[[T0]],0x1f 1903 ; MIPS32: sll [[T11]],[[T11]],0x1f
1758 ; MIPS32: sll [[T1]],[[T1]],0x1f 1904 ; MIPS32: sll [[T1]],[[T1]],0x1f
1759 ; MIPS32: slt [[T1]],[[T1]],[[T0]] 1905 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
1760 ; MIPS32: andi [[T1]],[[T1]],0xffff 1906 ; MIPS32: sll [[T1]],[[T1]],0x10
1761 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 1907 ; MIPS32: sll [[T4]],[[T4]],0x10
1908 ; MIPS32: srl [[T4]],[[T4]],0x10
1909 ; MIPS32: or v1,[[T1]],[[T4]]
1910 ; MIPS32: move [[T10]],a2
1911 ; MIPS32: andi [[T10]],[[T10]],0xffff
1912 ; MIPS32: andi [[T10]],[[T10]],0x1
1913 ; MIPS32: move [[T11]],[[T2]]
1914 ; MIPS32: andi [[T11]],[[T11]],0xffff
1915 ; MIPS32: andi [[T11]],[[T11]],0x1
1916 ; MIPS32: sll [[T10]],[[T10]],0x1f
1917 ; MIPS32: sll [[T11]],[[T11]],0x1f
1918 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
1919 ; MIPS32: andi [[T11]],[[T11]],0xffff
1920 ; MIPS32: srl [[T6]],[[T6]],0x10
1921 ; MIPS32: sll [[T6]],[[T6]],0x10
1922 ; MIPS32: or [[T11]],[[T11]],[[T6]]
1923 ; MIPS32: srl [[T12:.*]],a2,0x10
1924 ; MIPS32: andi [[T12]],[[T12]],0x1
1925 ; MIPS32: srl [[T2]],[[T2]],0x10
1926 ; MIPS32: andi [[T2]],[[T2]],0x1
1927 ; MIPS32: sll [[T12]],[[T12]],0x1f
1928 ; MIPS32: sll [[T2]],[[T2]],0x1f
1929 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
1762 ; MIPS32: sll [[T2]],[[T2]],0x10 1930 ; MIPS32: sll [[T2]],[[T2]],0x10
1763 ; MIPS32: or [[T1]],[[T1]],[[T2]] 1931 ; MIPS32: sll [[T11]],[[T11]],0x10
1764 ; MIPS32: srl [[T3:.*]],a0,0x10 1932 ; MIPS32: srl [[T11]],[[T11]],0x10
1933 ; MIPS32: or [[T2]],[[T2]],[[T11]]
1934 ; MIPS32: move [[T10]],a3
1935 ; MIPS32: andi [[T10]],[[T10]],0xffff
1936 ; MIPS32: andi [[T10]],[[T10]],0x1
1937 ; MIPS32: move [[T11]],[[T3]]
1938 ; MIPS32: andi [[T11]],[[T11]],0xffff
1939 ; MIPS32: andi [[T11]],[[T11]],0x1
1940 ; MIPS32: sll [[T10]],[[T10]],0x1f
1941 ; MIPS32: sll [[T11]],[[T11]],0x1f
1942 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
1943 ; MIPS32: andi [[T11]],[[T11]],0xffff
1944 ; MIPS32: srl [[T7]],[[T7]],0x10
1945 ; MIPS32: sll [[T7]],[[T7]],0x10
1946 ; MIPS32: or [[T11]],[[T11]],[[T7]]
1947 ; MIPS32: srl [[T13:.*]],a3,0x10
1948 ; MIPS32: andi [[T13]],[[T13]],0x1
1949 ; MIPS32: srl [[T3]],[[T3]],0x10
1765 ; MIPS32: andi [[T3]],[[T3]],0x1 1950 ; MIPS32: andi [[T3]],[[T3]],0x1
1766 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 1951 ; MIPS32: sll [[T13]],[[T13]],0x1f
1767 ; MIPS32: andi [[T4]],[[T4]],0x1
1768 ; MIPS32: sll [[T3]],[[T3]],0x1f 1952 ; MIPS32: sll [[T3]],[[T3]],0x1f
1769 ; MIPS32: sll [[T4]],[[T4]],0x1f 1953 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
1770 ; MIPS32: slt [[T4]],[[T4]],[[T3]] 1954 ; MIPS32: sll [[T3]],[[T3]],0x10
1771 ; MIPS32: sll [[T4]],[[T4]],0x10 1955 ; MIPS32: sll [[T11]],[[T11]],0x10
1772 ; MIPS32: sll [[T1]],[[T1]],0x10 1956 ; MIPS32: srl [[T11]],[[T11]],0x10
1773 ; MIPS32: srl [[T1]],[[T1]],0x10 1957 ; MIPS32: or [[T3]],[[T3]],[[T11]]
1774 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 1958 ; MIPS32: move a0,[[T2]]
1775 ; MIPS32: andi [[T0:.*]],a1,0xffff 1959 ; MIPS32: move a1,[[T3]]
1776 ; MIPS32: andi [[T0]],[[T0]],0x1
1777 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
1778 ; MIPS32: andi [[T1]],[[T1]],0x1
1779 ; MIPS32: sll [[T0]],[[T0]],0x1f
1780 ; MIPS32: sll [[T1]],[[T1]],0x1f
1781 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1782 ; MIPS32: andi [[T1]],[[T1]],0xffff
1783 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
1784 ; MIPS32: sll [[T2]],[[T2]],0x10
1785 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1786 ; MIPS32: srl [[T3:.*]],a1,0x10
1787 ; MIPS32: andi [[T3]],[[T3]],0x1
1788 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
1789 ; MIPS32: andi [[T4]],[[T4]],0x1
1790 ; MIPS32: sll [[T3]],[[T3]],0x1f
1791 ; MIPS32: sll [[T4]],[[T4]],0x1f
1792 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1793 ; MIPS32: sll [[T4]],[[T4]],0x10
1794 ; MIPS32: sll [[T1]],[[T1]],0x10
1795 ; MIPS32: srl [[T1]],[[T1]],0x10
1796 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
1797 ; MIPS32: andi [[T0:.*]],a2,0xffff
1798 ; MIPS32: andi [[T0]],[[T0]],0x1
1799 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
1800 ; MIPS32: andi [[T1]],[[T1]],0x1
1801 ; MIPS32: sll [[T0]],[[T0]],0x1f
1802 ; MIPS32: sll [[T1]],[[T1]],0x1f
1803 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1804 ; MIPS32: andi [[T1]],[[T1]],0xffff
1805 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
1806 ; MIPS32: sll [[T2]],[[T2]],0x10
1807 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1808 ; MIPS32: srl [[T3:.*]],a2,0x10
1809 ; MIPS32: andi [[T3]],[[T3]],0x1
1810 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
1811 ; MIPS32: andi [[T4]],[[T4]],0x1
1812 ; MIPS32: sll [[T3]],[[T3]],0x1f
1813 ; MIPS32: sll [[T4]],[[T4]],0x1f
1814 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1815 ; MIPS32: sll [[T4]],[[T4]],0x10
1816 ; MIPS32: sll [[T1]],[[T1]],0x10
1817 ; MIPS32: srl [[T1]],[[T1]],0x10
1818 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
1819 ; MIPS32: andi [[T0:.*]],a3,0xffff
1820 ; MIPS32: andi [[T0]],[[T0]],0x1
1821 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
1822 ; MIPS32: andi [[T1]],[[T1]],0x1
1823 ; MIPS32: sll [[T0]],[[T0]],0x1f
1824 ; MIPS32: sll [[T1]],[[T1]],0x1f
1825 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1826 ; MIPS32: andi [[T1]],[[T1]],0xffff
1827 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
1828 ; MIPS32: sll [[T2]],[[T2]],0x10
1829 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1830 ; MIPS32: srl [[T3:.*]],a3,0x10
1831 ; MIPS32: andi [[T3]],[[T3]],0x1
1832 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
1833 ; MIPS32: andi [[T4]],[[T4]],0x1
1834 ; MIPS32: sll [[T3]],[[T3]],0x1f
1835 ; MIPS32: sll [[T4]],[[T4]],0x1f
1836 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1837 ; MIPS32: sll [[T4]],[[T4]],0x10
1838 ; MIPS32: sll [[T1]],[[T1]],0x10
1839 ; MIPS32: srl [[T1]],[[T1]],0x10
1840 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
1841 } 1960 }
1842 1961
1843 define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) { 1962 define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) {
1844 entry: 1963 entry:
1845 %res = icmp sle <8 x i1> %a, %b 1964 %res = icmp sle <8 x i1> %a, %b
1846 ret <8 x i1> %res 1965 ret <8 x i1> %res
1847 ; CHECK-LABEL: test_icmp_v8i1_sle 1966 ; CHECK-LABEL: test_icmp_v8i1_sle
1848 ; CHECK: pcmpgtw 1967 ; CHECK: pcmpgtw
1849 ; CHECK: pxor 1968 ; CHECK: pxor
1850 1969
1851 ; MIPS32-LABEL: test_icmp_v8i1_sle 1970 ; MIPS32-LABEL: test_icmp_v8i1_sle
1852 ; MIPS32: lw [[BV_E0:.*]], 1971 ; MIPS32: lw [[T0:.*]],
1853 ; MIPS32: lw [[BV_E1:.*]], 1972 ; MIPS32: lw [[T1:.*]],
1854 ; MIPS32: lw [[BV_E2:.*]], 1973 ; MIPS32: lw [[T2:.*]],
1855 ; MIPS32: lw [[BV_E3:.*]], 1974 ; MIPS32: lw [[T3:.*]],
1856 ; MIPS32: move [[TV_E0:.*]],zero 1975 ; MIPS32: move [[T4:.*]],zero
1857 ; MIPS32: move [[TV_E1:.*]],zero 1976 ; MIPS32: move [[T5:.*]],zero
1858 ; MIPS32: move [[TV_E2:.*]],zero 1977 ; MIPS32: move [[T6:.*]],zero
1859 ; MIPS32: move [[TV_E3:.*]],zero 1978 ; MIPS32: move [[T7:.*]],zero
1860 ; MIPS32: andi [[T0:.*]],a0,0xffff 1979 ; MIPS32: move [[T8:.*]],a0
1980 ; MIPS32: andi [[T8]],[[T8]],0xffff
1981 ; MIPS32: andi [[T8]],[[T8]],0x1
1982 ; MIPS32: move [[T9:.*]],[[T0]]
1983 ; MIPS32: andi [[T9]],[[T9]],0xffff
1984 ; MIPS32: andi [[T9]],[[T9]],0x1
1985 ; MIPS32: sll [[T8]],[[T8]],0x1f
1986 ; MIPS32: sll [[T9]],[[T9]],0x1f
1987 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
1988 ; MIPS32: xori [[T9]],[[T9]],0x1
1989 ; MIPS32: andi [[T9]],[[T9]],0xffff
1990 ; MIPS32: srl [[T4]],[[T4]],0x10
1991 ; MIPS32: sll [[T4]],[[T4]],0x10
1992 ; MIPS32: or [[T9]],[[T9]],[[T4]]
1993 ; MIPS32: srl [[T10:.*]],a0,0x10
1994 ; MIPS32: andi [[T10]],[[T10]],0x1
1995 ; MIPS32: srl [[T0]],[[T0]],0x10
1861 ; MIPS32: andi [[T0]],[[T0]],0x1 1996 ; MIPS32: andi [[T0]],[[T0]],0x1
1862 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 1997 ; MIPS32: sll [[T10]],[[T10]],0x1f
1998 ; MIPS32: sll [[T0]],[[T0]],0x1f
1999 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
2000 ; MIPS32: xori [[T0]],[[T0]],0x1
2001 ; MIPS32: sll [[T0]],[[T0]],0x10
2002 ; MIPS32: sll [[T9]],[[T9]],0x10
2003 ; MIPS32: srl [[T9]],[[T9]],0x10
2004 ; MIPS32: or v0,[[T0]],[[T9]]
2005 ; MIPS32: move [[T10]],a1
2006 ; MIPS32: andi [[T10]],[[T10]],0xffff
2007 ; MIPS32: andi [[T10]],[[T10]],0x1
2008 ; MIPS32: move [[T4]],[[T1]]
2009 ; MIPS32: andi [[T4]],[[T4]],0xffff
2010 ; MIPS32: andi [[T4]],[[T4]],0x1
2011 ; MIPS32: sll [[T10]],[[T10]],0x1f
2012 ; MIPS32: sll [[T4]],[[T4]],0x1f
2013 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
2014 ; MIPS32: xori [[T4]],[[T4]],0x1
2015 ; MIPS32: andi [[T4]],[[T4]],0xffff
2016 ; MIPS32: srl [[T5]],[[T5]],0x10
2017 ; MIPS32: sll [[T5]],[[T5]],0x10
2018 ; MIPS32: or [[T4]],[[T4]],[[T5]]
2019 ; MIPS32: srl [[T11:.*]],a1,0x10
2020 ; MIPS32: andi [[T11]],[[T11]],0x1
2021 ; MIPS32: srl [[T1]],[[T1]],0x10
1863 ; MIPS32: andi [[T1]],[[T1]],0x1 2022 ; MIPS32: andi [[T1]],[[T1]],0x1
1864 ; MIPS32: sll [[T0]],[[T0]],0x1f 2023 ; MIPS32: sll [[T11]],[[T11]],0x1f
1865 ; MIPS32: sll [[T1]],[[T1]],0x1f 2024 ; MIPS32: sll [[T1]],[[T1]],0x1f
1866 ; MIPS32: slt [[T1]],[[T1]],[[T0]] 2025 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
1867 ; MIPS32: xori [[T1]],[[T1]],0x1 2026 ; MIPS32: xori [[T1]],[[T1]],0x1
1868 ; MIPS32: andi [[T1]],[[T1]],0xffff 2027 ; MIPS32: sll [[T1]],[[T1]],0x10
1869 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2028 ; MIPS32: sll [[T4]],[[T4]],0x10
2029 ; MIPS32: srl [[T4]],[[T4]],0x10
2030 ; MIPS32: or v1,[[T1]],[[T4]]
2031 ; MIPS32: move [[T10]],a2
2032 ; MIPS32: andi [[T10]],[[T10]],0xffff
2033 ; MIPS32: andi [[T10]],[[T10]],0x1
2034 ; MIPS32: move [[T11]],[[T2]]
2035 ; MIPS32: andi [[T11]],[[T11]],0xffff
2036 ; MIPS32: andi [[T11]],[[T11]],0x1
2037 ; MIPS32: sll [[T10]],[[T10]],0x1f
2038 ; MIPS32: sll [[T11]],[[T11]],0x1f
2039 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
2040 ; MIPS32: xori [[T11]],[[T11]],0x1
2041 ; MIPS32: andi [[T11]],[[T11]],0xffff
2042 ; MIPS32: srl [[T6]],[[T6]],0x10
2043 ; MIPS32: sll [[T6]],[[T6]],0x10
2044 ; MIPS32: or [[T11]],[[T11]],[[T6]]
2045 ; MIPS32: srl [[T12:.*]],a2,0x10
2046 ; MIPS32: andi [[T12]],[[T12]],0x1
2047 ; MIPS32: srl [[T2]],[[T2]],0x10
2048 ; MIPS32: andi [[T2]],[[T2]],0x1
2049 ; MIPS32: sll [[T12]],[[T12]],0x1f
2050 ; MIPS32: sll [[T2]],[[T2]],0x1f
2051 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
2052 ; MIPS32: xori [[T2]],[[T2]],0x1
1870 ; MIPS32: sll [[T2]],[[T2]],0x10 2053 ; MIPS32: sll [[T2]],[[T2]],0x10
1871 ; MIPS32: or [[T1]],[[T1]],[[T2]] 2054 ; MIPS32: sll [[T11]],[[T11]],0x10
1872 ; MIPS32: srl [[T3:.*]],a0,0x10 2055 ; MIPS32: srl [[T11]],[[T11]],0x10
2056 ; MIPS32: or [[T2]],[[T2]],[[T11]]
2057 ; MIPS32: move [[T10]],a3
2058 ; MIPS32: andi [[T10]],[[T10]],0xffff
2059 ; MIPS32: andi [[T10]],[[T10]],0x1
2060 ; MIPS32: move [[T11]],[[T3]]
2061 ; MIPS32: andi [[T11]],[[T11]],0xffff
2062 ; MIPS32: andi [[T11]],[[T11]],0x1
2063 ; MIPS32: sll [[T10]],[[T10]],0x1f
2064 ; MIPS32: sll [[T11]],[[T11]],0x1f
2065 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
2066 ; MIPS32: xori [[T11]],[[T11]],0x1
2067 ; MIPS32: andi [[T11]],[[T11]],0xffff
2068 ; MIPS32: srl [[T7]],[[T7]],0x10
2069 ; MIPS32: sll [[T7]],[[T7]],0x10
2070 ; MIPS32: or [[T11]],[[T11]],[[T7]]
2071 ; MIPS32: srl [[T13:.*]],a3,0x10
2072 ; MIPS32: andi [[T13]],[[T13]],0x1
2073 ; MIPS32: srl [[T3]],[[T3]],0x10
1873 ; MIPS32: andi [[T3]],[[T3]],0x1 2074 ; MIPS32: andi [[T3]],[[T3]],0x1
1874 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2075 ; MIPS32: sll [[T13]],[[T13]],0x1f
1875 ; MIPS32: andi [[T4]],[[T4]],0x1
1876 ; MIPS32: sll [[T3]],[[T3]],0x1f 2076 ; MIPS32: sll [[T3]],[[T3]],0x1f
1877 ; MIPS32: sll [[T4]],[[T4]],0x1f 2077 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
1878 ; MIPS32: slt [[T4]],[[T4]],[[T3]] 2078 ; MIPS32: xori [[T3]],[[T3]],0x1
1879 ; MIPS32: xori [[T4]],[[T4]],0x1 2079 ; MIPS32: sll [[T3]],[[T3]],0x10
1880 ; MIPS32: sll [[T4]],[[T4]],0x10 2080 ; MIPS32: sll [[T11]],[[T11]],0x10
1881 ; MIPS32: sll [[T1]],[[T1]],0x10 2081 ; MIPS32: srl [[T11]],[[T11]],0x10
1882 ; MIPS32: srl [[T1]],[[T1]],0x10 2082 ; MIPS32: or [[T3]],[[T3]],[[T11]]
1883 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 2083 ; MIPS32: move a0,[[T2]]
1884 ; MIPS32: andi [[T0:.*]],a1,0xffff 2084 ; MIPS32: move a1,[[T3]]
1885 ; MIPS32: andi [[T0]],[[T0]],0x1
1886 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
1887 ; MIPS32: andi [[T1]],[[T1]],0x1
1888 ; MIPS32: sll [[T0]],[[T0]],0x1f
1889 ; MIPS32: sll [[T1]],[[T1]],0x1f
1890 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1891 ; MIPS32: xori [[T1]],[[T1]],0x1
1892 ; MIPS32: andi [[T1]],[[T1]],0xffff
1893 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
1894 ; MIPS32: sll [[T2]],[[T2]],0x10
1895 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1896 ; MIPS32: srl [[T3:.*]],a1,0x10
1897 ; MIPS32: andi [[T3]],[[T3]],0x1
1898 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
1899 ; MIPS32: andi [[T4]],[[T4]],0x1
1900 ; MIPS32: sll [[T3]],[[T3]],0x1f
1901 ; MIPS32: sll [[T4]],[[T4]],0x1f
1902 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1903 ; MIPS32: xori [[T4]],[[T4]],0x1
1904 ; MIPS32: sll [[T4]],[[T4]],0x10
1905 ; MIPS32: sll [[T1]],[[T1]],0x10
1906 ; MIPS32: srl [[T1]],[[T1]],0x10
1907 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
1908 ; MIPS32: andi [[T0:.*]],a2,0xffff
1909 ; MIPS32: andi [[T0]],[[T0]],0x1
1910 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
1911 ; MIPS32: andi [[T1]],[[T1]],0x1
1912 ; MIPS32: sll [[T0]],[[T0]],0x1f
1913 ; MIPS32: sll [[T1]],[[T1]],0x1f
1914 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1915 ; MIPS32: xori [[T1]],[[T1]],0x1
1916 ; MIPS32: andi [[T1]],[[T1]],0xffff
1917 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
1918 ; MIPS32: sll [[T2]],[[T2]],0x10
1919 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1920 ; MIPS32: srl [[T3:.*]],a2,0x10
1921 ; MIPS32: andi [[T3]],[[T3]],0x1
1922 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
1923 ; MIPS32: andi [[T4]],[[T4]],0x1
1924 ; MIPS32: sll [[T3]],[[T3]],0x1f
1925 ; MIPS32: sll [[T4]],[[T4]],0x1f
1926 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1927 ; MIPS32: xori [[T4]],[[T4]],0x1
1928 ; MIPS32: sll [[T4]],[[T4]],0x10
1929 ; MIPS32: sll [[T1]],[[T1]],0x10
1930 ; MIPS32: srl [[T1]],[[T1]],0x10
1931 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
1932 ; MIPS32: andi [[T0:.*]],a3,0xffff
1933 ; MIPS32: andi [[T0]],[[T0]],0x1
1934 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
1935 ; MIPS32: andi [[T1]],[[T1]],0x1
1936 ; MIPS32: sll [[T0]],[[T0]],0x1f
1937 ; MIPS32: sll [[T1]],[[T1]],0x1f
1938 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1939 ; MIPS32: xori [[T1]],[[T1]],0x1
1940 ; MIPS32: andi [[T1]],[[T1]],0xffff
1941 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
1942 ; MIPS32: sll [[T2]],[[T2]],0x10
1943 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1944 ; MIPS32: srl [[T3:.*]],a3,0x10
1945 ; MIPS32: andi [[T3]],[[T3]],0x1
1946 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
1947 ; MIPS32: andi [[T4]],[[T4]],0x1
1948 ; MIPS32: sll [[T3]],[[T3]],0x1f
1949 ; MIPS32: sll [[T4]],[[T4]],0x1f
1950 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1951 ; MIPS32: xori [[T4]],[[T4]],0x1
1952 ; MIPS32: sll [[T4]],[[T4]],0x10
1953 ; MIPS32: sll [[T1]],[[T1]],0x10
1954 ; MIPS32: srl [[T1]],[[T1]],0x10
1955 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
1956 } 2085 }
1957 2086
1958 define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) { 2087 define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) {
1959 entry: 2088 entry:
1960 %res = icmp slt <8 x i1> %a, %b 2089 %res = icmp slt <8 x i1> %a, %b
1961 ret <8 x i1> %res 2090 ret <8 x i1> %res
1962 ; CHECK-LABEL: test_icmp_v8i1_slt 2091 ; CHECK-LABEL: test_icmp_v8i1_slt
1963 ; CHECK: pcmpgtw 2092 ; CHECK: pcmpgtw
1964 2093
1965 ; MIPS32-LABEL: test_icmp_v8i1_slt 2094 ; MIPS32-LABEL: test_icmp_v8i1_slt
1966 ; MIPS32: lw [[BV_E0:.*]], 2095 ; MIPS32: lw [[T0:.*]],
1967 ; MIPS32: lw [[BV_E1:.*]], 2096 ; MIPS32: lw [[T1:.*]],
1968 ; MIPS32: lw [[BV_E2:.*]], 2097 ; MIPS32: lw [[T2:.*]],
1969 ; MIPS32: lw [[BV_E3:.*]], 2098 ; MIPS32: lw [[T3:.*]],
1970 ; MIPS32: move [[TV_E0:.*]],zero 2099 ; MIPS32: move [[T4:.*]],zero
1971 ; MIPS32: move [[TV_E1:.*]],zero 2100 ; MIPS32: move [[T5:.*]],zero
1972 ; MIPS32: move [[TV_E2:.*]],zero 2101 ; MIPS32: move [[T6:.*]],zero
1973 ; MIPS32: move [[TV_E3:.*]],zero 2102 ; MIPS32: move [[T7:.*]],zero
1974 ; MIPS32: andi [[T0:.*]],a0,0xffff 2103 ; MIPS32: move [[T8:.*]],a0
2104 ; MIPS32: andi [[T8]],[[T8]],0xffff
2105 ; MIPS32: andi [[T8]],[[T8]],0x1
2106 ; MIPS32: move [[T9:.*]],[[T0]]
2107 ; MIPS32: andi [[T9]],[[T9]],0xffff
2108 ; MIPS32: andi [[T9]],[[T9]],0x1
2109 ; MIPS32: sll [[T8]],[[T8]],0x1f
2110 ; MIPS32: sll [[T9]],[[T9]],0x1f
2111 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
2112 ; MIPS32: andi [[T8]],[[T8]],0xffff
2113 ; MIPS32: srl [[T4]],[[T4]],0x10
2114 ; MIPS32: sll [[T4]],[[T4]],0x10
2115 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2116 ; MIPS32: srl [[T10:.*]],a0,0x10
2117 ; MIPS32: andi [[T10]],[[T10]],0x1
2118 ; MIPS32: srl [[T0]],[[T0]],0x10
1975 ; MIPS32: andi [[T0]],[[T0]],0x1 2119 ; MIPS32: andi [[T0]],[[T0]],0x1
1976 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 2120 ; MIPS32: sll [[T10]],[[T10]],0x1f
2121 ; MIPS32: sll [[T0]],[[T0]],0x1f
2122 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
2123 ; MIPS32: sll [[T10]],[[T10]],0x10
2124 ; MIPS32: sll [[T8]],[[T8]],0x10
2125 ; MIPS32: srl [[T8]],[[T8]],0x10
2126 ; MIPS32: or [[T10]],[[T10]],[[T8]]
2127 ; MIPS32: move [[T0]],a1
2128 ; MIPS32: andi [[T0]],[[T0]],0xffff
2129 ; MIPS32: andi [[T0]],[[T0]],0x1
2130 ; MIPS32: move [[T4]],[[T1]]
2131 ; MIPS32: andi [[T4]],[[T4]],0xffff
2132 ; MIPS32: andi [[T4]],[[T4]],0x1
2133 ; MIPS32: sll [[T0]],[[T0]],0x1f
2134 ; MIPS32: sll [[T4]],[[T4]],0x1f
2135 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
2136 ; MIPS32: andi [[T0]],[[T0]],0xffff
2137 ; MIPS32: srl [[T5]],[[T5]],0x10
2138 ; MIPS32: sll [[T5]],[[T5]],0x10
2139 ; MIPS32: or [[T0]],[[T0]],[[T5]]
2140 ; MIPS32: srl [[T11:.*]],a1,0x10
2141 ; MIPS32: andi [[T11]],[[T11]],0x1
2142 ; MIPS32: srl [[T1]],[[T1]],0x10
2143 ; MIPS32: andi [[T1]],[[T1]],0x1
2144 ; MIPS32: sll [[T11]],[[T11]],0x1f
2145 ; MIPS32: sll [[T1]],[[T1]],0x1f
2146 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
2147 ; MIPS32: sll [[T11]],[[T11]],0x10
2148 ; MIPS32: sll [[T0]],[[T0]],0x10
2149 ; MIPS32: srl [[T0]],[[T0]],0x10
2150 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2151 ; MIPS32: move [[T0]],a2
2152 ; MIPS32: andi [[T0]],[[T0]],0xffff
2153 ; MIPS32: andi [[T0]],[[T0]],0x1
2154 ; MIPS32: move [[T1]],[[T2]]
2155 ; MIPS32: andi [[T1]],[[T1]],0xffff
1977 ; MIPS32: andi [[T1]],[[T1]],0x1 2156 ; MIPS32: andi [[T1]],[[T1]],0x1
1978 ; MIPS32: sll [[T0]],[[T0]],0x1f 2157 ; MIPS32: sll [[T0]],[[T0]],0x1f
1979 ; MIPS32: sll [[T1]],[[T1]],0x1f 2158 ; MIPS32: sll [[T1]],[[T1]],0x1f
1980 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 2159 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
1981 ; MIPS32: andi [[T0]],[[T0]],0xffff 2160 ; MIPS32: andi [[T0]],[[T0]],0xffff
1982 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2161 ; MIPS32: srl [[T6]],[[T6]],0x10
1983 ; MIPS32: sll [[T2]],[[T2]],0x10 2162 ; MIPS32: sll [[T6]],[[T6]],0x10
1984 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2163 ; MIPS32: or [[T0]],[[T0]],[[T6]]
1985 ; MIPS32: srl [[T3:.*]],a0,0x10 2164 ; MIPS32: srl [[T12:.*]],a2,0x10
1986 ; MIPS32: andi [[T3]],[[T3]],0x1 2165 ; MIPS32: andi [[T12]],[[T12]],0x1
1987 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2166 ; MIPS32: srl [[T2]],[[T2]],0x10
1988 ; MIPS32: andi [[T4]],[[T4]],0x1 2167 ; MIPS32: andi [[T2]],[[T2]],0x1
1989 ; MIPS32: sll [[T3]],[[T3]],0x1f 2168 ; MIPS32: sll [[T12]],[[T12]],0x1f
1990 ; MIPS32: sll [[T4]],[[T4]],0x1f 2169 ; MIPS32: sll [[T2]],[[T2]],0x1f
1991 ; MIPS32: slt [[T3]],[[T3]],[[T4]] 2170 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
1992 ; MIPS32: sll [[T3]],[[T3]],0x10 2171 ; MIPS32: sll [[T12]],[[T12]],0x10
1993 ; MIPS32: sll [[T0]],[[T0]],0x10 2172 ; MIPS32: sll [[T0]],[[T0]],0x10
1994 ; MIPS32: srl [[T0]],[[T0]],0x10 2173 ; MIPS32: srl [[T0]],[[T0]],0x10
1995 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 2174 ; MIPS32: or [[T12]],[[T12]],[[T0]]
1996 ; MIPS32: andi [[T0:.*]],a1,0xffff 2175 ; MIPS32: move [[T0]],a3
2176 ; MIPS32: andi [[T0]],[[T0]],0xffff
1997 ; MIPS32: andi [[T0]],[[T0]],0x1 2177 ; MIPS32: andi [[T0]],[[T0]],0x1
1998 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff 2178 ; MIPS32: move [[T1]],[[T3]]
2179 ; MIPS32: andi [[T1]],[[T1]],0xffff
1999 ; MIPS32: andi [[T1]],[[T1]],0x1 2180 ; MIPS32: andi [[T1]],[[T1]],0x1
2000 ; MIPS32: sll [[T0]],[[T0]],0x1f 2181 ; MIPS32: sll [[T0]],[[T0]],0x1f
2001 ; MIPS32: sll [[T1]],[[T1]],0x1f 2182 ; MIPS32: sll [[T1]],[[T1]],0x1f
2002 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 2183 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2003 ; MIPS32: andi [[T0]],[[T0]],0xffff 2184 ; MIPS32: andi [[T0]],[[T0]],0xffff
2004 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 2185 ; MIPS32: srl [[T7]],[[T7]],0x10
2005 ; MIPS32: sll [[T2]],[[T2]],0x10 2186 ; MIPS32: sll [[T7]],[[T7]],0x10
2006 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2187 ; MIPS32: or [[T0]],[[T0]],[[T7]]
2007 ; MIPS32: srl [[T3:.*]],a1,0x10 2188 ; MIPS32: srl [[T13:.*]],a3,0x10
2189 ; MIPS32: andi [[T13]],[[T13]],0x1
2190 ; MIPS32: srl [[T3]],[[T3]],0x10
2008 ; MIPS32: andi [[T3]],[[T3]],0x1 2191 ; MIPS32: andi [[T3]],[[T3]],0x1
2009 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 2192 ; MIPS32: sll [[T13]],[[T13]],0x1f
2010 ; MIPS32: andi [[T4]],[[T4]],0x1
2011 ; MIPS32: sll [[T3]],[[T3]],0x1f 2193 ; MIPS32: sll [[T3]],[[T3]],0x1f
2012 ; MIPS32: sll [[T4]],[[T4]],0x1f 2194 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
2013 ; MIPS32: slt [[T3]],[[T3]],[[T4]] 2195 ; MIPS32: sll [[T13]],[[T13]],0x10
2014 ; MIPS32: sll [[T3]],[[T3]],0x10
2015 ; MIPS32: sll [[T0]],[[T0]],0x10 2196 ; MIPS32: sll [[T0]],[[T0]],0x10
2016 ; MIPS32: srl [[T0]],[[T0]],0x10 2197 ; MIPS32: srl [[T0]],[[T0]],0x10
2017 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] 2198 ; MIPS32: or [[T13]],[[T13]],[[T0]]
2018 ; MIPS32: andi [[T0:.*]],a2,0xffff 2199 ; MIPS32: move v0,[[T10]]
2019 ; MIPS32: andi [[T0]],[[T0]],0x1 2200 ; MIPS32: move v1,[[T11]]
2020 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff 2201 ; MIPS32: move a0,[[T12]]
2021 ; MIPS32: andi [[T1]],[[T1]],0x1 2202 ; MIPS32: move a1,[[T13]]
2022 ; MIPS32: sll [[T0]],[[T0]],0x1f
2023 ; MIPS32: sll [[T1]],[[T1]],0x1f
2024 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2025 ; MIPS32: andi [[T0]],[[T0]],0xffff
2026 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2027 ; MIPS32: sll [[T2]],[[T2]],0x10
2028 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2029 ; MIPS32: srl [[T3:.*]],a2,0x10
2030 ; MIPS32: andi [[T3]],[[T3]],0x1
2031 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2032 ; MIPS32: andi [[T4]],[[T4]],0x1
2033 ; MIPS32: sll [[T3]],[[T3]],0x1f
2034 ; MIPS32: sll [[T4]],[[T4]],0x1f
2035 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
2036 ; MIPS32: sll [[T3]],[[T3]],0x10
2037 ; MIPS32: sll [[T0]],[[T0]],0x10
2038 ; MIPS32: srl [[T0]],[[T0]],0x10
2039 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2040 ; MIPS32: andi [[T0:.*]],a3,0xffff
2041 ; MIPS32: andi [[T0]],[[T0]],0x1
2042 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2043 ; MIPS32: andi [[T1]],[[T1]],0x1
2044 ; MIPS32: sll [[T0]],[[T0]],0x1f
2045 ; MIPS32: sll [[T1]],[[T1]],0x1f
2046 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2047 ; MIPS32: andi [[T0]],[[T0]],0xffff
2048 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2049 ; MIPS32: sll [[T2]],[[T2]],0x10
2050 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2051 ; MIPS32: srl [[T3:.*]],a3,0x10
2052 ; MIPS32: andi [[T3]],[[T3]],0x1
2053 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2054 ; MIPS32: andi [[T4]],[[T4]],0x1
2055 ; MIPS32: sll [[T3]],[[T3]],0x1f
2056 ; MIPS32: sll [[T4]],[[T4]],0x1f
2057 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
2058 ; MIPS32: sll [[T3]],[[T3]],0x10
2059 ; MIPS32: sll [[T0]],[[T0]],0x10
2060 ; MIPS32: srl [[T0]],[[T0]],0x10
2061 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
2062 } 2203 }
2063 2204
2064 define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) { 2205 define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) {
2065 entry: 2206 entry:
2066 %res = icmp uge <8 x i1> %a, %b 2207 %res = icmp uge <8 x i1> %a, %b
2067 ret <8 x i1> %res 2208 ret <8 x i1> %res
2068 ; CHECK-LABEL: test_icmp_v8i1_uge 2209 ; CHECK-LABEL: test_icmp_v8i1_uge
2069 ; CHECK: pxor 2210 ; CHECK: pxor
2070 ; CHECK: pcmpgtw 2211 ; CHECK: pcmpgtw
2071 ; CHECK: pxor 2212 ; CHECK: pxor
2072 2213
2073 ; MIPS32-LABEL: test_icmp_v8i1_uge 2214 ; MIPS32-LABEL: test_icmp_v8i1_uge
2074 ; MIPS32: lw [[BV_E0:.*]], 2215 ; MIPS32: lw [[T0:.*]],
2075 ; MIPS32: lw [[BV_E1:.*]], 2216 ; MIPS32: lw [[T1:.*]],
2076 ; MIPS32: lw [[BV_E2:.*]], 2217 ; MIPS32: lw [[T2:.*]],
2077 ; MIPS32: lw [[BV_E3:.*]], 2218 ; MIPS32: lw [[T3:.*]],
2078 ; MIPS32: move [[TV_E0:.*]],zero 2219 ; MIPS32: move [[T4:.*]],zero
2079 ; MIPS32: move [[TV_E1:.*]],zero 2220 ; MIPS32: move [[T5:.*]],zero
2080 ; MIPS32: move [[TV_E2:.*]],zero 2221 ; MIPS32: move [[T6:.*]],zero
2081 ; MIPS32: move [[TV_E3:.*]],zero 2222 ; MIPS32: move [[T7:.*]],zero
2082 ; MIPS32: andi [[T0:.*]],a0,0xffff 2223 ; MIPS32: move [[T8:.*]],a0
2224 ; MIPS32: andi [[T8]],[[T8]],0xffff
2225 ; MIPS32: andi [[T8]],[[T8]],0x1
2226 ; MIPS32: move [[T9:.*]],[[T0]]
2227 ; MIPS32: andi [[T9]],[[T9]],0xffff
2228 ; MIPS32: andi [[T9]],[[T9]],0x1
2229 ; MIPS32: sll [[T8]],[[T8]],0x1f
2230 ; MIPS32: sll [[T9]],[[T9]],0x1f
2231 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
2232 ; MIPS32: xori [[T8]],[[T8]],0x1
2233 ; MIPS32: andi [[T8]],[[T8]],0xffff
2234 ; MIPS32: srl [[T4]],[[T4]],0x10
2235 ; MIPS32: sll [[T4]],[[T4]],0x10
2236 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2237 ; MIPS32: srl [[T10:.*]],a0,0x10
2238 ; MIPS32: andi [[T10]],[[T10]],0x1
2239 ; MIPS32: srl [[T0]],[[T0]],0x10
2083 ; MIPS32: andi [[T0]],[[T0]],0x1 2240 ; MIPS32: andi [[T0]],[[T0]],0x1
2084 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 2241 ; MIPS32: sll [[T10]],[[T10]],0x1f
2242 ; MIPS32: sll [[T0]],[[T0]],0x1f
2243 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
2244 ; MIPS32: xori [[T10]],[[T10]],0x1
2245 ; MIPS32: sll [[T10]],[[T10]],0x10
2246 ; MIPS32: sll [[T8]],[[T8]],0x10
2247 ; MIPS32: srl [[T8]],[[T8]],0x10
2248 ; MIPS32: or [[T10]],[[T10]],[[T8]]
2249 ; MIPS32: move [[T0]],a1
2250 ; MIPS32: andi [[T0]],[[T0]],0xffff
2251 ; MIPS32: andi [[T0]],[[T0]],0x1
2252 ; MIPS32: move [[T4]],[[T1]]
2253 ; MIPS32: andi [[T4]],[[T4]],0xffff
2254 ; MIPS32: andi [[T4]],[[T4]],0x1
2255 ; MIPS32: sll [[T0]],[[T0]],0x1f
2256 ; MIPS32: sll [[T4]],[[T4]],0x1f
2257 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
2258 ; MIPS32: xori [[T0]],[[T0]],0x1
2259 ; MIPS32: andi [[T0]],[[T0]],0xffff
2260 ; MIPS32: srl [[T5]],[[T5]],0x10
2261 ; MIPS32: sll [[T5]],[[T5]],0x10
2262 ; MIPS32: or [[T0]],[[T0]],[[T5]]
2263 ; MIPS32: srl [[T11:.*]],a1,0x10
2264 ; MIPS32: andi [[T11]],[[T11]],0x1
2265 ; MIPS32: srl [[T1]],[[T1]],0x10
2266 ; MIPS32: andi [[T1]],[[T1]],0x1
2267 ; MIPS32: sll [[T11]],[[T11]],0x1f
2268 ; MIPS32: sll [[T1]],[[T1]],0x1f
2269 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
2270 ; MIPS32: xori [[T11]],[[T11]],0x1
2271 ; MIPS32: sll [[T11]],[[T11]],0x10
2272 ; MIPS32: sll [[T0]],[[T0]],0x10
2273 ; MIPS32: srl [[T0]],[[T0]],0x10
2274 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2275 ; MIPS32: move [[T0]],a2
2276 ; MIPS32: andi [[T0]],[[T0]],0xffff
2277 ; MIPS32: andi [[T0]],[[T0]],0x1
2278 ; MIPS32: move [[T1]],[[T2]]
2279 ; MIPS32: andi [[T1]],[[T1]],0xffff
2085 ; MIPS32: andi [[T1]],[[T1]],0x1 2280 ; MIPS32: andi [[T1]],[[T1]],0x1
2086 ; MIPS32: sll [[T0]],[[T0]],0x1f 2281 ; MIPS32: sll [[T0]],[[T0]],0x1f
2087 ; MIPS32: sll [[T1]],[[T1]],0x1f 2282 ; MIPS32: sll [[T1]],[[T1]],0x1f
2088 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2283 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2089 ; MIPS32: xori [[T0]],[[T0]],0x1 2284 ; MIPS32: xori [[T0]],[[T0]],0x1
2090 ; MIPS32: andi [[T0]],[[T0]],0xffff 2285 ; MIPS32: andi [[T0]],[[T0]],0xffff
2091 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2286 ; MIPS32: srl [[T6]],[[T6]],0x10
2092 ; MIPS32: sll [[T2]],[[T2]],0x10 2287 ; MIPS32: sll [[T6]],[[T6]],0x10
2093 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2288 ; MIPS32: or [[T0]],[[T0]],[[T6]]
2094 ; MIPS32: srl [[T3:.*]],a0,0x10 2289 ; MIPS32: srl [[T12:.*]],a2,0x10
2095 ; MIPS32: andi [[T3]],[[T3]],0x1 2290 ; MIPS32: andi [[T12]],[[T12]],0x1
2096 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2291 ; MIPS32: srl [[T2]],[[T2]],0x10
2097 ; MIPS32: andi [[T4]],[[T4]],0x1 2292 ; MIPS32: andi [[T2]],[[T2]],0x1
2098 ; MIPS32: sll [[T3]],[[T3]],0x1f 2293 ; MIPS32: sll [[T12]],[[T12]],0x1f
2099 ; MIPS32: sll [[T4]],[[T4]],0x1f 2294 ; MIPS32: sll [[T2]],[[T2]],0x1f
2100 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 2295 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
2101 ; MIPS32: xori [[T3]],[[T3]],0x1 2296 ; MIPS32: xori [[T12]],[[T12]],0x1
2102 ; MIPS32: sll [[T3]],[[T3]],0x10 2297 ; MIPS32: sll [[T12]],[[T12]],0x10
2103 ; MIPS32: sll [[T0]],[[T0]],0x10 2298 ; MIPS32: sll [[T0]],[[T0]],0x10
2104 ; MIPS32: srl [[T0]],[[T0]],0x10 2299 ; MIPS32: srl [[T0]],[[T0]],0x10
2105 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 2300 ; MIPS32: or [[T12]],[[T12]],[[T0]]
2106 ; MIPS32: andi [[T0:.*]],a1,0xffff 2301 ; MIPS32: move [[T0]],a3
2302 ; MIPS32: andi [[T0]],[[T0]],0xffff
2107 ; MIPS32: andi [[T0]],[[T0]],0x1 2303 ; MIPS32: andi [[T0]],[[T0]],0x1
2108 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff 2304 ; MIPS32: move [[T1]],[[T3]]
2305 ; MIPS32: andi [[T1]],[[T1]],0xffff
2109 ; MIPS32: andi [[T1]],[[T1]],0x1 2306 ; MIPS32: andi [[T1]],[[T1]],0x1
2110 ; MIPS32: sll [[T0]],[[T0]],0x1f 2307 ; MIPS32: sll [[T0]],[[T0]],0x1f
2111 ; MIPS32: sll [[T1]],[[T1]],0x1f 2308 ; MIPS32: sll [[T1]],[[T1]],0x1f
2112 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2309 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2113 ; MIPS32: xori [[T0]],[[T0]],0x1 2310 ; MIPS32: xori [[T0]],[[T0]],0x1
2114 ; MIPS32: andi [[T0]],[[T0]],0xffff 2311 ; MIPS32: andi [[T0]],[[T0]],0xffff
2115 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 2312 ; MIPS32: srl [[T7]],[[T7]],0x10
2116 ; MIPS32: sll [[T2]],[[T2]],0x10 2313 ; MIPS32: sll [[T7]],[[T7]],0x10
2117 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2314 ; MIPS32: or [[T0]],[[T0]],[[T7]]
2118 ; MIPS32: srl [[T3:.*]],a1,0x10 2315 ; MIPS32: srl [[T13:.*]],a3,0x10
2316 ; MIPS32: andi [[T13]],[[T13]],0x1
2317 ; MIPS32: srl [[T3]],[[T3]],0x10
2119 ; MIPS32: andi [[T3]],[[T3]],0x1 2318 ; MIPS32: andi [[T3]],[[T3]],0x1
2120 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 2319 ; MIPS32: sll [[T13]],[[T13]],0x1f
2121 ; MIPS32: andi [[T4]],[[T4]],0x1
2122 ; MIPS32: sll [[T3]],[[T3]],0x1f 2320 ; MIPS32: sll [[T3]],[[T3]],0x1f
2123 ; MIPS32: sll [[T4]],[[T4]],0x1f 2321 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
2124 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 2322 ; MIPS32: xori [[T13]],[[T13]],0x1
2125 ; MIPS32: xori [[T3]],[[T3]],0x1 2323 ; MIPS32: sll [[T13]],[[T13]],0x10
2126 ; MIPS32: sll [[T3]],[[T3]],0x10
2127 ; MIPS32: sll [[T0]],[[T0]],0x10 2324 ; MIPS32: sll [[T0]],[[T0]],0x10
2128 ; MIPS32: srl [[T0]],[[T0]],0x10 2325 ; MIPS32: srl [[T0]],[[T0]],0x10
2129 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] 2326 ; MIPS32: or [[T13]],[[T13]],[[T0]]
2130 ; MIPS32: andi [[T0:.*]],a2,0xffff 2327 ; MIPS32: move v0,[[T10]]
2131 ; MIPS32: andi [[T0]],[[T0]],0x1 2328 ; MIPS32: move v1,[[T11]]
2132 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff 2329 ; MIPS32: move a0,[[T12]]
2133 ; MIPS32: andi [[T1]],[[T1]],0x1 2330 ; MIPS32: move a1,[[T13]]
2134 ; MIPS32: sll [[T0]],[[T0]],0x1f
2135 ; MIPS32: sll [[T1]],[[T1]],0x1f
2136 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2137 ; MIPS32: xori [[T0]],[[T0]],0x1
2138 ; MIPS32: andi [[T0]],[[T0]],0xffff
2139 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2140 ; MIPS32: sll [[T2]],[[T2]],0x10
2141 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2142 ; MIPS32: srl [[T3:.*]],a2,0x10
2143 ; MIPS32: andi [[T3]],[[T3]],0x1
2144 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2145 ; MIPS32: andi [[T4]],[[T4]],0x1
2146 ; MIPS32: sll [[T3]],[[T3]],0x1f
2147 ; MIPS32: sll [[T4]],[[T4]],0x1f
2148 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2149 ; MIPS32: xori [[T3]],[[T3]],0x1
2150 ; MIPS32: sll [[T3]],[[T3]],0x10
2151 ; MIPS32: sll [[T0]],[[T0]],0x10
2152 ; MIPS32: srl [[T0]],[[T0]],0x10
2153 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2154 ; MIPS32: andi [[T0:.*]],a3,0xffff
2155 ; MIPS32: andi [[T0]],[[T0]],0x1
2156 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2157 ; MIPS32: andi [[T1]],[[T1]],0x1
2158 ; MIPS32: sll [[T0]],[[T0]],0x1f
2159 ; MIPS32: sll [[T1]],[[T1]],0x1f
2160 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2161 ; MIPS32: xori [[T0]],[[T0]],0x1
2162 ; MIPS32: andi [[T0]],[[T0]],0xffff
2163 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2164 ; MIPS32: sll [[T2]],[[T2]],0x10
2165 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2166 ; MIPS32: srl [[T3:.*]],a3,0x10
2167 ; MIPS32: andi [[T3]],[[T3]],0x1
2168 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2169 ; MIPS32: andi [[T4]],[[T4]],0x1
2170 ; MIPS32: sll [[T3]],[[T3]],0x1f
2171 ; MIPS32: sll [[T4]],[[T4]],0x1f
2172 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2173 ; MIPS32: xori [[T3]],[[T3]],0x1
2174 ; MIPS32: sll [[T3]],[[T3]],0x10
2175 ; MIPS32: sll [[T0]],[[T0]],0x10
2176 ; MIPS32: srl [[T0]],[[T0]],0x10
2177 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
2178 } 2331 }
2179 2332
2180 define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) { 2333 define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) {
2181 entry: 2334 entry:
2182 %res = icmp ugt <8 x i1> %a, %b 2335 %res = icmp ugt <8 x i1> %a, %b
2183 ret <8 x i1> %res 2336 ret <8 x i1> %res
2184 ; CHECK-LABEL: test_icmp_v8i1_ugt 2337 ; CHECK-LABEL: test_icmp_v8i1_ugt
2185 ; CHECK: pxor 2338 ; CHECK: pxor
2186 ; CHECK: pcmpgtw 2339 ; CHECK: pcmpgtw
2187 2340
2188 ; MIPS32-LABEL: test_icmp_v8i1_ugt 2341 ; MIPS32-LABEL: test_icmp_v8i1_ugt
2189 ; MIPS32: lw [[BV_E0:.*]], 2342 ; MIPS32: lw [[T0:.*]],
2190 ; MIPS32: lw [[BV_E1:.*]], 2343 ; MIPS32: lw [[T1:.*]],
2191 ; MIPS32: lw [[BV_E2:.*]], 2344 ; MIPS32: lw [[T2:.*]],
2192 ; MIPS32: lw [[BV_E3:.*]], 2345 ; MIPS32: lw [[T3:.*]],
2193 ; MIPS32: move [[TV_E0:.*]],zero 2346 ; MIPS32: move [[T4:.*]],zero
2194 ; MIPS32: move [[TV_E1:.*]],zero 2347 ; MIPS32: move [[T5:.*]],zero
2195 ; MIPS32: move [[TV_E2:.*]],zero 2348 ; MIPS32: move [[T6:.*]],zero
2196 ; MIPS32: move [[TV_E3:.*]],zero 2349 ; MIPS32: move [[T7:.*]],zero
2197 ; MIPS32: andi [[T0:.*]],a0,0xffff 2350 ; MIPS32: move [[T8:.*]],a0
2351 ; MIPS32: andi [[T8]],[[T8]],0xffff
2352 ; MIPS32: andi [[T8]],[[T8]],0x1
2353 ; MIPS32: move [[T9:.*]],[[T0]]
2354 ; MIPS32: andi [[T9]],[[T9]],0xffff
2355 ; MIPS32: andi [[T9]],[[T9]],0x1
2356 ; MIPS32: sll [[T8]],[[T8]],0x1f
2357 ; MIPS32: sll [[T9]],[[T9]],0x1f
2358 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
2359 ; MIPS32: andi [[T9]],[[T9]],0xffff
2360 ; MIPS32: srl [[T4]],[[T4]],0x10
2361 ; MIPS32: sll [[T4]],[[T4]],0x10
2362 ; MIPS32: or [[T9]],[[T9]],[[T4]]
2363 ; MIPS32: srl [[T10:.*]],a0,0x10
2364 ; MIPS32: andi [[T10]],[[T10]],0x1
2365 ; MIPS32: srl [[T0]],[[T0]],0x10
2198 ; MIPS32: andi [[T0]],[[T0]],0x1 2366 ; MIPS32: andi [[T0]],[[T0]],0x1
2199 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 2367 ; MIPS32: sll [[T10]],[[T10]],0x1f
2368 ; MIPS32: sll [[T0]],[[T0]],0x1f
2369 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
2370 ; MIPS32: sll [[T0]],[[T0]],0x10
2371 ; MIPS32: sll [[T9]],[[T9]],0x10
2372 ; MIPS32: srl [[T9]],[[T9]],0x10
2373 ; MIPS32: or v0,[[T0]],[[T9]]
2374 ; MIPS32: move [[T10]],a1
2375 ; MIPS32: andi [[T10]],[[T10]],0xffff
2376 ; MIPS32: andi [[T10]],[[T10]],0x1
2377 ; MIPS32: move [[T4]],[[T1]]
2378 ; MIPS32: andi [[T4]],[[T4]],0xffff
2379 ; MIPS32: andi [[T4]],[[T4]],0x1
2380 ; MIPS32: sll [[T10]],[[T10]],0x1f
2381 ; MIPS32: sll [[T4]],[[T4]],0x1f
2382 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
2383 ; MIPS32: andi [[T4]],[[T4]],0xffff
2384 ; MIPS32: srl [[T5]],[[T5]],0x10
2385 ; MIPS32: sll [[T5]],[[T5]],0x10
2386 ; MIPS32: or [[T4]],[[T4]],[[T5]]
2387 ; MIPS32: srl [[T11:.*]],a1,0x10
2388 ; MIPS32: andi [[T11]],[[T11]],0x1
2389 ; MIPS32: srl [[T1]],[[T1]],0x10
2200 ; MIPS32: andi [[T1]],[[T1]],0x1 2390 ; MIPS32: andi [[T1]],[[T1]],0x1
2201 ; MIPS32: sll [[T0]],[[T0]],0x1f 2391 ; MIPS32: sll [[T11]],[[T11]],0x1f
2202 ; MIPS32: sll [[T1]],[[T1]],0x1f 2392 ; MIPS32: sll [[T1]],[[T1]],0x1f
2203 ; MIPS32: sltu [[T1]],[[T1]],[[T0]] 2393 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
2204 ; MIPS32: andi [[T1]],[[T1]],0xffff 2394 ; MIPS32: sll [[T1]],[[T1]],0x10
2205 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2395 ; MIPS32: sll [[T4]],[[T4]],0x10
2396 ; MIPS32: srl [[T4]],[[T4]],0x10
2397 ; MIPS32: or v1,[[T1]],[[T4]]
2398 ; MIPS32: move [[T10]],a2
2399 ; MIPS32: andi [[T10]],[[T10]],0xffff
2400 ; MIPS32: andi [[T10]],[[T10]],0x1
2401 ; MIPS32: move [[T11]],[[T2]]
2402 ; MIPS32: andi [[T11]],[[T11]],0xffff
2403 ; MIPS32: andi [[T11]],[[T11]],0x1
2404 ; MIPS32: sll [[T10]],[[T10]],0x1f
2405 ; MIPS32: sll [[T11]],[[T11]],0x1f
2406 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
2407 ; MIPS32: andi [[T11]],[[T11]],0xffff
2408 ; MIPS32: srl [[T6]],[[T6]],0x10
2409 ; MIPS32: sll [[T6]],[[T6]],0x10
2410 ; MIPS32: or [[T11]],[[T11]],[[T6]]
2411 ; MIPS32: srl [[T12:.*]],a2,0x10
2412 ; MIPS32: andi [[T12]],[[T12]],0x1
2413 ; MIPS32: srl [[T2]],[[T2]],0x10
2414 ; MIPS32: andi [[T2]],[[T2]],0x1
2415 ; MIPS32: sll [[T12]],[[T12]],0x1f
2416 ; MIPS32: sll [[T2]],[[T2]],0x1f
2417 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
2206 ; MIPS32: sll [[T2]],[[T2]],0x10 2418 ; MIPS32: sll [[T2]],[[T2]],0x10
2207 ; MIPS32: or [[T1]],[[T1]],[[T2]] 2419 ; MIPS32: sll [[T11]],[[T11]],0x10
2208 ; MIPS32: srl [[T3:.*]],a0,0x10 2420 ; MIPS32: srl [[T11]],[[T11]],0x10
2421 ; MIPS32: or [[T2]],[[T2]],[[T11]]
2422 ; MIPS32: move [[T10]],a3
2423 ; MIPS32: andi [[T10]],[[T10]],0xffff
2424 ; MIPS32: andi [[T10]],[[T10]],0x1
2425 ; MIPS32: move [[T11]],[[T3]]
2426 ; MIPS32: andi [[T11]],[[T11]],0xffff
2427 ; MIPS32: andi [[T11]],[[T11]],0x1
2428 ; MIPS32: sll [[T10]],[[T10]],0x1f
2429 ; MIPS32: sll [[T11]],[[T11]],0x1f
2430 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
2431 ; MIPS32: andi [[T11]],[[T11]],0xffff
2432 ; MIPS32: srl [[T7]],[[T7]],0x10
2433 ; MIPS32: sll [[T7]],[[T7]],0x10
2434 ; MIPS32: or [[T11]],[[T11]],[[T7]]
2435 ; MIPS32: srl [[T13:.*]],a3,0x10
2436 ; MIPS32: andi [[T13]],[[T13]],0x1
2437 ; MIPS32: srl [[T3]],[[T3]],0x10
2209 ; MIPS32: andi [[T3]],[[T3]],0x1 2438 ; MIPS32: andi [[T3]],[[T3]],0x1
2210 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2439 ; MIPS32: sll [[T13]],[[T13]],0x1f
2211 ; MIPS32: andi [[T4]],[[T4]],0x1
2212 ; MIPS32: sll [[T3]],[[T3]],0x1f 2440 ; MIPS32: sll [[T3]],[[T3]],0x1f
2213 ; MIPS32: sll [[T4]],[[T4]],0x1f 2441 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
2214 ; MIPS32: sltu [[T4]],[[T4]],[[T3]] 2442 ; MIPS32: sll [[T3]],[[T3]],0x10
2215 ; MIPS32: sll [[T4]],[[T4]],0x10 2443 ; MIPS32: sll [[T11]],[[T11]],0x10
2216 ; MIPS32: sll [[T1]],[[T1]],0x10 2444 ; MIPS32: srl [[T11]],[[T11]],0x10
2217 ; MIPS32: srl [[T1]],[[T1]],0x10 2445 ; MIPS32: or [[T3]],[[T3]],[[T11]]
2218 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 2446 ; MIPS32: move a0,[[T2]]
2219 ; MIPS32: andi [[T0:.*]],a1,0xffff 2447 ; MIPS32: move a1,[[T3]]
2220 ; MIPS32: andi [[T0]],[[T0]],0x1
2221 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2222 ; MIPS32: andi [[T1]],[[T1]],0x1
2223 ; MIPS32: sll [[T0]],[[T0]],0x1f
2224 ; MIPS32: sll [[T1]],[[T1]],0x1f
2225 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2226 ; MIPS32: andi [[T1]],[[T1]],0xffff
2227 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2228 ; MIPS32: sll [[T2]],[[T2]],0x10
2229 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2230 ; MIPS32: srl [[T3:.*]],a1,0x10
2231 ; MIPS32: andi [[T3]],[[T3]],0x1
2232 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2233 ; MIPS32: andi [[T4]],[[T4]],0x1
2234 ; MIPS32: sll [[T3]],[[T3]],0x1f
2235 ; MIPS32: sll [[T4]],[[T4]],0x1f
2236 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2237 ; MIPS32: sll [[T4]],[[T4]],0x10
2238 ; MIPS32: sll [[T1]],[[T1]],0x10
2239 ; MIPS32: srl [[T1]],[[T1]],0x10
2240 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
2241 ; MIPS32: andi [[T0:.*]],a2,0xffff
2242 ; MIPS32: andi [[T0]],[[T0]],0x1
2243 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2244 ; MIPS32: andi [[T1]],[[T1]],0x1
2245 ; MIPS32: sll [[T0]],[[T0]],0x1f
2246 ; MIPS32: sll [[T1]],[[T1]],0x1f
2247 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2248 ; MIPS32: andi [[T1]],[[T1]],0xffff
2249 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2250 ; MIPS32: sll [[T2]],[[T2]],0x10
2251 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2252 ; MIPS32: srl [[T3:.*]],a2,0x10
2253 ; MIPS32: andi [[T3]],[[T3]],0x1
2254 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2255 ; MIPS32: andi [[T4]],[[T4]],0x1
2256 ; MIPS32: sll [[T3]],[[T3]],0x1f
2257 ; MIPS32: sll [[T4]],[[T4]],0x1f
2258 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2259 ; MIPS32: sll [[T4]],[[T4]],0x10
2260 ; MIPS32: sll [[T1]],[[T1]],0x10
2261 ; MIPS32: srl [[T1]],[[T1]],0x10
2262 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
2263 ; MIPS32: andi [[T0:.*]],a3,0xffff
2264 ; MIPS32: andi [[T0]],[[T0]],0x1
2265 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2266 ; MIPS32: andi [[T1]],[[T1]],0x1
2267 ; MIPS32: sll [[T0]],[[T0]],0x1f
2268 ; MIPS32: sll [[T1]],[[T1]],0x1f
2269 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2270 ; MIPS32: andi [[T1]],[[T1]],0xffff
2271 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2272 ; MIPS32: sll [[T2]],[[T2]],0x10
2273 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2274 ; MIPS32: srl [[T3:.*]],a3,0x10
2275 ; MIPS32: andi [[T3]],[[T3]],0x1
2276 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2277 ; MIPS32: andi [[T4]],[[T4]],0x1
2278 ; MIPS32: sll [[T3]],[[T3]],0x1f
2279 ; MIPS32: sll [[T4]],[[T4]],0x1f
2280 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2281 ; MIPS32: sll [[T4]],[[T4]],0x10
2282 ; MIPS32: sll [[T1]],[[T1]],0x10
2283 ; MIPS32: srl [[T1]],[[T1]],0x10
2284 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
2285 } 2448 }
2286 2449
2287 define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) { 2450 define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) {
2288 entry: 2451 entry:
2289 %res = icmp ule <8 x i1> %a, %b 2452 %res = icmp ule <8 x i1> %a, %b
2290 ret <8 x i1> %res 2453 ret <8 x i1> %res
2291 ; CHECK-LABEL: test_icmp_v8i1_ule 2454 ; CHECK-LABEL: test_icmp_v8i1_ule
2292 ; CHECK: pxor 2455 ; CHECK: pxor
2293 ; CHECK: pcmpgtw 2456 ; CHECK: pcmpgtw
2294 ; CHECK: pxor 2457 ; CHECK: pxor
2295 2458
2296 ; MIPS32-LABEL: test_icmp_v8i1_ule 2459 ; MIPS32-LABEL: test_icmp_v8i1_ule
2297 ; MIPS32: lw [[BV_E0:.*]], 2460 ; MIPS32: lw [[T0:.*]],
2298 ; MIPS32: lw [[BV_E1:.*]], 2461 ; MIPS32: lw [[T1:.*]],
2299 ; MIPS32: lw [[BV_E2:.*]], 2462 ; MIPS32: lw [[T2:.*]],
2300 ; MIPS32: lw [[BV_E3:.*]], 2463 ; MIPS32: lw [[T3:.*]],
2301 ; MIPS32: move [[TV_E0:.*]],zero 2464 ; MIPS32: move [[T4:.*]],zero
2302 ; MIPS32: move [[TV_E1:.*]],zero 2465 ; MIPS32: move [[T5:.*]],zero
2303 ; MIPS32: move [[TV_E2:.*]],zero 2466 ; MIPS32: move [[T6:.*]],zero
2304 ; MIPS32: move [[TV_E3:.*]],zero 2467 ; MIPS32: move [[T7:.*]],zero
2305 ; MIPS32: andi [[T0:.*]],a0,0xffff 2468 ; MIPS32: move [[T8:.*]],a0
2469 ; MIPS32: andi [[T8]],[[T8]],0xffff
2470 ; MIPS32: andi [[T8]],[[T8]],0x1
2471 ; MIPS32: move [[T9:.*]],[[T0]]
2472 ; MIPS32: andi [[T9]],[[T9]],0xffff
2473 ; MIPS32: andi [[T9]],[[T9]],0x1
2474 ; MIPS32: sll [[T8]],[[T8]],0x1f
2475 ; MIPS32: sll [[T9]],[[T9]],0x1f
2476 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
2477 ; MIPS32: xori [[T9]],[[T9]],0x1
2478 ; MIPS32: andi [[T9]],[[T9]],0xffff
2479 ; MIPS32: srl [[T4]],[[T4]],0x10
2480 ; MIPS32: sll [[T4]],[[T4]],0x10
2481 ; MIPS32: or [[T9]],[[T9]],[[T4]]
2482 ; MIPS32: srl [[T10:.*]],a0,0x10
2483 ; MIPS32: andi [[T10]],[[T10]],0x1
2484 ; MIPS32: srl [[T0]],[[T0]],0x10
2306 ; MIPS32: andi [[T0]],[[T0]],0x1 2485 ; MIPS32: andi [[T0]],[[T0]],0x1
2307 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 2486 ; MIPS32: sll [[T10]],[[T10]],0x1f
2487 ; MIPS32: sll [[T0]],[[T0]],0x1f
2488 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
2489 ; MIPS32: xori [[T0]],[[T0]],0x1
2490 ; MIPS32: sll [[T0]],[[T0]],0x10
2491 ; MIPS32: sll [[T9]],[[T9]],0x10
2492 ; MIPS32: srl [[T9]],[[T9]],0x10
2493 ; MIPS32: or v0,[[T0]],[[T9]]
2494 ; MIPS32: move [[T10]],a1
2495 ; MIPS32: andi [[T10]],[[T10]],0xffff
2496 ; MIPS32: andi [[T10]],[[T10]],0x1
2497 ; MIPS32: move [[T4]],[[T1]]
2498 ; MIPS32: andi [[T4]],[[T4]],0xffff
2499 ; MIPS32: andi [[T4]],[[T4]],0x1
2500 ; MIPS32: sll [[T10]],[[T10]],0x1f
2501 ; MIPS32: sll [[T4]],[[T4]],0x1f
2502 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
2503 ; MIPS32: xori [[T4]],[[T4]],0x1
2504 ; MIPS32: andi [[T4]],[[T4]],0xffff
2505 ; MIPS32: srl [[T5]],[[T5]],0x10
2506 ; MIPS32: sll [[T5]],[[T5]],0x10
2507 ; MIPS32: or [[T4]],[[T4]],[[T5]]
2508 ; MIPS32: srl [[T11:.*]],a1,0x10
2509 ; MIPS32: andi [[T11]],[[T11]],0x1
2510 ; MIPS32: srl [[T1]],[[T1]],0x10
2308 ; MIPS32: andi [[T1]],[[T1]],0x1 2511 ; MIPS32: andi [[T1]],[[T1]],0x1
2309 ; MIPS32: sll [[T0]],[[T0]],0x1f 2512 ; MIPS32: sll [[T11]],[[T11]],0x1f
2310 ; MIPS32: sll [[T1]],[[T1]],0x1f 2513 ; MIPS32: sll [[T1]],[[T1]],0x1f
2311 ; MIPS32: sltu [[T1]],[[T1]],[[T0]] 2514 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
2312 ; MIPS32: xori [[T1]],[[T1]],0x1 2515 ; MIPS32: xori [[T1]],[[T1]],0x1
2313 ; MIPS32: andi [[T1]],[[T1]],0xffff 2516 ; MIPS32: sll [[T1]],[[T1]],0x10
2314 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2517 ; MIPS32: sll [[T4]],[[T4]],0x10
2518 ; MIPS32: srl [[T4]],[[T4]],0x10
2519 ; MIPS32: or v1,[[T1]],[[T4]]
2520 ; MIPS32: move [[T10]],a2
2521 ; MIPS32: andi [[T10]],[[T10]],0xffff
2522 ; MIPS32: andi [[T10]],[[T10]],0x1
2523 ; MIPS32: move [[T11]],[[T2]]
2524 ; MIPS32: andi [[T11]],[[T11]],0xffff
2525 ; MIPS32: andi [[T11]],[[T11]],0x1
2526 ; MIPS32: sll [[T10]],[[T10]],0x1f
2527 ; MIPS32: sll [[T11]],[[T11]],0x1f
2528 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
2529 ; MIPS32: xori [[T11]],[[T11]],0x1
2530 ; MIPS32: andi [[T11]],[[T11]],0xffff
2531 ; MIPS32: srl [[T6]],[[T6]],0x10
2532 ; MIPS32: sll [[T6]],[[T6]],0x10
2533 ; MIPS32: or [[T11]],[[T11]],[[T6]]
2534 ; MIPS32: srl [[T12:.*]],a2,0x10
2535 ; MIPS32: andi [[T12]],[[T12]],0x1
2536 ; MIPS32: srl [[T2]],[[T2]],0x10
2537 ; MIPS32: andi [[T2]],[[T2]],0x1
2538 ; MIPS32: sll [[T12]],[[T12]],0x1f
2539 ; MIPS32: sll [[T2]],[[T2]],0x1f
2540 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
2541 ; MIPS32: xori [[T2]],[[T2]],0x1
2315 ; MIPS32: sll [[T2]],[[T2]],0x10 2542 ; MIPS32: sll [[T2]],[[T2]],0x10
2316 ; MIPS32: or [[T1]],[[T1]],[[T2]] 2543 ; MIPS32: sll [[T11]],[[T11]],0x10
2317 ; MIPS32: srl [[T3:.*]],a0,0x10 2544 ; MIPS32: srl [[T11]],[[T11]],0x10
2545 ; MIPS32: or [[T2]],[[T2]],[[T11]]
2546 ; MIPS32: move [[T10]],a3
2547 ; MIPS32: andi [[T10]],[[T10]],0xffff
2548 ; MIPS32: andi [[T10]],[[T10]],0x1
2549 ; MIPS32: move [[T11]],[[T3]]
2550 ; MIPS32: andi [[T11]],[[T11]],0xffff
2551 ; MIPS32: andi [[T11]],[[T11]],0x1
2552 ; MIPS32: sll [[T10]],[[T10]],0x1f
2553 ; MIPS32: sll [[T11]],[[T11]],0x1f
2554 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
2555 ; MIPS32: xori [[T11]],[[T11]],0x1
2556 ; MIPS32: andi [[T11]],[[T11]],0xffff
2557 ; MIPS32: srl [[T7]],[[T7]],0x10
2558 ; MIPS32: sll [[T7]],[[T7]],0x10
2559 ; MIPS32: or [[T11]],[[T11]],[[T7]]
2560 ; MIPS32: srl [[T13:.*]],a3,0x10
2561 ; MIPS32: andi [[T13]],[[T13]],0x1
2562 ; MIPS32: srl [[T3]],[[T3]],0x10
2318 ; MIPS32: andi [[T3]],[[T3]],0x1 2563 ; MIPS32: andi [[T3]],[[T3]],0x1
2319 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2564 ; MIPS32: sll [[T13]],[[T13]],0x1f
2320 ; MIPS32: andi [[T4]],[[T4]],0x1
2321 ; MIPS32: sll [[T3]],[[T3]],0x1f 2565 ; MIPS32: sll [[T3]],[[T3]],0x1f
2322 ; MIPS32: sll [[T4]],[[T4]],0x1f 2566 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
2323 ; MIPS32: sltu [[T4]],[[T4]],[[T3]] 2567 ; MIPS32: xori [[T3]],[[T3]],0x1
2324 ; MIPS32: xori [[T4]],[[T4]],0x1 2568 ; MIPS32: sll [[T3]],[[T3]],0x10
2325 ; MIPS32: sll [[T4]],[[T4]],0x10 2569 ; MIPS32: sll [[T11]],[[T11]],0x10
2326 ; MIPS32: sll [[T1]],[[T1]],0x10 2570 ; MIPS32: srl [[T11]],[[T11]],0x10
2327 ; MIPS32: srl [[T1]],[[T1]],0x10 2571 ; MIPS32: or [[T3]],[[T3]],[[T11]]
2328 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 2572 ; MIPS32: move a0,[[T2]]
2329 ; MIPS32: andi [[T0:.*]],a1,0xffff 2573 ; MIPS32: move a1,[[T3]]
2330 ; MIPS32: andi [[T0]],[[T0]],0x1
2331 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2332 ; MIPS32: andi [[T1]],[[T1]],0x1
2333 ; MIPS32: sll [[T0]],[[T0]],0x1f
2334 ; MIPS32: sll [[T1]],[[T1]],0x1f
2335 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2336 ; MIPS32: xori [[T1]],[[T1]],0x1
2337 ; MIPS32: andi [[T1]],[[T1]],0xffff
2338 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2339 ; MIPS32: sll [[T2]],[[T2]],0x10
2340 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2341 ; MIPS32: srl [[T3:.*]],a1,0x10
2342 ; MIPS32: andi [[T3]],[[T3]],0x1
2343 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2344 ; MIPS32: andi [[T4]],[[T4]],0x1
2345 ; MIPS32: sll [[T3]],[[T3]],0x1f
2346 ; MIPS32: sll [[T4]],[[T4]],0x1f
2347 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2348 ; MIPS32: xori [[T4]],[[T4]],0x1
2349 ; MIPS32: sll [[T4]],[[T4]],0x10
2350 ; MIPS32: sll [[T1]],[[T1]],0x10
2351 ; MIPS32: srl [[T1]],[[T1]],0x10
2352 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
2353 ; MIPS32: andi [[T0:.*]],a2,0xffff
2354 ; MIPS32: andi [[T0]],[[T0]],0x1
2355 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2356 ; MIPS32: andi [[T1]],[[T1]],0x1
2357 ; MIPS32: sll [[T0]],[[T0]],0x1f
2358 ; MIPS32: sll [[T1]],[[T1]],0x1f
2359 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2360 ; MIPS32: xori [[T1]],[[T1]],0x1
2361 ; MIPS32: andi [[T1]],[[T1]],0xffff
2362 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2363 ; MIPS32: sll [[T2]],[[T2]],0x10
2364 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2365 ; MIPS32: srl [[T3:.*]],a2,0x10
2366 ; MIPS32: andi [[T3]],[[T3]],0x1
2367 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2368 ; MIPS32: andi [[T4]],[[T4]],0x1
2369 ; MIPS32: sll [[T3]],[[T3]],0x1f
2370 ; MIPS32: sll [[T4]],[[T4]],0x1f
2371 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2372 ; MIPS32: xori [[T4]],[[T4]],0x1
2373 ; MIPS32: sll [[T4]],[[T4]],0x10
2374 ; MIPS32: sll [[T1]],[[T1]],0x10
2375 ; MIPS32: srl [[T1]],[[T1]],0x10
2376 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
2377 ; MIPS32: andi [[T0:.*]],a3,0xffff
2378 ; MIPS32: andi [[T0]],[[T0]],0x1
2379 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2380 ; MIPS32: andi [[T1]],[[T1]],0x1
2381 ; MIPS32: sll [[T0]],[[T0]],0x1f
2382 ; MIPS32: sll [[T1]],[[T1]],0x1f
2383 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2384 ; MIPS32: xori [[T1]],[[T1]],0x1
2385 ; MIPS32: andi [[T1]],[[T1]],0xffff
2386 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2387 ; MIPS32: sll [[T2]],[[T2]],0x10
2388 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2389 ; MIPS32: srl [[T3:.*]],a3,0x10
2390 ; MIPS32: andi [[T3]],[[T3]],0x1
2391 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2392 ; MIPS32: andi [[T4]],[[T4]],0x1
2393 ; MIPS32: sll [[T3]],[[T3]],0x1f
2394 ; MIPS32: sll [[T4]],[[T4]],0x1f
2395 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2396 ; MIPS32: xori [[T4]],[[T4]],0x1
2397 ; MIPS32: sll [[T4]],[[T4]],0x10
2398 ; MIPS32: sll [[T1]],[[T1]],0x10
2399 ; MIPS32: srl [[T1]],[[T1]],0x10
2400 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
2401 } 2574 }
2402 2575
2403 define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) { 2576 define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) {
2404 entry: 2577 entry:
2405 %res = icmp ult <8 x i1> %a, %b 2578 %res = icmp ult <8 x i1> %a, %b
2406 ret <8 x i1> %res 2579 ret <8 x i1> %res
2407 ; CHECK-LABEL: test_icmp_v8i1_ult 2580 ; CHECK-LABEL: test_icmp_v8i1_ult
2408 ; CHECK: pxor 2581 ; CHECK: pxor
2409 ; CHECK: pcmpgtw 2582 ; CHECK: pcmpgtw
2410 2583
2411 ; MIPS32-LABEL: test_icmp_v8i1_ult 2584 ; MIPS32-LABEL: test_icmp_v8i1_ult
2412 ; MIPS32: lw [[BV_E0:.*]], 2585 ; MIPS32: lw [[T0:.*]],
2413 ; MIPS32: lw [[BV_E1:.*]], 2586 ; MIPS32: lw [[T1:.*]],
2414 ; MIPS32: lw [[BV_E2:.*]], 2587 ; MIPS32: lw [[T2:.*]],
2415 ; MIPS32: lw [[BV_E3:.*]], 2588 ; MIPS32: lw [[T3:.*]],
2416 ; MIPS32: move [[TV_E0:.*]],zero 2589 ; MIPS32: move [[T4:.*]],zero
2417 ; MIPS32: move [[TV_E1:.*]],zero 2590 ; MIPS32: move [[T5:.*]],zero
2418 ; MIPS32: move [[TV_E2:.*]],zero 2591 ; MIPS32: move [[T6:.*]],zero
2419 ; MIPS32: move [[TV_E3:.*]],zero 2592 ; MIPS32: move [[T7:.*]],zero
2420 ; MIPS32: andi [[T0:.*]],a0,0xffff 2593 ; MIPS32: move [[T8:.*]],a0
2594 ; MIPS32: andi [[T8]],[[T8]],0xffff
2595 ; MIPS32: andi [[T8]],[[T8]],0x1
2596 ; MIPS32: move [[T9:.*]],[[T0]]
2597 ; MIPS32: andi [[T9]],[[T9]],0xffff
2598 ; MIPS32: andi [[T9]],[[T9]],0x1
2599 ; MIPS32: sll [[T8]],[[T8]],0x1f
2600 ; MIPS32: sll [[T9]],[[T9]],0x1f
2601 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
2602 ; MIPS32: andi [[T8]],[[T8]],0xffff
2603 ; MIPS32: srl [[T4]],[[T4]],0x10
2604 ; MIPS32: sll [[T4]],[[T4]],0x10
2605 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2606 ; MIPS32: srl [[T10:.*]],a0,0x10
2607 ; MIPS32: andi [[T10]],[[T10]],0x1
2608 ; MIPS32: srl [[T0]],[[T0]],0x10
2421 ; MIPS32: andi [[T0]],[[T0]],0x1 2609 ; MIPS32: andi [[T0]],[[T0]],0x1
2422 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff 2610 ; MIPS32: sll [[T10]],[[T10]],0x1f
2611 ; MIPS32: sll [[T0]],[[T0]],0x1f
2612 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
2613 ; MIPS32: sll [[T10]],[[T10]],0x10
2614 ; MIPS32: sll [[T8]],[[T8]],0x10
2615 ; MIPS32: srl [[T8]],[[T8]],0x10
2616 ; MIPS32: or [[T10]],[[T10]],[[T8]]
2617 ; MIPS32: move [[T0]],a1
2618 ; MIPS32: andi [[T0]],[[T0]],0xffff
2619 ; MIPS32: andi [[T0]],[[T0]],0x1
2620 ; MIPS32: move [[T4]],[[T1]]
2621 ; MIPS32: andi [[T4]],[[T4]],0xffff
2622 ; MIPS32: andi [[T4]],[[T4]],0x1
2623 ; MIPS32: sll [[T0]],[[T0]],0x1f
2624 ; MIPS32: sll [[T4]],[[T4]],0x1f
2625 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
2626 ; MIPS32: andi [[T0]],[[T0]],0xffff
2627 ; MIPS32: srl [[T5]],[[T5]],0x10
2628 ; MIPS32: sll [[T5]],[[T5]],0x10
2629 ; MIPS32: or [[T0]],[[T0]],[[T5]]
2630 ; MIPS32: srl [[T11:.*]],a1,0x10
2631 ; MIPS32: andi [[T11]],[[T11]],0x1
2632 ; MIPS32: srl [[T1]],[[T1]],0x10
2633 ; MIPS32: andi [[T1]],[[T1]],0x1
2634 ; MIPS32: sll [[T11]],[[T11]],0x1f
2635 ; MIPS32: sll [[T1]],[[T1]],0x1f
2636 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
2637 ; MIPS32: sll [[T11]],[[T11]],0x10
2638 ; MIPS32: sll [[T0]],[[T0]],0x10
2639 ; MIPS32: srl [[T0]],[[T0]],0x10
2640 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2641 ; MIPS32: move [[T0]],a2
2642 ; MIPS32: andi [[T0]],[[T0]],0xffff
2643 ; MIPS32: andi [[T0]],[[T0]],0x1
2644 ; MIPS32: move [[T1]],[[T2]]
2645 ; MIPS32: andi [[T1]],[[T1]],0xffff
2423 ; MIPS32: andi [[T1]],[[T1]],0x1 2646 ; MIPS32: andi [[T1]],[[T1]],0x1
2424 ; MIPS32: sll [[T0]],[[T0]],0x1f 2647 ; MIPS32: sll [[T0]],[[T0]],0x1f
2425 ; MIPS32: sll [[T1]],[[T1]],0x1f 2648 ; MIPS32: sll [[T1]],[[T1]],0x1f
2426 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2649 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2427 ; MIPS32: andi [[T0]],[[T0]],0xffff 2650 ; MIPS32: andi [[T0]],[[T0]],0xffff
2428 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 2651 ; MIPS32: srl [[T6]],[[T6]],0x10
2429 ; MIPS32: sll [[T2]],[[T2]],0x10 2652 ; MIPS32: sll [[T6]],[[T6]],0x10
2430 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2653 ; MIPS32: or [[T0]],[[T0]],[[T6]]
2431 ; MIPS32: srl [[T3:.*]],a0,0x10 2654 ; MIPS32: srl [[T12:.*]],a2,0x10
2432 ; MIPS32: andi [[T3]],[[T3]],0x1 2655 ; MIPS32: andi [[T12]],[[T12]],0x1
2433 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 2656 ; MIPS32: srl [[T2]],[[T2]],0x10
2434 ; MIPS32: andi [[T4]],[[T4]],0x1 2657 ; MIPS32: andi [[T2]],[[T2]],0x1
2435 ; MIPS32: sll [[T3]],[[T3]],0x1f 2658 ; MIPS32: sll [[T12]],[[T12]],0x1f
2436 ; MIPS32: sll [[T4]],[[T4]],0x1f 2659 ; MIPS32: sll [[T2]],[[T2]],0x1f
2437 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 2660 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
2438 ; MIPS32: sll [[T3]],[[T3]],0x10 2661 ; MIPS32: sll [[T12]],[[T12]],0x10
2439 ; MIPS32: sll [[T0]],[[T0]],0x10 2662 ; MIPS32: sll [[T0]],[[T0]],0x10
2440 ; MIPS32: srl [[T0]],[[T0]],0x10 2663 ; MIPS32: srl [[T0]],[[T0]],0x10
2441 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 2664 ; MIPS32: or [[T12]],[[T12]],[[T0]]
2442 ; MIPS32: andi [[T0:.*]],a1,0xffff 2665 ; MIPS32: move [[T0]],a3
2666 ; MIPS32: andi [[T0]],[[T0]],0xffff
2443 ; MIPS32: andi [[T0]],[[T0]],0x1 2667 ; MIPS32: andi [[T0]],[[T0]],0x1
2444 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff 2668 ; MIPS32: move [[T1]],[[T3]]
2669 ; MIPS32: andi [[T1]],[[T1]],0xffff
2445 ; MIPS32: andi [[T1]],[[T1]],0x1 2670 ; MIPS32: andi [[T1]],[[T1]],0x1
2446 ; MIPS32: sll [[T0]],[[T0]],0x1f 2671 ; MIPS32: sll [[T0]],[[T0]],0x1f
2447 ; MIPS32: sll [[T1]],[[T1]],0x1f 2672 ; MIPS32: sll [[T1]],[[T1]],0x1f
2448 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2673 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2449 ; MIPS32: andi [[T0]],[[T0]],0xffff 2674 ; MIPS32: andi [[T0]],[[T0]],0xffff
2450 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 2675 ; MIPS32: srl [[T7]],[[T7]],0x10
2451 ; MIPS32: sll [[T2]],[[T2]],0x10 2676 ; MIPS32: sll [[T7]],[[T7]],0x10
2452 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2677 ; MIPS32: or [[T0]],[[T0]],[[T7]]
2453 ; MIPS32: srl [[T3:.*]],a1,0x10 2678 ; MIPS32: srl [[T13:.*]],a3,0x10
2679 ; MIPS32: andi [[T13]],[[T13]],0x1
2680 ; MIPS32: srl [[T3]],[[T3]],0x10
2454 ; MIPS32: andi [[T3]],[[T3]],0x1 2681 ; MIPS32: andi [[T3]],[[T3]],0x1
2455 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 2682 ; MIPS32: sll [[T13]],[[T13]],0x1f
2456 ; MIPS32: andi [[T4]],[[T4]],0x1
2457 ; MIPS32: sll [[T3]],[[T3]],0x1f 2683 ; MIPS32: sll [[T3]],[[T3]],0x1f
2458 ; MIPS32: sll [[T4]],[[T4]],0x1f 2684 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
2459 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 2685 ; MIPS32: sll [[T13]],[[T13]],0x10
2460 ; MIPS32: sll [[T3]],[[T3]],0x10
2461 ; MIPS32: sll [[T0]],[[T0]],0x10 2686 ; MIPS32: sll [[T0]],[[T0]],0x10
2462 ; MIPS32: srl [[T0]],[[T0]],0x10 2687 ; MIPS32: srl [[T0]],[[T0]],0x10
2463 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] 2688 ; MIPS32: or [[T13]],[[T13]],[[T0]]
2464 ; MIPS32: andi [[T0:.*]],a2,0xffff 2689 ; MIPS32: move v0,[[T10]]
2465 ; MIPS32: andi [[T0]],[[T0]],0x1 2690 ; MIPS32: move v1,[[T11]]
2466 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff 2691 ; MIPS32: move a0,[[T12]]
2467 ; MIPS32: andi [[T1]],[[T1]],0x1 2692 ; MIPS32: move a1,[[T13]]
2468 ; MIPS32: sll [[T0]],[[T0]],0x1f
2469 ; MIPS32: sll [[T1]],[[T1]],0x1f
2470 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2471 ; MIPS32: andi [[T0]],[[T0]],0xffff
2472 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2473 ; MIPS32: sll [[T2]],[[T2]],0x10
2474 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2475 ; MIPS32: srl [[T3:.*]],a2,0x10
2476 ; MIPS32: andi [[T3]],[[T3]],0x1
2477 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2478 ; MIPS32: andi [[T4]],[[T4]],0x1
2479 ; MIPS32: sll [[T3]],[[T3]],0x1f
2480 ; MIPS32: sll [[T4]],[[T4]],0x1f
2481 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2482 ; MIPS32: sll [[T3]],[[T3]],0x10
2483 ; MIPS32: sll [[T0]],[[T0]],0x10
2484 ; MIPS32: srl [[T0]],[[T0]],0x10
2485 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2486 ; MIPS32: andi [[T0:.*]],a3,0xffff
2487 ; MIPS32: andi [[T0]],[[T0]],0x1
2488 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2489 ; MIPS32: andi [[T1]],[[T1]],0x1
2490 ; MIPS32: sll [[T0]],[[T0]],0x1f
2491 ; MIPS32: sll [[T1]],[[T1]],0x1f
2492 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2493 ; MIPS32: andi [[T0]],[[T0]],0xffff
2494 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2495 ; MIPS32: sll [[T2]],[[T2]],0x10
2496 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2497 ; MIPS32: srl [[T3:.*]],a3,0x10
2498 ; MIPS32: andi [[T3]],[[T3]],0x1
2499 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2500 ; MIPS32: andi [[T4]],[[T4]],0x1
2501 ; MIPS32: sll [[T3]],[[T3]],0x1f
2502 ; MIPS32: sll [[T4]],[[T4]],0x1f
2503 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2504 ; MIPS32: sll [[T3]],[[T3]],0x10
2505 ; MIPS32: sll [[T0]],[[T0]],0x10
2506 ; MIPS32: srl [[T0]],[[T0]],0x10
2507 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
2508 } 2693 }
2509 2694
2510 define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) { 2695 define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) {
2511 entry: 2696 entry:
2512 %res = icmp eq <16 x i8> %a, %b 2697 %res = icmp eq <16 x i8> %a, %b
2513 ret <16 x i1> %res 2698 ret <16 x i1> %res
2514 ; CHECK-LABEL: test_icmp_v16i8_eq 2699 ; CHECK-LABEL: test_icmp_v16i8_eq
2515 ; CHECK: pcmpeqb 2700 ; CHECK: pcmpeqb
2516 2701
2517 ; MIPS32-LABEL: test_icmp_v16i8_eq 2702 ; MIPS32-LABEL: test_icmp_v16i8_eq
2518 ; MIPS32: lw [[BV_E0:.*]], 2703 ; MIPS32: lw [[T0:.*]],
2519 ; MIPS32: lw [[BV_E1:.*]], 2704 ; MIPS32: lw [[T1:.*]],
2520 ; MIPS32: lw [[BV_E2:.*]], 2705 ; MIPS32: lw [[T2:.*]],
2521 ; MIPS32: lw [[BV_E3:.*]], 2706 ; MIPS32: lw [[T3:.*]],
2522 ; MIPS32: move [[TV_E0:.*]],zero 2707 ; MIPS32: move [[T4:.*]],zero
2523 ; MIPS32: move [[TV_E1:.*]],zero 2708 ; MIPS32: move [[T5:.*]],zero
2524 ; MIPS32: move [[TV_E2:.*]],zero 2709 ; MIPS32: move [[T6:.*]],zero
2525 ; MIPS32: move [[TV_E3:.*]],zero 2710 ; MIPS32: move [[T7:.*]],zero
2526 ; MIPS32: andi [[T0:.*]],a0,0xff 2711 ; MIPS32: move [[T8:.*]],a0
2527 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 2712 ; MIPS32: andi [[T8]],[[T8]],0xff
2528 ; MIPS32: sll [[T0]],[[T0]],0x18 2713 ; MIPS32: move [[T9:.*]],[[T0]]
2529 ; MIPS32: sll [[T1]],[[T1]],0x18 2714 ; MIPS32: andi [[T9]],[[T9]],0xff
2530 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 2715 ; MIPS32: sll [[T8]],[[T8]],0x18
2531 ; MIPS32: sltiu [[T0]],[[T0]],1 2716 ; MIPS32: sll [[T9]],[[T9]],0x18
2532 ; MIPS32: andi [[T0]],[[T0]],0xff 2717 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
2533 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 2718 ; MIPS32: sltiu [[T8]],[[T8]],1
2534 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 2719 ; MIPS32: andi [[T8]],[[T8]],0xff
2535 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2720 ; MIPS32: srl [[T4]],[[T4]],0x8
2536 ; MIPS32: srl [[T2]],a0,0x8 2721 ; MIPS32: sll [[T4]],[[T4]],0x8
2537 ; MIPS32: andi [[T2]],[[T2]],0xff 2722 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2538 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 2723 ; MIPS32: move [[T4]],a0
2539 ; MIPS32: andi [[T1]],[[T1]],0xff 2724 ; MIPS32: srl [[T4]],[[T4]],0x8
2540 ; MIPS32: sll [[T2]],[[T2]],0x18 2725 ; MIPS32: andi [[T4]],[[T4]],0xff
2541 ; MIPS32: sll [[T1]],[[T1]],0x18 2726 ; MIPS32: move [[T9]],[[T0]]
2542 ; MIPS32: xor [[T2]],[[T2]],[[T1]] 2727 ; MIPS32: srl [[T9]],[[T9]],0x8
2543 ; MIPS32: sltiu [[T2]],[[T2]],1 2728 ; MIPS32: andi [[T9]],[[T9]],0xff
2544 ; MIPS32: andi [[T2]],[[T2]],0xff 2729 ; MIPS32: sll [[T4]],[[T4]],0x18
2545 ; MIPS32: sll [[T2]],[[T2]],0x8 2730 ; MIPS32: sll [[T9]],[[T9]],0x18
2546 ; MIPS32: lui [[T1]],0xffff 2731 ; MIPS32: xor [[T4]],[[T4]],[[T9]]
2547 ; MIPS32: ori [[T1]],[[T1]],0xff
2548 ; MIPS32: and [[T0]],[[T0]],[[T1]]
2549 ; MIPS32: or [[T2]],[[T2]],[[T0]]
2550 ; MIPS32: srl [[T0]],a0,0x10
2551 ; MIPS32: andi [[T0]],[[T0]],0xff
2552 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
2553 ; MIPS32: andi [[T1]],[[T1]],0xff
2554 ; MIPS32: sll [[T0]],[[T0]],0x18
2555 ; MIPS32: sll [[T1]],[[T1]],0x18
2556 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2557 ; MIPS32: sltiu [[T0]],[[T0]],1
2558 ; MIPS32: andi [[T0]],[[T0]],0xff
2559 ; MIPS32: sll [[T0]],[[T0]],0x10
2560 ; MIPS32: lui [[T1]],0xff00
2561 ; MIPS32: ori [[T1]],[[T1]],0xffff
2562 ; MIPS32: and [[T2]],[[T2]],[[T1]]
2563 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2564 ; MIPS32: srl [[T3:.*]],a0,0x18
2565 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
2566 ; MIPS32: sll [[T3]],[[T3]],0x18
2567 ; MIPS32: sll [[T4]],[[T4]],0x18
2568 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
2569 ; MIPS32: sltiu [[T3]],[[T3]],1
2570 ; MIPS32: srl [[T3]],[[T3]],0x18
2571 ; MIPS32: sll [[T0]],[[T0]],0x8
2572 ; MIPS32: srl [[T0]],[[T0]],0x8
2573 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2574 ; MIPS32: andi [[T4]],a1,0xff
2575 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
2576 ; MIPS32: sll [[T4]],[[T4]],0x18
2577 ; MIPS32: sll [[T2]],[[T2]],0x18
2578 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2579 ; MIPS32: sltiu [[T4]],[[T4]],1 2732 ; MIPS32: sltiu [[T4]],[[T4]],1
2580 ; MIPS32: andi [[T4]],[[T4]],0xff 2733 ; MIPS32: andi [[T4]],[[T4]],0xff
2581 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 2734 ; MIPS32: sll [[T4]],[[T4]],0x8
2582 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 2735 ; MIPS32: lui [[T9]],0xffff
2583 ; MIPS32: or [[T4]],[[T4]],[[T5]] 2736 ; MIPS32: ori [[T9]],[[T9]],0xff
2584 ; MIPS32: srl [[T2]],a1,0x8 2737 ; MIPS32: and [[T8]],[[T8]],[[T9]]
2585 ; MIPS32: andi [[T2]],[[T2]],0xff 2738 ; MIPS32: or [[T4]],[[T4]],[[T8]]
2586 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 2739 ; MIPS32: move [[T8]],a0
2587 ; MIPS32: andi [[T5]],[[T5]],0xff 2740 ; MIPS32: srl [[T8]],[[T8]],0x10
2588 ; MIPS32: sll [[T2]],[[T2]],0x18 2741 ; MIPS32: andi [[T8]],[[T8]],0xff
2589 ; MIPS32: sll [[T5]],[[T5]],0x18 2742 ; MIPS32: move [[T9]],[[T0]]
2590 ; MIPS32: xor [[T2]],[[T2]],[[T5]] 2743 ; MIPS32: srl [[T9]],[[T9]],0x10
2591 ; MIPS32: sltiu [[T2]],[[T2]],1 2744 ; MIPS32: andi [[T9]],[[T9]],0xff
2592 ; MIPS32: andi [[T2]],[[T2]],0xff 2745 ; MIPS32: sll [[T8]],[[T8]],0x18
2593 ; MIPS32: sll [[T2]],[[T2]],0x8 2746 ; MIPS32: sll [[T9]],[[T9]],0x18
2594 ; MIPS32: lui [[T5]],0xffff 2747 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
2595 ; MIPS32: ori [[T5]],[[T5]],0xff 2748 ; MIPS32: sltiu [[T8]],[[T8]],1
2596 ; MIPS32: and [[T4]],[[T4]],[[T5]] 2749 ; MIPS32: andi [[T8]],[[T8]],0xff
2597 ; MIPS32: or [[T2]],[[T2]],[[T4]] 2750 ; MIPS32: sll [[T8]],[[T8]],0x10
2598 ; MIPS32: srl [[T4]],a1,0x10 2751 ; MIPS32: lui [[T9]],0xff00
2599 ; MIPS32: andi [[T4]],[[T4]],0xff 2752 ; MIPS32: ori [[T9]],[[T9]],0xffff
2600 ; MIPS32: srl [[T5]],[[BV_E1]],0x10 2753 ; MIPS32: and [[T4]],[[T4]],[[T9]]
2754 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2755 ; MIPS32: srl [[T10:.*]],a0,0x18
2756 ; MIPS32: srl [[T0]],[[T0]],0x18
2757 ; MIPS32: sll [[T10]],[[T10]],0x18
2758 ; MIPS32: sll [[T0]],[[T0]],0x18
2759 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
2760 ; MIPS32: sltiu [[T10]],[[T10]],1
2761 ; MIPS32: srl [[T10]],[[T10]],0x18
2762 ; MIPS32: sll [[T8]],[[T8]],0x8
2763 ; MIPS32: srl [[T8]],[[T8]],0x8
2764 ; MIPS32: or [[T10]],[[T10]],[[T8]]
2765 ; MIPS32: move [[T0]],a1
2766 ; MIPS32: andi [[T0]],[[T0]],0xff
2767 ; MIPS32: move [[T4]],[[T1]]
2768 ; MIPS32: andi [[T4]],[[T4]],0xff
2769 ; MIPS32: sll [[T0]],[[T0]],0x18
2770 ; MIPS32: sll [[T4]],[[T4]],0x18
2771 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
2772 ; MIPS32: sltiu [[T0]],[[T0]],1
2773 ; MIPS32: andi [[T0]],[[T0]],0xff
2774 ; MIPS32: srl [[T5]],[[T5]],0x8
2775 ; MIPS32: sll [[T5]],[[T5]],0x8
2776 ; MIPS32: or [[T0]],[[T0]],[[T5]]
2777 ; MIPS32: move [[T4]],a1
2778 ; MIPS32: srl [[T4]],[[T4]],0x8
2779 ; MIPS32: andi [[T4]],[[T4]],0xff
2780 ; MIPS32: move [[T5]],[[T1]]
2781 ; MIPS32: srl [[T5]],[[T5]],0x8
2601 ; MIPS32: andi [[T5]],[[T5]],0xff 2782 ; MIPS32: andi [[T5]],[[T5]],0xff
2602 ; MIPS32: sll [[T4]],[[T4]],0x18 2783 ; MIPS32: sll [[T4]],[[T4]],0x18
2603 ; MIPS32: sll [[T5]],[[T5]],0x18 2784 ; MIPS32: sll [[T5]],[[T5]],0x18
2604 ; MIPS32: xor [[T4]],[[T4]],[[T5]] 2785 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
2605 ; MIPS32: sltiu [[T4]],[[T4]],1 2786 ; MIPS32: sltiu [[T4]],[[T4]],1
2606 ; MIPS32: andi [[T4]],[[T4]],0xff 2787 ; MIPS32: andi [[T4]],[[T4]],0xff
2607 ; MIPS32: sll [[T4]],[[T4]],0x10 2788 ; MIPS32: sll [[T4]],[[T4]],0x8
2789 ; MIPS32: lui [[T5]],0xffff
2790 ; MIPS32: ori [[T5]],[[T5]],0xff
2791 ; MIPS32: and [[T0]],[[T0]],[[T5]]
2792 ; MIPS32: or [[T4]],[[T4]],[[T0]]
2793 ; MIPS32: move [[T0]],a1
2794 ; MIPS32: srl [[T0]],[[T0]],0x10
2795 ; MIPS32: andi [[T0]],[[T0]],0xff
2796 ; MIPS32: move [[T5]],[[T1]]
2797 ; MIPS32: srl [[T5]],[[T5]],0x10
2798 ; MIPS32: andi [[T5]],[[T5]],0xff
2799 ; MIPS32: sll [[T0]],[[T0]],0x18
2800 ; MIPS32: sll [[T5]],[[T5]],0x18
2801 ; MIPS32: xor [[T0]],[[T0]],[[T5]]
2802 ; MIPS32: sltiu [[T0]],[[T0]],1
2803 ; MIPS32: andi [[T0]],[[T0]],0xff
2804 ; MIPS32: sll [[T0]],[[T0]],0x10
2608 ; MIPS32: lui [[T5]],0xff00 2805 ; MIPS32: lui [[T5]],0xff00
2609 ; MIPS32: ori [[T5]],[[T5]],0xffff 2806 ; MIPS32: ori [[T5]],[[T5]],0xffff
2610 ; MIPS32: and [[T2]],[[T2]],[[T5]] 2807 ; MIPS32: and [[T4]],[[T4]],[[T5]]
2611 ; MIPS32: or [[T4]],[[T4]],[[T2]] 2808 ; MIPS32: or [[T0]],[[T0]],[[T4]]
2612 ; MIPS32: srl [[T6:.*]],a1,0x18 2809 ; MIPS32: srl [[T11:.*]],a1,0x18
2613 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 2810 ; MIPS32: srl [[T1]],[[T1]],0x18
2614 ; MIPS32: sll [[T6]],[[T6]],0x18 2811 ; MIPS32: sll [[T11]],[[T11]],0x18
2615 ; MIPS32: sll [[T7]],[[T7]],0x18 2812 ; MIPS32: sll [[T1]],[[T1]],0x18
2616 ; MIPS32: xor [[T6]],[[T6]],[[T7]] 2813 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
2617 ; MIPS32: sltiu [[T6]],[[T6]],1 2814 ; MIPS32: sltiu [[T11]],[[T11]],1
2618 ; MIPS32: srl [[T6]],[[T6]],0x18 2815 ; MIPS32: srl [[T11]],[[T11]],0x18
2619 ; MIPS32: sll [[T4]],[[T4]],0x8 2816 ; MIPS32: sll [[T0]],[[T0]],0x8
2620 ; MIPS32: srl [[T4]],[[T4]],0x8 2817 ; MIPS32: srl [[T0]],[[T0]],0x8
2621 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] 2818 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2622 ; MIPS32: andi [[T4]],a2,0xff 2819 ; MIPS32: move [[T0]],a2
2623 ; MIPS32: andi [[T7]],[[BV_E2]],0xff 2820 ; MIPS32: andi [[T0]],[[T0]],0xff
2624 ; MIPS32: sll [[T4]],[[T4]],0x18 2821 ; MIPS32: move [[T1]],[[T2]]
2625 ; MIPS32: sll [[T7]],[[T7]],0x18 2822 ; MIPS32: andi [[T1]],[[T1]],0xff
2626 ; MIPS32: xor [[T4]],[[T4]],[[T7]] 2823 ; MIPS32: sll [[T0]],[[T0]],0x18
2627 ; MIPS32: sltiu [[T4]],[[T4]],1 2824 ; MIPS32: sll [[T1]],[[T1]],0x18
2628 ; MIPS32: andi [[T4]],[[T4]],0xff 2825 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2629 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 2826 ; MIPS32: sltiu [[T0]],[[T0]],1
2630 ; MIPS32: sll [[T8]],[[TV_E2]],0x8 2827 ; MIPS32: andi [[T0]],[[T0]],0xff
2631 ; MIPS32: or [[T4]],[[T4]],[[T8]] 2828 ; MIPS32: srl [[T6]],[[T6]],0x8
2632 ; MIPS32: srl [[T7]],a2,0x8 2829 ; MIPS32: sll [[T6]],[[T6]],0x8
2633 ; MIPS32: andi [[T7]],[[T7]],0xff 2830 ; MIPS32: or [[T0]],[[T0]],[[T6]]
2634 ; MIPS32: srl [[T2]],[[BV_E2]],0x8 2831 ; MIPS32: move [[T1]],a2
2832 ; MIPS32: srl [[T1]],[[T1]],0x8
2833 ; MIPS32: andi [[T1]],[[T1]],0xff
2834 ; MIPS32: move [[T4]],[[T2]]
2835 ; MIPS32: srl [[T4]],[[T4]],0x8
2836 ; MIPS32: andi [[T4]],[[T4]],0xff
2837 ; MIPS32: sll [[T1]],[[T1]],0x18
2838 ; MIPS32: sll [[T4]],[[T4]],0x18
2839 ; MIPS32: xor [[T1]],[[T1]],[[T4]]
2840 ; MIPS32: sltiu [[T1]],[[T1]],1
2841 ; MIPS32: andi [[T1]],[[T1]],0xff
2842 ; MIPS32: sll [[T1]],[[T1]],0x8
2843 ; MIPS32: lui [[T4]],0xffff
2844 ; MIPS32: ori [[T4]],[[T4]],0xff
2845 ; MIPS32: and [[T0]],[[T0]],[[T4]]
2846 ; MIPS32: or [[T1]],[[T1]],[[T0]]
2847 ; MIPS32: move [[T0]],a2
2848 ; MIPS32: srl [[T0]],[[T0]],0x10
2849 ; MIPS32: andi [[T0]],[[T0]],0xff
2850 ; MIPS32: move [[T4]],[[T2]]
2851 ; MIPS32: srl [[T4]],[[T4]],0x10
2852 ; MIPS32: andi [[T4]],[[T4]],0xff
2853 ; MIPS32: sll [[T0]],[[T0]],0x18
2854 ; MIPS32: sll [[T4]],[[T4]],0x18
2855 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
2856 ; MIPS32: sltiu [[T0]],[[T0]],1
2857 ; MIPS32: andi [[T0]],[[T0]],0xff
2858 ; MIPS32: sll [[T0]],[[T0]],0x10
2859 ; MIPS32: lui [[T4]],0xff00
2860 ; MIPS32: ori [[T4]],[[T4]],0xffff
2861 ; MIPS32: and [[T1]],[[T1]],[[T4]]
2862 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2863 ; MIPS32: srl [[T12:.*]],a2,0x18
2864 ; MIPS32: srl [[T2]],[[T2]],0x18
2865 ; MIPS32: sll [[T12]],[[T12]],0x18
2866 ; MIPS32: sll [[T2]],[[T2]],0x18
2867 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
2868 ; MIPS32: sltiu [[T12]],[[T12]],1
2869 ; MIPS32: srl [[T12]],[[T12]],0x18
2870 ; MIPS32: sll [[T0]],[[T0]],0x8
2871 ; MIPS32: srl [[T0]],[[T0]],0x8
2872 ; MIPS32: or [[T12]],[[T12]],[[T0]]
2873 ; MIPS32: move [[T0]],a3
2874 ; MIPS32: andi [[T0]],[[T0]],0xff
2875 ; MIPS32: move [[T1]],[[T3]]
2876 ; MIPS32: andi [[T1]],[[T1]],0xff
2877 ; MIPS32: sll [[T0]],[[T0]],0x18
2878 ; MIPS32: sll [[T1]],[[T1]],0x18
2879 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2880 ; MIPS32: sltiu [[T0]],[[T0]],1
2881 ; MIPS32: andi [[T0]],[[T0]],0xff
2882 ; MIPS32: srl [[T7]],[[T7]],0x8
2883 ; MIPS32: sll [[T7]],[[T7]],0x8
2884 ; MIPS32: or [[T0]],[[T0]],[[T7]]
2885 ; MIPS32: move [[T1]],a3
2886 ; MIPS32: srl [[T1]],[[T1]],0x8
2887 ; MIPS32: andi [[T1]],[[T1]],0xff
2888 ; MIPS32: move [[T2]],[[T3]]
2889 ; MIPS32: srl [[T2]],[[T2]],0x8
2635 ; MIPS32: andi [[T2]],[[T2]],0xff 2890 ; MIPS32: andi [[T2]],[[T2]],0xff
2636 ; MIPS32: sll [[T7]],[[T7]],0x18 2891 ; MIPS32: sll [[T1]],[[T1]],0x18
2637 ; MIPS32: sll [[T2]],[[T2]],0x18 2892 ; MIPS32: sll [[T2]],[[T2]],0x18
2638 ; MIPS32: xor [[T7]],[[T7]],[[T2]] 2893 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
2639 ; MIPS32: sltiu [[T7]],[[T7]],1 2894 ; MIPS32: sltiu [[T1]],[[T1]],1
2640 ; MIPS32: andi [[T7]],[[T7]],0xff 2895 ; MIPS32: andi [[T1]],[[T1]],0xff
2641 ; MIPS32: sll [[T7]],[[T7]],0x8 2896 ; MIPS32: sll [[T1]],[[T1]],0x8
2642 ; MIPS32: lui [[T2]],0xffff 2897 ; MIPS32: lui [[T2]],0xffff
2643 ; MIPS32: ori [[T2]],[[T2]],0xff 2898 ; MIPS32: ori [[T2]],[[T2]],0xff
2644 ; MIPS32: and [[T4]],[[T4]],[[T2]] 2899 ; MIPS32: and [[T0]],[[T0]],[[T2]]
2645 ; MIPS32: or [[T7]],[[T7]],[[T4]] 2900 ; MIPS32: or [[T1]],[[T1]],[[T0]]
2646 ; MIPS32: srl [[T4]],a2,0x10 2901 ; MIPS32: move [[T0]],a3
2647 ; MIPS32: andi [[T4]],[[T4]],0xff 2902 ; MIPS32: srl [[T0]],[[T0]],0x10
2648 ; MIPS32: srl [[T2]],[[BV_E2]],0x10 2903 ; MIPS32: andi [[T0]],[[T0]],0xff
2904 ; MIPS32: move [[T2]],[[T3]]
2905 ; MIPS32: srl [[T2]],[[T2]],0x10
2649 ; MIPS32: andi [[T2]],[[T2]],0xff 2906 ; MIPS32: andi [[T2]],[[T2]],0xff
2650 ; MIPS32: sll [[T4]],[[T4]],0x18 2907 ; MIPS32: sll [[T0]],[[T0]],0x18
2651 ; MIPS32: sll [[T2]],[[T2]],0x18 2908 ; MIPS32: sll [[T2]],[[T2]],0x18
2652 ; MIPS32: xor [[T4]],[[T4]],[[T2]] 2909 ; MIPS32: xor [[T0]],[[T0]],[[T2]]
2653 ; MIPS32: sltiu [[T4]],[[T4]],1 2910 ; MIPS32: sltiu [[T0]],[[T0]],1
2654 ; MIPS32: andi [[T4]],[[T4]],0xff 2911 ; MIPS32: andi [[T0]],[[T0]],0xff
2655 ; MIPS32: sll [[T4]],[[T4]],0x10 2912 ; MIPS32: sll [[T0]],[[T0]],0x10
2656 ; MIPS32: lui [[T2]],0xff00 2913 ; MIPS32: lui [[T2]],0xff00
2657 ; MIPS32: ori [[T2]],[[T2]],0xffff 2914 ; MIPS32: ori [[T2]],[[T2]],0xffff
2658 ; MIPS32: and [[T7]],[[T7]],[[T2]] 2915 ; MIPS32: and [[T1]],[[T1]],[[T2]]
2659 ; MIPS32: or [[T4]],[[T4]],[[T7]] 2916 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2660 ; MIPS32: srl [[T9:.*]],a2,0x18 2917 ; MIPS32: srl [[T13:.*]],a3,0x18
2661 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 2918 ; MIPS32: srl [[T3]],[[T3]],0x18
2662 ; MIPS32: sll [[T9]],[[T9]],0x18
2663 ; MIPS32: sll [[T10]],[[T10]],0x18
2664 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
2665 ; MIPS32: sltiu [[T9]],[[T9]],1
2666 ; MIPS32: srl [[T9]],[[T9]],0x18
2667 ; MIPS32: sll [[T4]],[[T4]],0x8
2668 ; MIPS32: srl [[T4]],[[T4]],0x8
2669 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
2670 ; MIPS32: andi [[T4]],a3,0xff
2671 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
2672 ; MIPS32: sll [[T4]],[[T4]],0x18
2673 ; MIPS32: sll [[T7]],[[T7]],0x18
2674 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2675 ; MIPS32: sltiu [[T4]],[[T4]],1
2676 ; MIPS32: andi [[T4]],[[T4]],0xff
2677 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
2678 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
2679 ; MIPS32: or [[T4]],[[T4]],[[T11]]
2680 ; MIPS32: srl [[T7]],a3,0x8
2681 ; MIPS32: andi [[T7]],[[T7]],0xff
2682 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
2683 ; MIPS32: andi [[T10]],[[T10]],0xff
2684 ; MIPS32: sll [[T7]],[[T7]],0x18
2685 ; MIPS32: sll [[T10]],[[T10]],0x18
2686 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
2687 ; MIPS32: sltiu [[T7]],[[T7]],1
2688 ; MIPS32: andi [[T7]],[[T7]],0xff
2689 ; MIPS32: sll [[T7]],[[T7]],0x8
2690 ; MIPS32: lui [[T10]],0xffff
2691 ; MIPS32: ori [[T10]],[[T10]],0xff
2692 ; MIPS32: and [[T4]],[[T4]],[[T10]]
2693 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2694 ; MIPS32: srl [[T4]],a3,0x10
2695 ; MIPS32: andi [[T4]],[[T4]],0xff
2696 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
2697 ; MIPS32: andi [[T10]],[[T10]],0xff
2698 ; MIPS32: sll [[T4]],[[T4]],0x18
2699 ; MIPS32: sll [[T10]],[[T10]],0x18
2700 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
2701 ; MIPS32: sltiu [[T4]],[[T4]],1
2702 ; MIPS32: andi [[T4]],[[T4]],0xff
2703 ; MIPS32: sll [[T4]],[[T4]],0x10
2704 ; MIPS32: lui [[T10]],0xff00
2705 ; MIPS32: ori [[T10]],[[T10]],0xffff
2706 ; MIPS32: and [[T7]],[[T7]],[[T10]]
2707 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2708 ; MIPS32: srl [[T12:.*]],a3,0x18
2709 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
2710 ; MIPS32: sll [[T12]],[[T12]],0x18
2711 ; MIPS32: sll [[T13]],[[T13]],0x18 2919 ; MIPS32: sll [[T13]],[[T13]],0x18
2712 ; MIPS32: xor [[T12]],[[T12]],[[T13]] 2920 ; MIPS32: sll [[T3]],[[T3]],0x18
2713 ; MIPS32: sltiu [[T12]],[[T12]],1 2921 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
2714 ; MIPS32: srl [[T12]],[[T12]],0x18 2922 ; MIPS32: sltiu [[T13]],[[T13]],1
2715 ; MIPS32: sll [[T4]],[[T4]],0x8 2923 ; MIPS32: srl [[T13]],[[T13]],0x18
2716 ; MIPS32: srl [[T4]],[[T4]],0x8 2924 ; MIPS32: sll [[T0]],[[T0]],0x8
2717 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 2925 ; MIPS32: srl [[T0]],[[T0]],0x8
2926 ; MIPS32: or [[T13]],[[T13]],[[T0]]
2927 ; MIPS32: move v0,[[T10]]
2928 ; MIPS32: move v1,[[T11]]
2929 ; MIPS32: move a0,[[T12]]
2930 ; MIPS32: move a1,[[T13]]
2718 } 2931 }
2719 2932
2720 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) { 2933 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) {
2721 entry: 2934 entry:
2722 %res = icmp ne <16 x i8> %a, %b 2935 %res = icmp ne <16 x i8> %a, %b
2723 ret <16 x i1> %res 2936 ret <16 x i1> %res
2724 ; CHECK-LABEL: test_icmp_v16i8_ne 2937 ; CHECK-LABEL: test_icmp_v16i8_ne
2725 ; CHECK: pcmpeqb 2938 ; CHECK: pcmpeqb
2726 ; CHECK: pxor 2939 ; CHECK: pxor
2727 2940
2728 ; MIPS32-LABEL: test_icmp_v16i8_ne 2941 ; MIPS32-LABEL: test_icmp_v16i8_ne
2729 ; MIPS32: lw [[BV_E0:.*]], 2942 ; MIPS32: lw [[T0:.*]],
2730 ; MIPS32: lw [[BV_E1:.*]], 2943 ; MIPS32: lw [[T1:.*]],
2731 ; MIPS32: lw [[BV_E2:.*]], 2944 ; MIPS32: lw [[T2:.*]],
2732 ; MIPS32: lw [[BV_E3:.*]], 2945 ; MIPS32: lw [[T3:.*]],
2733 ; MIPS32: move [[TV_E0:.*]],zero 2946 ; MIPS32: move [[T4:.*]],zero
2734 ; MIPS32: move [[TV_E1:.*]],zero 2947 ; MIPS32: move [[T5:.*]],zero
2735 ; MIPS32: move [[TV_E2:.*]],zero 2948 ; MIPS32: move [[T6:.*]],zero
2736 ; MIPS32: move [[TV_E3:.*]],zero 2949 ; MIPS32: move [[T7:.*]],zero
2737 ; MIPS32: andi [[T0:.*]],a0,0xff 2950 ; MIPS32: move [[T8:.*]],a0
2738 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 2951 ; MIPS32: andi [[T8]],[[T8]],0xff
2739 ; MIPS32: sll [[T0]],[[T0]],0x18 2952 ; MIPS32: move [[T9:.*]],[[T0]]
2740 ; MIPS32: sll [[T1]],[[T1]],0x18 2953 ; MIPS32: andi [[T9]],[[T9]],0xff
2741 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 2954 ; MIPS32: sll [[T8]],[[T8]],0x18
2742 ; MIPS32: sltu [[T0]],zero,[[T0]] 2955 ; MIPS32: sll [[T9]],[[T9]],0x18
2743 ; MIPS32: andi [[T0]],[[T0]],0xff 2956 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
2744 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 2957 ; MIPS32: sltu [[T8]],zero,[[T8]]
2745 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 2958 ; MIPS32: andi [[T8]],[[T8]],0xff
2746 ; MIPS32: or [[T0]],[[T0]],[[T2]] 2959 ; MIPS32: srl [[T4]],[[T4]],0x8
2747 ; MIPS32: srl [[T2]],a0,0x8 2960 ; MIPS32: sll [[T4]],[[T4]],0x8
2748 ; MIPS32: andi [[T2]],[[T2]],0xff 2961 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2749 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 2962 ; MIPS32: move [[T4]],a0
2750 ; MIPS32: andi [[T1]],[[T1]],0xff 2963 ; MIPS32: srl [[T4]],[[T4]],0x8
2751 ; MIPS32: sll [[T2]],[[T2]],0x18 2964 ; MIPS32: andi [[T4]],[[T4]],0xff
2752 ; MIPS32: sll [[T1]],[[T1]],0x18 2965 ; MIPS32: move [[T9]],[[T0]]
2753 ; MIPS32: xor [[T2]],[[T2]],[[T1]] 2966 ; MIPS32: srl [[T9]],[[T9]],0x8
2754 ; MIPS32: sltu [[T2]],zero,[[T2]] 2967 ; MIPS32: andi [[T9]],[[T9]],0xff
2755 ; MIPS32: andi [[T2]],[[T2]],0xff 2968 ; MIPS32: sll [[T4]],[[T4]],0x18
2756 ; MIPS32: sll [[T2]],[[T2]],0x8 2969 ; MIPS32: sll [[T9]],[[T9]],0x18
2757 ; MIPS32: lui [[T1]],0xffff 2970 ; MIPS32: xor [[T4]],[[T4]],[[T9]]
2758 ; MIPS32: ori [[T1]],[[T1]],0xff
2759 ; MIPS32: and [[T0]],[[T0]],[[T1]]
2760 ; MIPS32: or [[T2]],[[T2]],[[T0]]
2761 ; MIPS32: srl [[T0]],a0,0x10
2762 ; MIPS32: andi [[T0]],[[T0]],0xff
2763 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
2764 ; MIPS32: andi [[T1]],[[T1]],0xff
2765 ; MIPS32: sll [[T0]],[[T0]],0x18
2766 ; MIPS32: sll [[T1]],[[T1]],0x18
2767 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2768 ; MIPS32: sltu [[T0]],zero,[[T0]]
2769 ; MIPS32: andi [[T0]],[[T0]],0xff
2770 ; MIPS32: sll [[T0]],[[T0]],0x10
2771 ; MIPS32: lui [[T1]],0xff00
2772 ; MIPS32: ori [[T1]],[[T1]],0xffff
2773 ; MIPS32: and [[T2]],[[T2]],[[T1]]
2774 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2775 ; MIPS32: srl [[T3:.*]],a0,0x18
2776 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
2777 ; MIPS32: sll [[T3]],[[T3]],0x18
2778 ; MIPS32: sll [[T4]],[[T4]],0x18
2779 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
2780 ; MIPS32: sltu [[T3]],zero,[[T3]]
2781 ; MIPS32: srl [[T3]],[[T3]],0x18
2782 ; MIPS32: sll [[T0]],[[T0]],0x8
2783 ; MIPS32: srl [[T0]],[[T0]],0x8
2784 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2785 ; MIPS32: andi [[T4]],a1,0xff
2786 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
2787 ; MIPS32: sll [[T4]],[[T4]],0x18
2788 ; MIPS32: sll [[T2]],[[T2]],0x18
2789 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2790 ; MIPS32: sltu [[T4]],zero,[[T4]] 2971 ; MIPS32: sltu [[T4]],zero,[[T4]]
2791 ; MIPS32: andi [[T4]],[[T4]],0xff 2972 ; MIPS32: andi [[T4]],[[T4]],0xff
2792 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 2973 ; MIPS32: sll [[T4]],[[T4]],0x8
2793 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 2974 ; MIPS32: lui [[T9]],0xffff
2794 ; MIPS32: or [[T4]],[[T4]],[[T5]] 2975 ; MIPS32: ori [[T9]],[[T9]],0xff
2795 ; MIPS32: srl [[T2]],a1,0x8 2976 ; MIPS32: and [[T8]],[[T8]],[[T9]]
2796 ; MIPS32: andi [[T2]],[[T2]],0xff 2977 ; MIPS32: or [[T4]],[[T4]],[[T8]]
2797 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 2978 ; MIPS32: move [[T8]],a0
2798 ; MIPS32: andi [[T5]],[[T5]],0xff 2979 ; MIPS32: srl [[T8]],[[T8]],0x10
2799 ; MIPS32: sll [[T2]],[[T2]],0x18 2980 ; MIPS32: andi [[T8]],[[T8]],0xff
2800 ; MIPS32: sll [[T5]],[[T5]],0x18 2981 ; MIPS32: move [[T9]],[[T0]]
2801 ; MIPS32: xor [[T2]],[[T2]],[[T5]] 2982 ; MIPS32: srl [[T9]],[[T9]],0x10
2802 ; MIPS32: sltu [[T2]],zero,[[T2]] 2983 ; MIPS32: andi [[T9]],[[T9]],0xff
2803 ; MIPS32: andi [[T2]],[[T2]],0xff 2984 ; MIPS32: sll [[T8]],[[T8]],0x18
2804 ; MIPS32: sll [[T2]],[[T2]],0x8 2985 ; MIPS32: sll [[T9]],[[T9]],0x18
2805 ; MIPS32: lui [[T5]],0xffff 2986 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
2806 ; MIPS32: ori [[T5]],[[T5]],0xff 2987 ; MIPS32: sltu [[T8]],zero,[[T8]]
2807 ; MIPS32: and [[T4]],[[T4]],[[T5]] 2988 ; MIPS32: andi [[T8]],[[T8]],0xff
2808 ; MIPS32: or [[T2]],[[T2]],[[T4]] 2989 ; MIPS32: sll [[T8]],[[T8]],0x10
2809 ; MIPS32: srl [[T4]],a1,0x10 2990 ; MIPS32: lui [[T9]],0xff00
2810 ; MIPS32: andi [[T4]],[[T4]],0xff 2991 ; MIPS32: ori [[T9]],[[T9]],0xffff
2811 ; MIPS32: srl [[T5]],[[BV_E1]],0x10 2992 ; MIPS32: and [[T4]],[[T4]],[[T9]]
2993 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2994 ; MIPS32: srl [[T10:.*]],a0,0x18
2995 ; MIPS32: srl [[T0]],[[T0]],0x18
2996 ; MIPS32: sll [[T10]],[[T10]],0x18
2997 ; MIPS32: sll [[T0]],[[T0]],0x18
2998 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
2999 ; MIPS32: sltu [[T10]],zero,[[T10]]
3000 ; MIPS32: srl [[T10]],[[T10]],0x18
3001 ; MIPS32: sll [[T8]],[[T8]],0x8
3002 ; MIPS32: srl [[T8]],[[T8]],0x8
3003 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3004 ; MIPS32: move [[T0]],a1
3005 ; MIPS32: andi [[T0]],[[T0]],0xff
3006 ; MIPS32: move [[T4]],[[T1]]
3007 ; MIPS32: andi [[T4]],[[T4]],0xff
3008 ; MIPS32: sll [[T0]],[[T0]],0x18
3009 ; MIPS32: sll [[T4]],[[T4]],0x18
3010 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
3011 ; MIPS32: sltu [[T0]],zero,[[T0]]
3012 ; MIPS32: andi [[T0]],[[T0]],0xff
3013 ; MIPS32: srl [[T5]],[[T5]],0x8
3014 ; MIPS32: sll [[T5]],[[T5]],0x8
3015 ; MIPS32: or [[T0]],[[T0]],[[T5]]
3016 ; MIPS32: move [[T4]],a1
3017 ; MIPS32: srl [[T4]],[[T4]],0x8
3018 ; MIPS32: andi [[T4]],[[T4]],0xff
3019 ; MIPS32: move [[T5]],[[T1]]
3020 ; MIPS32: srl [[T5]],[[T5]],0x8
2812 ; MIPS32: andi [[T5]],[[T5]],0xff 3021 ; MIPS32: andi [[T5]],[[T5]],0xff
2813 ; MIPS32: sll [[T4]],[[T4]],0x18 3022 ; MIPS32: sll [[T4]],[[T4]],0x18
2814 ; MIPS32: sll [[T5]],[[T5]],0x18 3023 ; MIPS32: sll [[T5]],[[T5]],0x18
2815 ; MIPS32: xor [[T4]],[[T4]],[[T5]] 3024 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
2816 ; MIPS32: sltu [[T4]],zero,[[T4]] 3025 ; MIPS32: sltu [[T4]],zero,[[T4]]
2817 ; MIPS32: andi [[T4]],[[T4]],0xff 3026 ; MIPS32: andi [[T4]],[[T4]],0xff
2818 ; MIPS32: sll [[T4]],[[T4]],0x10 3027 ; MIPS32: sll [[T4]],[[T4]],0x8
3028 ; MIPS32: lui [[T5]],0xffff
3029 ; MIPS32: ori [[T5]],[[T5]],0xff
3030 ; MIPS32: and [[T0]],[[T0]],[[T5]]
3031 ; MIPS32: or [[T4]],[[T4]],[[T0]]
3032 ; MIPS32: move [[T0]],a1
3033 ; MIPS32: srl [[T0]],[[T0]],0x10
3034 ; MIPS32: andi [[T0]],[[T0]],0xff
3035 ; MIPS32: move [[T5]],[[T1]]
3036 ; MIPS32: srl [[T5]],[[T5]],0x10
3037 ; MIPS32: andi [[T5]],[[T5]],0xff
3038 ; MIPS32: sll [[T0]],[[T0]],0x18
3039 ; MIPS32: sll [[T5]],[[T5]],0x18
3040 ; MIPS32: xor [[T0]],[[T0]],[[T5]]
3041 ; MIPS32: sltu [[T0]],zero,[[T0]]
3042 ; MIPS32: andi [[T0]],[[T0]],0xff
3043 ; MIPS32: sll [[T0]],[[T0]],0x10
2819 ; MIPS32: lui [[T5]],0xff00 3044 ; MIPS32: lui [[T5]],0xff00
2820 ; MIPS32: ori [[T5]],[[T5]],0xffff 3045 ; MIPS32: ori [[T5]],[[T5]],0xffff
2821 ; MIPS32: and [[T2]],[[T2]],[[T5]] 3046 ; MIPS32: and [[T4]],[[T4]],[[T5]]
2822 ; MIPS32: or [[T4]],[[T4]],[[T2]] 3047 ; MIPS32: or [[T0]],[[T0]],[[T4]]
2823 ; MIPS32: srl [[T6:.*]],a1,0x18 3048 ; MIPS32: srl [[T11:.*]],a1,0x18
2824 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 3049 ; MIPS32: srl [[T1]],[[T1]],0x18
2825 ; MIPS32: sll [[T6]],[[T6]],0x18 3050 ; MIPS32: sll [[T11]],[[T11]],0x18
2826 ; MIPS32: sll [[T7]],[[T7]],0x18 3051 ; MIPS32: sll [[T1]],[[T1]],0x18
2827 ; MIPS32: xor [[T6]],[[T6]],[[T7]] 3052 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
2828 ; MIPS32: sltu [[T6]],zero,[[T6]] 3053 ; MIPS32: sltu [[T11]],zero,[[T11]]
2829 ; MIPS32: srl [[T6]],[[T6]],0x18 3054 ; MIPS32: srl [[T11]],[[T11]],0x18
2830 ; MIPS32: sll [[T4]],[[T4]],0x8 3055 ; MIPS32: sll [[T0]],[[T0]],0x8
2831 ; MIPS32: srl [[T4]],[[T4]],0x8 3056 ; MIPS32: srl [[T0]],[[T0]],0x8
2832 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] 3057 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2833 ; MIPS32: andi [[T4]],a2,0xff 3058 ; MIPS32: move [[T0]],a2
2834 ; MIPS32: andi [[T7]],[[BV_E2]],0xff 3059 ; MIPS32: andi [[T0]],[[T0]],0xff
2835 ; MIPS32: sll [[T4]],[[T4]],0x18 3060 ; MIPS32: move [[T1]],[[T2]]
2836 ; MIPS32: sll [[T7]],[[T7]],0x18 3061 ; MIPS32: andi [[T1]],[[T1]],0xff
2837 ; MIPS32: xor [[T4]],[[T4]],[[T7]] 3062 ; MIPS32: sll [[T0]],[[T0]],0x18
2838 ; MIPS32: sltu [[T4]],zero,[[T4]] 3063 ; MIPS32: sll [[T1]],[[T1]],0x18
2839 ; MIPS32: andi [[T4]],[[T4]],0xff 3064 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2840 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 3065 ; MIPS32: sltu [[T0]],zero,[[T0]]
2841 ; MIPS32: sll [[T8]],[[TV_E2]],0x8 3066 ; MIPS32: andi [[T0]],[[T0]],0xff
2842 ; MIPS32: or [[T4]],[[T4]],[[T8]] 3067 ; MIPS32: srl [[T6]],[[T6]],0x8
2843 ; MIPS32: srl [[T7]],a2,0x8 3068 ; MIPS32: sll [[T6]],[[T6]],0x8
2844 ; MIPS32: andi [[T7]],[[T7]],0xff 3069 ; MIPS32: or [[T0]],[[T0]],[[T6]]
2845 ; MIPS32: srl [[T2]],[[BV_E2]],0x8 3070 ; MIPS32: move [[T1]],a2
3071 ; MIPS32: srl [[T1]],[[T1]],0x8
3072 ; MIPS32: andi [[T1]],[[T1]],0xff
3073 ; MIPS32: move [[T4]],[[T2]]
3074 ; MIPS32: srl [[T4]],[[T4]],0x8
3075 ; MIPS32: andi [[T4]],[[T4]],0xff
3076 ; MIPS32: sll [[T1]],[[T1]],0x18
3077 ; MIPS32: sll [[T4]],[[T4]],0x18
3078 ; MIPS32: xor [[T1]],[[T1]],[[T4]]
3079 ; MIPS32: sltu [[T1]],zero,[[T1]]
3080 ; MIPS32: andi [[T1]],[[T1]],0xff
3081 ; MIPS32: sll [[T1]],[[T1]],0x8
3082 ; MIPS32: lui [[T4]],0xffff
3083 ; MIPS32: ori [[T4]],[[T4]],0xff
3084 ; MIPS32: and [[T0]],[[T0]],[[T4]]
3085 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3086 ; MIPS32: move [[T0]],a2
3087 ; MIPS32: srl [[T0]],[[T0]],0x10
3088 ; MIPS32: andi [[T0]],[[T0]],0xff
3089 ; MIPS32: move [[T4]],[[T2]]
3090 ; MIPS32: srl [[T4]],[[T4]],0x10
3091 ; MIPS32: andi [[T4]],[[T4]],0xff
3092 ; MIPS32: sll [[T0]],[[T0]],0x18
3093 ; MIPS32: sll [[T4]],[[T4]],0x18
3094 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
3095 ; MIPS32: sltu [[T0]],zero,[[T0]]
3096 ; MIPS32: andi [[T0]],[[T0]],0xff
3097 ; MIPS32: sll [[T0]],[[T0]],0x10
3098 ; MIPS32: lui [[T4]],0xff00
3099 ; MIPS32: ori [[T4]],[[T4]],0xffff
3100 ; MIPS32: and [[T1]],[[T1]],[[T4]]
3101 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3102 ; MIPS32: srl [[T12:.*]],a2,0x18
3103 ; MIPS32: srl [[T2]],[[T2]],0x18
3104 ; MIPS32: sll [[T12]],[[T12]],0x18
3105 ; MIPS32: sll [[T2]],[[T2]],0x18
3106 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
3107 ; MIPS32: sltu [[T12]],zero,[[T12]]
3108 ; MIPS32: srl [[T12]],[[T12]],0x18
3109 ; MIPS32: sll [[T0]],[[T0]],0x8
3110 ; MIPS32: srl [[T0]],[[T0]],0x8
3111 ; MIPS32: or [[T12]],[[T12]],[[T0]]
3112 ; MIPS32: move [[T0]],a3
3113 ; MIPS32: andi [[T0]],[[T0]],0xff
3114 ; MIPS32: move [[T1]],[[T3]]
3115 ; MIPS32: andi [[T1]],[[T1]],0xff
3116 ; MIPS32: sll [[T0]],[[T0]],0x18
3117 ; MIPS32: sll [[T1]],[[T1]],0x18
3118 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
3119 ; MIPS32: sltu [[T0]],zero,[[T0]]
3120 ; MIPS32: andi [[T0]],[[T0]],0xff
3121 ; MIPS32: srl [[T7]],[[T7]],0x8
3122 ; MIPS32: sll [[T7]],[[T7]],0x8
3123 ; MIPS32: or [[T0]],[[T0]],[[T7]]
3124 ; MIPS32: move [[T1]],a3
3125 ; MIPS32: srl [[T1]],[[T1]],0x8
3126 ; MIPS32: andi [[T1]],[[T1]],0xff
3127 ; MIPS32: move [[T2]],[[T3]]
3128 ; MIPS32: srl [[T2]],[[T2]],0x8
2846 ; MIPS32: andi [[T2]],[[T2]],0xff 3129 ; MIPS32: andi [[T2]],[[T2]],0xff
2847 ; MIPS32: sll [[T7]],[[T7]],0x18 3130 ; MIPS32: sll [[T1]],[[T1]],0x18
2848 ; MIPS32: sll [[T2]],[[T2]],0x18 3131 ; MIPS32: sll [[T2]],[[T2]],0x18
2849 ; MIPS32: xor [[T7]],[[T7]],[[T2]] 3132 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
2850 ; MIPS32: sltu [[T7]],zero,[[T7]] 3133 ; MIPS32: sltu [[T1]],zero,[[T1]]
2851 ; MIPS32: andi [[T7]],[[T7]],0xff 3134 ; MIPS32: andi [[T1]],[[T1]],0xff
2852 ; MIPS32: sll [[T7]],[[T7]],0x8 3135 ; MIPS32: sll [[T1]],[[T1]],0x8
2853 ; MIPS32: lui [[T2]],0xffff 3136 ; MIPS32: lui [[T2]],0xffff
2854 ; MIPS32: ori [[T2]],[[T2]],0xff 3137 ; MIPS32: ori [[T2]],[[T2]],0xff
2855 ; MIPS32: and [[T4]],[[T4]],[[T2]] 3138 ; MIPS32: and [[T0]],[[T0]],[[T2]]
2856 ; MIPS32: or [[T7]],[[T7]],[[T4]] 3139 ; MIPS32: or [[T1]],[[T1]],[[T0]]
2857 ; MIPS32: srl [[T4]],a2,0x10 3140 ; MIPS32: move [[T0]],a3
2858 ; MIPS32: andi [[T4]],[[T4]],0xff 3141 ; MIPS32: srl [[T0]],[[T0]],0x10
2859 ; MIPS32: srl [[T2]],[[BV_E2]],0x10 3142 ; MIPS32: andi [[T0]],[[T0]],0xff
3143 ; MIPS32: move [[T2]],[[T3]]
3144 ; MIPS32: srl [[T2]],[[T2]],0x10
2860 ; MIPS32: andi [[T2]],[[T2]],0xff 3145 ; MIPS32: andi [[T2]],[[T2]],0xff
2861 ; MIPS32: sll [[T4]],[[T4]],0x18 3146 ; MIPS32: sll [[T0]],[[T0]],0x18
2862 ; MIPS32: sll [[T2]],[[T2]],0x18 3147 ; MIPS32: sll [[T2]],[[T2]],0x18
2863 ; MIPS32: xor [[T4]],[[T4]],[[T2]] 3148 ; MIPS32: xor [[T0]],[[T0]],[[T2]]
2864 ; MIPS32: sltu [[T4]],zero,[[T4]] 3149 ; MIPS32: sltu [[T0]],zero,[[T0]]
2865 ; MIPS32: andi [[T4]],[[T4]],0xff 3150 ; MIPS32: andi [[T0]],[[T0]],0xff
2866 ; MIPS32: sll [[T4]],[[T4]],0x10 3151 ; MIPS32: sll [[T0]],[[T0]],0x10
2867 ; MIPS32: lui [[T2]],0xff00 3152 ; MIPS32: lui [[T2]],0xff00
2868 ; MIPS32: ori [[T2]],[[T2]],0xffff 3153 ; MIPS32: ori [[T2]],[[T2]],0xffff
2869 ; MIPS32: and [[T7]],[[T7]],[[T2]] 3154 ; MIPS32: and [[T1]],[[T1]],[[T2]]
2870 ; MIPS32: or [[T4]],[[T4]],[[T7]] 3155 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2871 ; MIPS32: srl [[T9:.*]],a2,0x18 3156 ; MIPS32: srl [[T13:.*]],a3,0x18
2872 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 3157 ; MIPS32: srl [[T3]],[[T3]],0x18
2873 ; MIPS32: sll [[T9]],[[T9]],0x18
2874 ; MIPS32: sll [[T10]],[[T10]],0x18
2875 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
2876 ; MIPS32: sltu [[T9]],zero,[[T9]]
2877 ; MIPS32: srl [[T9]],[[T9]],0x18
2878 ; MIPS32: sll [[T4]],[[T4]],0x8
2879 ; MIPS32: srl [[T4]],[[T4]],0x8
2880 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
2881 ; MIPS32: andi [[T4]],a3,0xff
2882 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
2883 ; MIPS32: sll [[T4]],[[T4]],0x18
2884 ; MIPS32: sll [[T7]],[[T7]],0x18
2885 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2886 ; MIPS32: sltu [[T4]],zero,[[T4]]
2887 ; MIPS32: andi [[T4]],[[T4]],0xff
2888 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
2889 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
2890 ; MIPS32: or [[T4]],[[T4]],[[T11]]
2891 ; MIPS32: srl [[T7]],a3,0x8
2892 ; MIPS32: andi [[T7]],[[T7]],0xff
2893 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
2894 ; MIPS32: andi [[T10]],[[T10]],0xff
2895 ; MIPS32: sll [[T7]],[[T7]],0x18
2896 ; MIPS32: sll [[T10]],[[T10]],0x18
2897 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
2898 ; MIPS32: sltu [[T7]],zero,[[T7]]
2899 ; MIPS32: andi [[T7]],[[T7]],0xff
2900 ; MIPS32: sll [[T7]],[[T7]],0x8
2901 ; MIPS32: lui [[T10]],0xffff
2902 ; MIPS32: ori [[T10]],[[T10]],0xff
2903 ; MIPS32: and [[T4]],[[T4]],[[T10]]
2904 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2905 ; MIPS32: srl [[T4]],a3,0x10
2906 ; MIPS32: andi [[T4]],[[T4]],0xff
2907 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
2908 ; MIPS32: andi [[T10]],[[T10]],0xff
2909 ; MIPS32: sll [[T4]],[[T4]],0x18
2910 ; MIPS32: sll [[T10]],[[T10]],0x18
2911 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
2912 ; MIPS32: sltu [[T4]],zero,[[T4]]
2913 ; MIPS32: andi [[T4]],[[T4]],0xff
2914 ; MIPS32: sll [[T4]],[[T4]],0x10
2915 ; MIPS32: lui [[T10]],0xff00
2916 ; MIPS32: ori [[T10]],[[T10]],0xffff
2917 ; MIPS32: and [[T7]],[[T7]],[[T10]]
2918 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2919 ; MIPS32: srl [[T12:.*]],a3,0x18
2920 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
2921 ; MIPS32: sll [[T12]],[[T12]],0x18
2922 ; MIPS32: sll [[T13]],[[T13]],0x18 3158 ; MIPS32: sll [[T13]],[[T13]],0x18
2923 ; MIPS32: xor [[T12]],[[T12]],[[T13]] 3159 ; MIPS32: sll [[T3]],[[T3]],0x18
2924 ; MIPS32: sltu [[T12]],zero,[[T12]] 3160 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
2925 ; MIPS32: srl [[T12]],[[T12]],0x18 3161 ; MIPS32: sltu [[T13]],zero,[[T13]]
2926 ; MIPS32: sll [[T4]],[[T4]],0x8 3162 ; MIPS32: srl [[T13]],[[T13]],0x18
2927 ; MIPS32: srl [[T4]],[[T4]],0x8 3163 ; MIPS32: sll [[T0]],[[T0]],0x8
2928 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 3164 ; MIPS32: srl [[T0]],[[T0]],0x8
3165 ; MIPS32: or [[T13]],[[T13]],[[T0]]
3166 ; MIPS32: move v0,[[T10]]
3167 ; MIPS32: move v1,[[T11]]
3168 ; MIPS32: move a0,[[T12]]
3169 ; MIPS32: move a1,[[T13]]
2929 } 3170 }
2930 3171
2931 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) { 3172 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) {
2932 entry: 3173 entry:
2933 %res = icmp sgt <16 x i8> %a, %b 3174 %res = icmp sgt <16 x i8> %a, %b
2934 ret <16 x i1> %res 3175 ret <16 x i1> %res
2935 ; CHECK-LABEL: test_icmp_v16i8_sgt 3176 ; CHECK-LABEL: test_icmp_v16i8_sgt
2936 ; CHECK: pcmpgtb 3177 ; CHECK: pcmpgtb
2937 3178
2938 ; MIPS32-LABEL: test_icmp_v16i8_sgt 3179 ; MIPS32-LABEL: test_icmp_v16i8_sgt
2939 ; MIPS32: lw [[BV_E0:.*]], 3180 ; MIPS32: lw [[T0:.*]],
2940 ; MIPS32: lw [[BV_E1:.*]], 3181 ; MIPS32: lw [[T1:.*]],
2941 ; MIPS32: lw [[BV_E2:.*]], 3182 ; MIPS32: lw [[T2:.*]],
2942 ; MIPS32: lw [[BV_E3:.*]], 3183 ; MIPS32: lw [[T3:.*]],
2943 ; MIPS32: move [[TV_E0:.*]],zero 3184 ; MIPS32: move [[T4:.*]],zero
2944 ; MIPS32: move [[TV_E1:.*]],zero 3185 ; MIPS32: move [[T5:.*]],zero
2945 ; MIPS32: move [[TV_E2:.*]],zero 3186 ; MIPS32: move [[T6:.*]],zero
2946 ; MIPS32: move [[TV_E3:.*]],zero 3187 ; MIPS32: move [[T7:.*]],zero
2947 ; MIPS32: andi [[T0:.*]],a0,0xff 3188 ; MIPS32: move [[T8:.*]],a0
2948 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 3189 ; MIPS32: andi [[T8]],[[T8]],0xff
2949 ; MIPS32: sll [[T0]],[[T0]],0x18 3190 ; MIPS32: move [[T9:.*]],[[T0]]
2950 ; MIPS32: sll [[T1]],[[T1]],0x18 3191 ; MIPS32: andi [[T9]],[[T9]],0xff
2951 ; MIPS32: slt [[T1]],[[T1]],[[T0]] 3192 ; MIPS32: sll [[T8]],[[T8]],0x18
2952 ; MIPS32: andi [[T1]],[[T1]],0xff 3193 ; MIPS32: sll [[T9]],[[T9]],0x18
2953 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 3194 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
2954 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 3195 ; MIPS32: andi [[T9]],[[T9]],0xff
2955 ; MIPS32: or [[T1]],[[T1]],[[T2]] 3196 ; MIPS32: srl [[T4]],[[T4]],0x8
2956 ; MIPS32: srl [[T2]],a0,0x8 3197 ; MIPS32: sll [[T4]],[[T4]],0x8
2957 ; MIPS32: andi [[T2]],[[T2]],0xff 3198 ; MIPS32: or [[T9]],[[T9]],[[T4]]
2958 ; MIPS32: srl [[T0]],[[BV_E0]],0x8 3199 ; MIPS32: move [[T4]],a0
2959 ; MIPS32: andi [[T0]],[[T0]],0xff 3200 ; MIPS32: srl [[T4]],[[T4]],0x8
2960 ; MIPS32: sll [[T2]],[[T2]],0x18 3201 ; MIPS32: andi [[T4]],[[T4]],0xff
2961 ; MIPS32: sll [[T0]],[[T0]],0x18 3202 ; MIPS32: move [[T8]],[[T0]]
2962 ; MIPS32: slt [[T0]],[[T0]],[[T2]] 3203 ; MIPS32: srl [[T8]],[[T8]],0x8
2963 ; MIPS32: andi [[T0]],[[T0]],0xff 3204 ; MIPS32: andi [[T8]],[[T8]],0xff
2964 ; MIPS32: sll [[T0]],[[T0]],0x8 3205 ; MIPS32: sll [[T4]],[[T4]],0x18
2965 ; MIPS32: lui [[T2]],0xffff 3206 ; MIPS32: sll [[T8]],[[T8]],0x18
2966 ; MIPS32: ori [[T2]],[[T2]],0xff 3207 ; MIPS32: slt [[T8]],[[T8]],[[T4]]
2967 ; MIPS32: and [[T1]],[[T1]],[[T2]] 3208 ; MIPS32: andi [[T8]],[[T8]],0xff
2968 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3209 ; MIPS32: sll [[T8]],[[T8]],0x8
2969 ; MIPS32: srl [[T2]],a0,0x10 3210 ; MIPS32: lui [[T4]],0xffff
2970 ; MIPS32: andi [[T2]],[[T2]],0xff 3211 ; MIPS32: ori [[T4]],[[T4]],0xff
2971 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 3212 ; MIPS32: and [[T9]],[[T9]],[[T4]]
2972 ; MIPS32: andi [[T1]],[[T1]],0xff 3213 ; MIPS32: or [[T8]],[[T8]],[[T9]]
2973 ; MIPS32: sll [[T2]],[[T2]],0x18 3214 ; MIPS32: move [[T4]],a0
2974 ; MIPS32: sll [[T1]],[[T1]],0x18 3215 ; MIPS32: srl [[T4]],[[T4]],0x10
2975 ; MIPS32: slt [[T1]],[[T1]],[[T2]] 3216 ; MIPS32: andi [[T4]],[[T4]],0xff
2976 ; MIPS32: andi [[T1]],[[T1]],0xff 3217 ; MIPS32: move [[T9]],[[T0]]
2977 ; MIPS32: sll [[T1]],[[T1]],0x10 3218 ; MIPS32: srl [[T9]],[[T9]],0x10
2978 ; MIPS32: lui [[T2]],0xff00 3219 ; MIPS32: andi [[T9]],[[T9]],0xff
2979 ; MIPS32: ori [[T2]],[[T2]],0xffff 3220 ; MIPS32: sll [[T4]],[[T4]],0x18
2980 ; MIPS32: and [[T0]],[[T0]],[[T2]] 3221 ; MIPS32: sll [[T9]],[[T9]],0x18
2981 ; MIPS32: or [[T1]],[[T1]],[[T0]] 3222 ; MIPS32: slt [[T9]],[[T9]],[[T4]]
2982 ; MIPS32: srl [[T3:.*]],a0,0x18 3223 ; MIPS32: andi [[T9]],[[T9]],0xff
2983 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 3224 ; MIPS32: sll [[T9]],[[T9]],0x10
2984 ; MIPS32: sll [[T3]],[[T3]],0x18 3225 ; MIPS32: lui [[T4]],0xff00
2985 ; MIPS32: sll [[T4]],[[T4]],0x18 3226 ; MIPS32: ori [[T4]],[[T4]],0xffff
2986 ; MIPS32: slt [[T4]],[[T4]],[[T3]] 3227 ; MIPS32: and [[T8]],[[T8]],[[T4]]
2987 ; MIPS32: srl [[T4]],[[T4]],0x18 3228 ; MIPS32: or [[T9]],[[T9]],[[T8]]
2988 ; MIPS32: sll [[T1]],[[T1]],0x8 3229 ; MIPS32: srl [[T10:.*]],a0,0x18
2989 ; MIPS32: srl [[T1]],[[T1]],0x8 3230 ; MIPS32: srl [[T0]],[[T0]],0x18
2990 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 3231 ; MIPS32: sll [[T10]],[[T10]],0x18
2991 ; MIPS32: andi [[T3]],a1,0xff 3232 ; MIPS32: sll [[T0]],[[T0]],0x18
2992 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 3233 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
2993 ; MIPS32: sll [[T3]],[[T3]],0x18 3234 ; MIPS32: srl [[T0]],[[T0]],0x18
2994 ; MIPS32: sll [[T2]],[[T2]],0x18 3235 ; MIPS32: sll [[T9]],[[T9]],0x8
2995 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 3236 ; MIPS32: srl [[T9]],[[T9]],0x8
2996 ; MIPS32: andi [[T2]],[[T2]],0xff 3237 ; MIPS32: or v0,[[T0]],[[T9]]
2997 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 3238 ; MIPS32: move [[T10]],a1
2998 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 3239 ; MIPS32: andi [[T10]],[[T10]],0xff
2999 ; MIPS32: or [[T2]],[[T2]],[[T5]] 3240 ; MIPS32: move [[T4]],[[T1]]
3000 ; MIPS32: srl [[T3]],a1,0x8 3241 ; MIPS32: andi [[T4]],[[T4]],0xff
3001 ; MIPS32: andi [[T3]],[[T3]],0xff 3242 ; MIPS32: sll [[T10]],[[T10]],0x18
3002 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 3243 ; MIPS32: sll [[T4]],[[T4]],0x18
3244 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3245 ; MIPS32: andi [[T4]],[[T4]],0xff
3246 ; MIPS32: srl [[T5]],[[T5]],0x8
3247 ; MIPS32: sll [[T5]],[[T5]],0x8
3248 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3249 ; MIPS32: move [[T10]],a1
3250 ; MIPS32: srl [[T10]],[[T10]],0x8
3251 ; MIPS32: andi [[T10]],[[T10]],0xff
3252 ; MIPS32: move [[T5]],[[T1]]
3253 ; MIPS32: srl [[T5]],[[T5]],0x8
3003 ; MIPS32: andi [[T5]],[[T5]],0xff 3254 ; MIPS32: andi [[T5]],[[T5]],0xff
3004 ; MIPS32: sll [[T3]],[[T3]],0x18 3255 ; MIPS32: sll [[T10]],[[T10]],0x18
3005 ; MIPS32: sll [[T5]],[[T5]],0x18 3256 ; MIPS32: sll [[T5]],[[T5]],0x18
3006 ; MIPS32: slt [[T5]],[[T5]],[[T3]] 3257 ; MIPS32: slt [[T5]],[[T5]],[[T10]]
3007 ; MIPS32: andi [[T5]],[[T5]],0xff 3258 ; MIPS32: andi [[T5]],[[T5]],0xff
3008 ; MIPS32: sll [[T5]],[[T5]],0x8 3259 ; MIPS32: sll [[T5]],[[T5]],0x8
3009 ; MIPS32: lui [[T3]],0xffff 3260 ; MIPS32: lui [[T10]],0xffff
3010 ; MIPS32: ori [[T3]],[[T3]],0xff 3261 ; MIPS32: ori [[T10]],[[T10]],0xff
3011 ; MIPS32: and [[T2]],[[T2]],[[T3]] 3262 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3012 ; MIPS32: or [[T5]],[[T5]],[[T2]] 3263 ; MIPS32: or [[T5]],[[T5]],[[T4]]
3013 ; MIPS32: srl [[T3]],a1,0x10 3264 ; MIPS32: move [[T10]],a1
3014 ; MIPS32: andi [[T3]],[[T3]],0xff 3265 ; MIPS32: srl [[T10]],[[T10]],0x10
3015 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 3266 ; MIPS32: andi [[T10]],[[T10]],0xff
3016 ; MIPS32: andi [[T2]],[[T2]],0xff 3267 ; MIPS32: move [[T4]],[[T1]]
3268 ; MIPS32: srl [[T4]],[[T4]],0x10
3269 ; MIPS32: andi [[T4]],[[T4]],0xff
3270 ; MIPS32: sll [[T10]],[[T10]],0x18
3271 ; MIPS32: sll [[T4]],[[T4]],0x18
3272 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3273 ; MIPS32: andi [[T4]],[[T4]],0xff
3274 ; MIPS32: sll [[T4]],[[T4]],0x10
3275 ; MIPS32: lui [[T10]],0xff00
3276 ; MIPS32: ori [[T10]],[[T10]],0xffff
3277 ; MIPS32: and [[T5]],[[T5]],[[T10]]
3278 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3279 ; MIPS32: srl [[T11:.*]],a1,0x18
3280 ; MIPS32: srl [[T1]],[[T1]],0x18
3281 ; MIPS32: sll [[T11]],[[T11]],0x18
3282 ; MIPS32: sll [[T1]],[[T1]],0x18
3283 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
3284 ; MIPS32: srl [[T1]],[[T1]],0x18
3285 ; MIPS32: sll [[T4]],[[T4]],0x8
3286 ; MIPS32: srl [[T4]],[[T4]],0x8
3287 ; MIPS32: or v1,[[T1]],[[T4]]
3288 ; MIPS32: move [[T10]],a2
3289 ; MIPS32: andi [[T10]],[[T10]],0xff
3290 ; MIPS32: move [[T11]],[[T2]]
3291 ; MIPS32: andi [[T11]],[[T11]],0xff
3292 ; MIPS32: sll [[T10]],[[T10]],0x18
3293 ; MIPS32: sll [[T11]],[[T11]],0x18
3294 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3295 ; MIPS32: andi [[T11]],[[T11]],0xff
3296 ; MIPS32: srl [[T6]],[[T6]],0x8
3297 ; MIPS32: sll [[T6]],[[T6]],0x8
3298 ; MIPS32: or [[T11]],[[T11]],[[T6]]
3299 ; MIPS32: move [[T10]],a2
3300 ; MIPS32: srl [[T10]],[[T10]],0x8
3301 ; MIPS32: andi [[T10]],[[T10]],0xff
3302 ; MIPS32: move [[T4]],[[T2]]
3303 ; MIPS32: srl [[T4]],[[T4]],0x8
3304 ; MIPS32: andi [[T4]],[[T4]],0xff
3305 ; MIPS32: sll [[T10]],[[T10]],0x18
3306 ; MIPS32: sll [[T4]],[[T4]],0x18
3307 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3308 ; MIPS32: andi [[T4]],[[T4]],0xff
3309 ; MIPS32: sll [[T4]],[[T4]],0x8
3310 ; MIPS32: lui [[T10]],0xffff
3311 ; MIPS32: ori [[T10]],[[T10]],0xff
3312 ; MIPS32: and [[T11]],[[T11]],[[T10]]
3313 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3314 ; MIPS32: move [[T10]],a2
3315 ; MIPS32: srl [[T10]],[[T10]],0x10
3316 ; MIPS32: andi [[T10]],[[T10]],0xff
3317 ; MIPS32: move [[T11]],[[T2]]
3318 ; MIPS32: srl [[T11]],[[T11]],0x10
3319 ; MIPS32: andi [[T11]],[[T11]],0xff
3320 ; MIPS32: sll [[T10]],[[T10]],0x18
3321 ; MIPS32: sll [[T11]],[[T11]],0x18
3322 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3323 ; MIPS32: andi [[T11]],[[T11]],0xff
3324 ; MIPS32: sll [[T11]],[[T11]],0x10
3325 ; MIPS32: lui [[T10]],0xff00
3326 ; MIPS32: ori [[T10]],[[T10]],0xffff
3327 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3328 ; MIPS32: or [[T11]],[[T11]],[[T4]]
3329 ; MIPS32: srl [[T12:.*]],a2,0x18
3330 ; MIPS32: srl [[T2]],[[T2]],0x18
3331 ; MIPS32: sll [[T12]],[[T12]],0x18
3332 ; MIPS32: sll [[T2]],[[T2]],0x18
3333 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
3334 ; MIPS32: srl [[T2]],[[T2]],0x18
3335 ; MIPS32: sll [[T11]],[[T11]],0x8
3336 ; MIPS32: srl [[T11]],[[T11]],0x8
3337 ; MIPS32: or [[T2]],[[T2]],[[T11]]
3338 ; MIPS32: move [[T10]],a3
3339 ; MIPS32: andi [[T10]],[[T10]],0xff
3340 ; MIPS32: move [[T11]],[[T3]]
3341 ; MIPS32: andi [[T11]],[[T11]],0xff
3342 ; MIPS32: sll [[T10]],[[T10]],0x18
3343 ; MIPS32: sll [[T11]],[[T11]],0x18
3344 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3345 ; MIPS32: andi [[T11]],[[T11]],0xff
3346 ; MIPS32: srl [[T7]],[[T7]],0x8
3347 ; MIPS32: sll [[T7]],[[T7]],0x8
3348 ; MIPS32: or [[T11]],[[T11]],[[T7]]
3349 ; MIPS32: move [[T10]],a3
3350 ; MIPS32: srl [[T10]],[[T10]],0x8
3351 ; MIPS32: andi [[T10]],[[T10]],0xff
3352 ; MIPS32: move [[T12]],[[T3]]
3353 ; MIPS32: srl [[T12]],[[T12]],0x8
3354 ; MIPS32: andi [[T12]],[[T12]],0xff
3355 ; MIPS32: sll [[T10]],[[T10]],0x18
3356 ; MIPS32: sll [[T12]],[[T12]],0x18
3357 ; MIPS32: slt [[T12]],[[T12]],[[T10]]
3358 ; MIPS32: andi [[T12]],[[T12]],0xff
3359 ; MIPS32: sll [[T12]],[[T12]],0x8
3360 ; MIPS32: lui [[T10]],0xffff
3361 ; MIPS32: ori [[T10]],[[T10]],0xff
3362 ; MIPS32: and [[T11]],[[T11]],[[T10]]
3363 ; MIPS32: or [[T12]],[[T12]],[[T11]]
3364 ; MIPS32: move [[T10]],a3
3365 ; MIPS32: srl [[T10]],[[T10]],0x10
3366 ; MIPS32: andi [[T10]],[[T10]],0xff
3367 ; MIPS32: move [[T11]],[[T3]]
3368 ; MIPS32: srl [[T11]],[[T11]],0x10
3369 ; MIPS32: andi [[T11]],[[T11]],0xff
3370 ; MIPS32: sll [[T10]],[[T10]],0x18
3371 ; MIPS32: sll [[T11]],[[T11]],0x18
3372 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3373 ; MIPS32: andi [[T11]],[[T11]],0xff
3374 ; MIPS32: sll [[T11]],[[T11]],0x10
3375 ; MIPS32: lui [[T10]],0xff00
3376 ; MIPS32: ori [[T10]],[[T10]],0xffff
3377 ; MIPS32: and [[T12]],[[T12]],[[T10]]
3378 ; MIPS32: or [[T11]],[[T11]],[[T12]]
3379 ; MIPS32: srl [[T13:.*]],a3,0x18
3380 ; MIPS32: srl [[T3]],[[T3]],0x18
3381 ; MIPS32: sll [[T13]],[[T13]],0x18
3017 ; MIPS32: sll [[T3]],[[T3]],0x18 3382 ; MIPS32: sll [[T3]],[[T3]],0x18
3018 ; MIPS32: sll [[T2]],[[T2]],0x18 3383 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
3019 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 3384 ; MIPS32: srl [[T3]],[[T3]],0x18
3020 ; MIPS32: andi [[T2]],[[T2]],0xff 3385 ; MIPS32: sll [[T11]],[[T11]],0x8
3021 ; MIPS32: sll [[T2]],[[T2]],0x10 3386 ; MIPS32: srl [[T11]],[[T11]],0x8
3022 ; MIPS32: lui [[T3]],0xff00 3387 ; MIPS32: or [[T3]],[[T3]],[[T11]]
3023 ; MIPS32: ori [[T3]],[[T3]],0xffff 3388 ; MIPS32: move a0,[[T2]]
3024 ; MIPS32: and [[T5]],[[T5]],[[T3]] 3389 ; MIPS32: move a1,[[T3]]
3025 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3026 ; MIPS32: srl [[T6:.*]],a1,0x18
3027 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3028 ; MIPS32: sll [[T6]],[[T6]],0x18
3029 ; MIPS32: sll [[T7]],[[T7]],0x18
3030 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
3031 ; MIPS32: srl [[T7]],[[T7]],0x18
3032 ; MIPS32: sll [[T2]],[[T2]],0x8
3033 ; MIPS32: srl [[T2]],[[T2]],0x8
3034 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3035 ; MIPS32: andi [[T3]],a2,0xff
3036 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3037 ; MIPS32: sll [[T3]],[[T3]],0x18
3038 ; MIPS32: sll [[T6]],[[T6]],0x18
3039 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3040 ; MIPS32: andi [[T6]],[[T6]],0xff
3041 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3042 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3043 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3044 ; MIPS32: srl [[T3]],a2,0x8
3045 ; MIPS32: andi [[T3]],[[T3]],0xff
3046 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3047 ; MIPS32: andi [[T2]],[[T2]],0xff
3048 ; MIPS32: sll [[T3]],[[T3]],0x18
3049 ; MIPS32: sll [[T2]],[[T2]],0x18
3050 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3051 ; MIPS32: andi [[T2]],[[T2]],0xff
3052 ; MIPS32: sll [[T2]],[[T2]],0x8
3053 ; MIPS32: lui [[T3]],0xffff
3054 ; MIPS32: ori [[T3]],[[T3]],0xff
3055 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3056 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3057 ; MIPS32: srl [[T3]],a2,0x10
3058 ; MIPS32: andi [[T3]],[[T3]],0xff
3059 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3060 ; MIPS32: andi [[T6]],[[T6]],0xff
3061 ; MIPS32: sll [[T3]],[[T3]],0x18
3062 ; MIPS32: sll [[T6]],[[T6]],0x18
3063 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3064 ; MIPS32: andi [[T6]],[[T6]],0xff
3065 ; MIPS32: sll [[T6]],[[T6]],0x10
3066 ; MIPS32: lui [[T3]],0xff00
3067 ; MIPS32: ori [[T3]],[[T3]],0xffff
3068 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3069 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3070 ; MIPS32: srl [[T9:.*]],a2,0x18
3071 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3072 ; MIPS32: sll [[T9]],[[T9]],0x18
3073 ; MIPS32: sll [[T10]],[[T10]],0x18
3074 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
3075 ; MIPS32: srl [[T10]],[[T10]],0x18
3076 ; MIPS32: sll [[T6]],[[T6]],0x8
3077 ; MIPS32: srl [[T6]],[[T6]],0x8
3078 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3079 ; MIPS32: andi [[T3]],a3,0xff
3080 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3081 ; MIPS32: sll [[T3]],[[T3]],0x18
3082 ; MIPS32: sll [[T6]],[[T6]],0x18
3083 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3084 ; MIPS32: andi [[T6]],[[T6]],0xff
3085 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3086 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3087 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3088 ; MIPS32: srl [[T3]],a3,0x8
3089 ; MIPS32: andi [[T3]],[[T3]],0xff
3090 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3091 ; MIPS32: andi [[T9]],[[T9]],0xff
3092 ; MIPS32: sll [[T3]],[[T3]],0x18
3093 ; MIPS32: sll [[T9]],[[T9]],0x18
3094 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
3095 ; MIPS32: andi [[T9]],[[T9]],0xff
3096 ; MIPS32: sll [[T9]],[[T9]],0x8
3097 ; MIPS32: lui [[T3]],0xffff
3098 ; MIPS32: ori [[T3]],[[T3]],0xff
3099 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3100 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3101 ; MIPS32: srl [[T3]],a3,0x10
3102 ; MIPS32: andi [[T3]],[[T3]],0xff
3103 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3104 ; MIPS32: andi [[T6]],[[T6]],0xff
3105 ; MIPS32: sll [[T3]],[[T3]],0x18
3106 ; MIPS32: sll [[T6]],[[T6]],0x18
3107 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3108 ; MIPS32: andi [[T6]],[[T6]],0xff
3109 ; MIPS32: sll [[T6]],[[T6]],0x10
3110 ; MIPS32: lui [[T3]],0xff00
3111 ; MIPS32: ori [[T3]],[[T3]],0xffff
3112 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3113 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3114 ; MIPS32: srl [[T12:.*]],a3,0x18
3115 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3116 ; MIPS32: sll [[T12]],[[T12]],0x18
3117 ; MIPS32: sll [[T13]],[[T13]],0x18
3118 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
3119 ; MIPS32: srl [[T13]],[[T13]],0x18
3120 ; MIPS32: sll [[T6]],[[T6]],0x8
3121 ; MIPS32: srl [[T6]],[[T6]],0x8
3122 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
3123 } 3390 }
3124 3391
3125 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) { 3392 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) {
3126 entry: 3393 entry:
3127 %res = icmp sle <16 x i8> %a, %b 3394 %res = icmp sle <16 x i8> %a, %b
3128 ret <16 x i1> %res 3395 ret <16 x i1> %res
3129 ; CHECK-LABEL: test_icmp_v16i8_sle 3396 ; CHECK-LABEL: test_icmp_v16i8_sle
3130 ; CHECK: pcmpgtb 3397 ; CHECK: pcmpgtb
3131 ; CHECK: pxor 3398 ; CHECK: pxor
3132 3399
3133 ; MIPS32-LABEL: test_icmp_v16i8_sle 3400 ; MIPS32-LABEL: test_icmp_v16i8_sle
3134 ; MIPS32: lw [[BV_E0:.*]], 3401 ; MIPS32: lw [[T0:.*]],
3135 ; MIPS32: lw [[BV_E1:.*]], 3402 ; MIPS32: lw [[T1:.*]],
3136 ; MIPS32: lw [[BV_E2:.*]], 3403 ; MIPS32: lw [[T2:.*]],
3137 ; MIPS32: lw [[BV_E3:.*]], 3404 ; MIPS32: lw [[T3:.*]],
3138 ; MIPS32: move [[TV_E0:.*]],zero 3405 ; MIPS32: move [[T4:.*]],zero
3139 ; MIPS32: move [[TV_E1:.*]],zero 3406 ; MIPS32: move [[T5:.*]],zero
3140 ; MIPS32: move [[TV_E2:.*]],zero 3407 ; MIPS32: move [[T6:.*]],zero
3141 ; MIPS32: move [[TV_E3:.*]],zero 3408 ; MIPS32: move [[T7:.*]],zero
3142 ; MIPS32: andi [[T0:.*]],a0,0xff 3409 ; MIPS32: move [[T8:.*]],a0
3143 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 3410 ; MIPS32: andi [[T8]],[[T8]],0xff
3411 ; MIPS32: move [[T9:.*]],[[T0]]
3412 ; MIPS32: andi [[T9]],[[T9]],0xff
3413 ; MIPS32: sll [[T8]],[[T8]],0x18
3414 ; MIPS32: sll [[T9]],[[T9]],0x18
3415 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
3416 ; MIPS32: xori [[T9]],[[T9]],0x1
3417 ; MIPS32: andi [[T9]],[[T9]],0xff
3418 ; MIPS32: srl [[T4]],[[T4]],0x8
3419 ; MIPS32: sll [[T4]],[[T4]],0x8
3420 ; MIPS32: or [[T9]],[[T9]],[[T4]]
3421 ; MIPS32: move [[T4]],a0
3422 ; MIPS32: srl [[T4]],[[T4]],0x8
3423 ; MIPS32: andi [[T4]],[[T4]],0xff
3424 ; MIPS32: move [[T8]],[[T0]]
3425 ; MIPS32: srl [[T8]],[[T8]],0x8
3426 ; MIPS32: andi [[T8]],[[T8]],0xff
3427 ; MIPS32: sll [[T4]],[[T4]],0x18
3428 ; MIPS32: sll [[T8]],[[T8]],0x18
3429 ; MIPS32: slt [[T8]],[[T8]],[[T4]]
3430 ; MIPS32: xori [[T8]],[[T8]],0x1
3431 ; MIPS32: andi [[T8]],[[T8]],0xff
3432 ; MIPS32: sll [[T8]],[[T8]],0x8
3433 ; MIPS32: lui [[T4]],0xffff
3434 ; MIPS32: ori [[T4]],[[T4]],0xff
3435 ; MIPS32: and [[T9]],[[T9]],[[T4]]
3436 ; MIPS32: or [[T8]],[[T8]],[[T9]]
3437 ; MIPS32: move [[T4]],a0
3438 ; MIPS32: srl [[T4]],[[T4]],0x10
3439 ; MIPS32: andi [[T4]],[[T4]],0xff
3440 ; MIPS32: move [[T9]],[[T0]]
3441 ; MIPS32: srl [[T9]],[[T9]],0x10
3442 ; MIPS32: andi [[T9]],[[T9]],0xff
3443 ; MIPS32: sll [[T4]],[[T4]],0x18
3444 ; MIPS32: sll [[T9]],[[T9]],0x18
3445 ; MIPS32: slt [[T9]],[[T9]],[[T4]]
3446 ; MIPS32: xori [[T9]],[[T9]],0x1
3447 ; MIPS32: andi [[T9]],[[T9]],0xff
3448 ; MIPS32: sll [[T9]],[[T9]],0x10
3449 ; MIPS32: lui [[T4]],0xff00
3450 ; MIPS32: ori [[T4]],[[T4]],0xffff
3451 ; MIPS32: and [[T8]],[[T8]],[[T4]]
3452 ; MIPS32: or [[T9]],[[T9]],[[T8]]
3453 ; MIPS32: srl [[T10:.*]],a0,0x18
3454 ; MIPS32: srl [[T0]],[[T0]],0x18
3455 ; MIPS32: sll [[T10]],[[T10]],0x18
3144 ; MIPS32: sll [[T0]],[[T0]],0x18 3456 ; MIPS32: sll [[T0]],[[T0]],0x18
3145 ; MIPS32: sll [[T1]],[[T1]],0x18 3457 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
3146 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
3147 ; MIPS32: xori [[T1]],[[T1]],0x1
3148 ; MIPS32: andi [[T1]],[[T1]],0xff
3149 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3150 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3151 ; MIPS32: or [[T1]],[[T1]],[[T2]]
3152 ; MIPS32: srl [[T2]],a0,0x8
3153 ; MIPS32: andi [[T2]],[[T2]],0xff
3154 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
3155 ; MIPS32: andi [[T0]],[[T0]],0xff
3156 ; MIPS32: sll [[T2]],[[T2]],0x18
3157 ; MIPS32: sll [[T0]],[[T0]],0x18
3158 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
3159 ; MIPS32: xori [[T0]],[[T0]],0x1 3458 ; MIPS32: xori [[T0]],[[T0]],0x1
3160 ; MIPS32: andi [[T0]],[[T0]],0xff 3459 ; MIPS32: srl [[T0]],[[T0]],0x18
3161 ; MIPS32: sll [[T0]],[[T0]],0x8 3460 ; MIPS32: sll [[T9]],[[T9]],0x8
3162 ; MIPS32: lui [[T2]],0xffff 3461 ; MIPS32: srl [[T9]],[[T9]],0x8
3163 ; MIPS32: ori [[T2]],[[T2]],0xff 3462 ; MIPS32: or v0,[[T0]],[[T9]]
3164 ; MIPS32: and [[T1]],[[T1]],[[T2]] 3463 ; MIPS32: move [[T10]],a1
3165 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3464 ; MIPS32: andi [[T10]],[[T10]],0xff
3166 ; MIPS32: srl [[T2]],a0,0x10 3465 ; MIPS32: move [[T4]],[[T1]]
3167 ; MIPS32: andi [[T2]],[[T2]],0xff 3466 ; MIPS32: andi [[T4]],[[T4]],0xff
3168 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 3467 ; MIPS32: sll [[T10]],[[T10]],0x18
3169 ; MIPS32: andi [[T1]],[[T1]],0xff 3468 ; MIPS32: sll [[T4]],[[T4]],0x18
3170 ; MIPS32: sll [[T2]],[[T2]],0x18 3469 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3171 ; MIPS32: sll [[T1]],[[T1]],0x18
3172 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
3173 ; MIPS32: xori [[T1]],[[T1]],0x1
3174 ; MIPS32: andi [[T1]],[[T1]],0xff
3175 ; MIPS32: sll [[T1]],[[T1]],0x10
3176 ; MIPS32: lui [[T2]],0xff00
3177 ; MIPS32: ori [[T2]],[[T2]],0xffff
3178 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3179 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3180 ; MIPS32: srl [[T3:.*]],a0,0x18
3181 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3182 ; MIPS32: sll [[T3]],[[T3]],0x18
3183 ; MIPS32: sll [[T4]],[[T4]],0x18
3184 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
3185 ; MIPS32: xori [[T4]],[[T4]],0x1 3470 ; MIPS32: xori [[T4]],[[T4]],0x1
3186 ; MIPS32: srl [[T4]],[[T4]],0x18 3471 ; MIPS32: andi [[T4]],[[T4]],0xff
3187 ; MIPS32: sll [[T1]],[[T1]],0x8 3472 ; MIPS32: srl [[T5]],[[T5]],0x8
3188 ; MIPS32: srl [[T1]],[[T1]],0x8 3473 ; MIPS32: sll [[T5]],[[T5]],0x8
3189 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 3474 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3190 ; MIPS32: andi [[T3]],a1,0xff 3475 ; MIPS32: move [[T10]],a1
3191 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 3476 ; MIPS32: srl [[T10]],[[T10]],0x8
3192 ; MIPS32: sll [[T3]],[[T3]],0x18 3477 ; MIPS32: andi [[T10]],[[T10]],0xff
3193 ; MIPS32: sll [[T2]],[[T2]],0x18 3478 ; MIPS32: move [[T5]],[[T1]]
3194 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 3479 ; MIPS32: srl [[T5]],[[T5]],0x8
3195 ; MIPS32: xori [[T2]],[[T2]],0x1
3196 ; MIPS32: andi [[T2]],[[T2]],0xff
3197 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3198 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3199 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3200 ; MIPS32: srl [[T3]],a1,0x8
3201 ; MIPS32: andi [[T3]],[[T3]],0xff
3202 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3203 ; MIPS32: andi [[T5]],[[T5]],0xff 3480 ; MIPS32: andi [[T5]],[[T5]],0xff
3204 ; MIPS32: sll [[T3]],[[T3]],0x18 3481 ; MIPS32: sll [[T10]],[[T10]],0x18
3205 ; MIPS32: sll [[T5]],[[T5]],0x18 3482 ; MIPS32: sll [[T5]],[[T5]],0x18
3206 ; MIPS32: slt [[T5]],[[T5]],[[T3]] 3483 ; MIPS32: slt [[T5]],[[T5]],[[T10]]
3207 ; MIPS32: xori [[T5]],[[T5]],0x1 3484 ; MIPS32: xori [[T5]],[[T5]],0x1
3208 ; MIPS32: andi [[T5]],[[T5]],0xff 3485 ; MIPS32: andi [[T5]],[[T5]],0xff
3209 ; MIPS32: sll [[T5]],[[T5]],0x8 3486 ; MIPS32: sll [[T5]],[[T5]],0x8
3210 ; MIPS32: lui [[T3]],0xffff 3487 ; MIPS32: lui [[T10]],0xffff
3211 ; MIPS32: ori [[T3]],[[T3]],0xff 3488 ; MIPS32: ori [[T10]],[[T10]],0xff
3212 ; MIPS32: and [[T2]],[[T2]],[[T3]] 3489 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3213 ; MIPS32: or [[T5]],[[T5]],[[T2]] 3490 ; MIPS32: or [[T5]],[[T5]],[[T4]]
3214 ; MIPS32: srl [[T3]],a1,0x10 3491 ; MIPS32: move [[T10]],a1
3215 ; MIPS32: andi [[T3]],[[T3]],0xff 3492 ; MIPS32: srl [[T10]],[[T10]],0x10
3216 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 3493 ; MIPS32: andi [[T10]],[[T10]],0xff
3217 ; MIPS32: andi [[T2]],[[T2]],0xff 3494 ; MIPS32: move [[T4]],[[T1]]
3495 ; MIPS32: srl [[T4]],[[T4]],0x10
3496 ; MIPS32: andi [[T4]],[[T4]],0xff
3497 ; MIPS32: sll [[T10]],[[T10]],0x18
3498 ; MIPS32: sll [[T4]],[[T4]],0x18
3499 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3500 ; MIPS32: xori [[T4]],[[T4]],0x1
3501 ; MIPS32: andi [[T4]],[[T4]],0xff
3502 ; MIPS32: sll [[T4]],[[T4]],0x10
3503 ; MIPS32: lui [[T10]],0xff00
3504 ; MIPS32: ori [[T10]],[[T10]],0xffff
3505 ; MIPS32: and [[T5]],[[T5]],[[T10]]
3506 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3507 ; MIPS32: srl [[T11:.*]],a1,0x18
3508 ; MIPS32: srl [[T1]],[[T1]],0x18
3509 ; MIPS32: sll [[T11]],[[T11]],0x18
3510 ; MIPS32: sll [[T1]],[[T1]],0x18
3511 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
3512 ; MIPS32: xori [[T1]],[[T1]],0x1
3513 ; MIPS32: srl [[T1]],[[T1]],0x18
3514 ; MIPS32: sll [[T4]],[[T4]],0x8
3515 ; MIPS32: srl [[T4]],[[T4]],0x8
3516 ; MIPS32: or v1,[[T1]],[[T4]]
3517 ; MIPS32: move [[T10]],a2
3518 ; MIPS32: andi [[T10]],[[T10]],0xff
3519 ; MIPS32: move [[T11]],[[T2]]
3520 ; MIPS32: andi [[T11]],[[T11]],0xff
3521 ; MIPS32: sll [[T10]],[[T10]],0x18
3522 ; MIPS32: sll [[T11]],[[T11]],0x18
3523 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3524 ; MIPS32: xori [[T11]],[[T11]],0x1
3525 ; MIPS32: andi [[T11]],[[T11]],0xff
3526 ; MIPS32: srl [[T6]],[[T6]],0x8
3527 ; MIPS32: sll [[T6]],[[T6]],0x8
3528 ; MIPS32: or [[T11]],[[T11]],[[T6]]
3529 ; MIPS32: move [[T10]],a2
3530 ; MIPS32: srl [[T10]],[[T10]],0x8
3531 ; MIPS32: andi [[T10]],[[T10]],0xff
3532 ; MIPS32: move [[T4]],[[T2]]
3533 ; MIPS32: srl [[T4]],[[T4]],0x8
3534 ; MIPS32: andi [[T4]],[[T4]],0xff
3535 ; MIPS32: sll [[T10]],[[T10]],0x18
3536 ; MIPS32: sll [[T4]],[[T4]],0x18
3537 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3538 ; MIPS32: xori [[T4]],[[T4]],0x1
3539 ; MIPS32: andi [[T4]],[[T4]],0xff
3540 ; MIPS32: sll [[T4]],[[T4]],0x8
3541 ; MIPS32: lui [[T10]],0xffff
3542 ; MIPS32: ori [[T10]],[[T10]],0xff
3543 ; MIPS32: and [[T11]],[[T11]],[[T10]]
3544 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3545 ; MIPS32: move [[T10]],a2
3546 ; MIPS32: srl [[T10]],[[T10]],0x10
3547 ; MIPS32: andi [[T10]],[[T10]],0xff
3548 ; MIPS32: move [[T11]],[[T2]]
3549 ; MIPS32: srl [[T11]],[[T11]],0x10
3550 ; MIPS32: andi [[T11]],[[T11]],0xff
3551 ; MIPS32: sll [[T10]],[[T10]],0x18
3552 ; MIPS32: sll [[T11]],[[T11]],0x18
3553 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3554 ; MIPS32: xori [[T11]],[[T11]],0x1
3555 ; MIPS32: andi [[T11]],[[T11]],0xff
3556 ; MIPS32: sll [[T11]],[[T11]],0x10
3557 ; MIPS32: lui [[T10]],0xff00
3558 ; MIPS32: ori [[T10]],[[T10]],0xffff
3559 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3560 ; MIPS32: or [[T11]],[[T11]],[[T4]]
3561 ; MIPS32: srl [[T12:.*]],a2,0x18
3562 ; MIPS32: srl [[T2]],[[T2]],0x18
3563 ; MIPS32: sll [[T12]],[[T12]],0x18
3564 ; MIPS32: sll [[T2]],[[T2]],0x18
3565 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
3566 ; MIPS32: xori [[T2]],[[T2]],0x1
3567 ; MIPS32: srl [[T2]],[[T2]],0x18
3568 ; MIPS32: sll [[T11]],[[T11]],0x8
3569 ; MIPS32: srl [[T11]],[[T11]],0x8
3570 ; MIPS32: or [[T2]],[[T2]],[[T11]]
3571 ; MIPS32: move [[T10]],a3
3572 ; MIPS32: andi [[T10]],[[T10]],0xff
3573 ; MIPS32: move [[T11]],[[T3]]
3574 ; MIPS32: andi [[T11]],[[T11]],0xff
3575 ; MIPS32: sll [[T10]],[[T10]],0x18
3576 ; MIPS32: sll [[T11]],[[T11]],0x18
3577 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3578 ; MIPS32: xori [[T11]],[[T11]],0x1
3579 ; MIPS32: andi [[T11]],[[T11]],0xff
3580 ; MIPS32: srl [[T7]],[[T7]],0x8
3581 ; MIPS32: sll [[T7]],[[T7]],0x8
3582 ; MIPS32: or [[T11]],[[T11]],[[T7]]
3583 ; MIPS32: move [[T10]],a3
3584 ; MIPS32: srl [[T10]],[[T10]],0x8
3585 ; MIPS32: andi [[T10]],[[T10]],0xff
3586 ; MIPS32: move [[T12]],[[T3]]
3587 ; MIPS32: srl [[T12]],[[T12]],0x8
3588 ; MIPS32: andi [[T12]],[[T12]],0xff
3589 ; MIPS32: sll [[T10]],[[T10]],0x18
3590 ; MIPS32: sll [[T12]],[[T12]],0x18
3591 ; MIPS32: slt [[T12]],[[T12]],[[T10]]
3592 ; MIPS32: xori [[T12]],[[T12]],0x1
3593 ; MIPS32: andi [[T12]],[[T12]],0xff
3594 ; MIPS32: sll [[T12]],[[T12]],0x8
3595 ; MIPS32: lui [[T10]],0xffff
3596 ; MIPS32: ori [[T10]],[[T10]],0xff
3597 ; MIPS32: and [[T11]],[[T11]],[[T10]]
3598 ; MIPS32: or [[T12]],[[T12]],[[T11]]
3599 ; MIPS32: move [[T10]],a3
3600 ; MIPS32: srl [[T10]],[[T10]],0x10
3601 ; MIPS32: andi [[T10]],[[T10]],0xff
3602 ; MIPS32: move [[T11]],[[T3]]
3603 ; MIPS32: srl [[T11]],[[T11]],0x10
3604 ; MIPS32: andi [[T11]],[[T11]],0xff
3605 ; MIPS32: sll [[T10]],[[T10]],0x18
3606 ; MIPS32: sll [[T11]],[[T11]],0x18
3607 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
3608 ; MIPS32: xori [[T11]],[[T11]],0x1
3609 ; MIPS32: andi [[T11]],[[T11]],0xff
3610 ; MIPS32: sll [[T11]],[[T11]],0x10
3611 ; MIPS32: lui [[T10]],0xff00
3612 ; MIPS32: ori [[T10]],[[T10]],0xffff
3613 ; MIPS32: and [[T12]],[[T12]],[[T10]]
3614 ; MIPS32: or [[T11]],[[T11]],[[T12]]
3615 ; MIPS32: srl [[T13:.*]],a3,0x18
3616 ; MIPS32: srl [[T3]],[[T3]],0x18
3617 ; MIPS32: sll [[T13]],[[T13]],0x18
3218 ; MIPS32: sll [[T3]],[[T3]],0x18 3618 ; MIPS32: sll [[T3]],[[T3]],0x18
3219 ; MIPS32: sll [[T2]],[[T2]],0x18 3619 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
3220 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 3620 ; MIPS32: xori [[T3]],[[T3]],0x1
3221 ; MIPS32: xori [[T2]],[[T2]],0x1 3621 ; MIPS32: srl [[T3]],[[T3]],0x18
3222 ; MIPS32: andi [[T2]],[[T2]],0xff 3622 ; MIPS32: sll [[T11]],[[T11]],0x8
3223 ; MIPS32: sll [[T2]],[[T2]],0x10 3623 ; MIPS32: srl [[T11]],[[T11]],0x8
3224 ; MIPS32: lui [[T3]],0xff00 3624 ; MIPS32: or [[T3]],[[T3]],[[T11]]
3225 ; MIPS32: ori [[T3]],[[T3]],0xffff 3625 ; MIPS32: move a0,[[T2]]
3226 ; MIPS32: and [[T5]],[[T5]],[[T3]] 3626 ; MIPS32: move a1,[[T3]]
3227 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3228 ; MIPS32: srl [[T6:.*]],a1,0x18
3229 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3230 ; MIPS32: sll [[T6]],[[T6]],0x18
3231 ; MIPS32: sll [[T7]],[[T7]],0x18
3232 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
3233 ; MIPS32: xori [[T7]],[[T7]],0x1
3234 ; MIPS32: srl [[T7]],[[T7]],0x18
3235 ; MIPS32: sll [[T2]],[[T2]],0x8
3236 ; MIPS32: srl [[T2]],[[T2]],0x8
3237 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3238 ; MIPS32: andi [[T3]],a2,0xff
3239 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3240 ; MIPS32: sll [[T3]],[[T3]],0x18
3241 ; MIPS32: sll [[T6]],[[T6]],0x18
3242 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3243 ; MIPS32: xori [[T6]],[[T6]],0x1
3244 ; MIPS32: andi [[T6]],[[T6]],0xff
3245 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3246 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3247 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3248 ; MIPS32: srl [[T3]],a2,0x8
3249 ; MIPS32: andi [[T3]],[[T3]],0xff
3250 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3251 ; MIPS32: andi [[T2]],[[T2]],0xff
3252 ; MIPS32: sll [[T3]],[[T3]],0x18
3253 ; MIPS32: sll [[T2]],[[T2]],0x18
3254 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3255 ; MIPS32: xori [[T2]],[[T2]],0x1
3256 ; MIPS32: andi [[T2]],[[T2]],0xff
3257 ; MIPS32: sll [[T2]],[[T2]],0x8
3258 ; MIPS32: lui [[T3]],0xffff
3259 ; MIPS32: ori [[T3]],[[T3]],0xff
3260 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3261 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3262 ; MIPS32: srl [[T3]],a2,0x10
3263 ; MIPS32: andi [[T3]],[[T3]],0xff
3264 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3265 ; MIPS32: andi [[T6]],[[T6]],0xff
3266 ; MIPS32: sll [[T3]],[[T3]],0x18
3267 ; MIPS32: sll [[T6]],[[T6]],0x18
3268 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3269 ; MIPS32: xori [[T6]],[[T6]],0x1
3270 ; MIPS32: andi [[T6]],[[T6]],0xff
3271 ; MIPS32: sll [[T6]],[[T6]],0x10
3272 ; MIPS32: lui [[T3]],0xff00
3273 ; MIPS32: ori [[T3]],[[T3]],0xffff
3274 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3275 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3276 ; MIPS32: srl [[T9:.*]],a2,0x18
3277 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3278 ; MIPS32: sll [[T9]],[[T9]],0x18
3279 ; MIPS32: sll [[T10]],[[T10]],0x18
3280 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
3281 ; MIPS32: xori [[T10]],[[T10]],0x1
3282 ; MIPS32: srl [[T10]],[[T10]],0x18
3283 ; MIPS32: sll [[T6]],[[T6]],0x8
3284 ; MIPS32: srl [[T6]],[[T6]],0x8
3285 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3286 ; MIPS32: andi [[T3]],a3,0xff
3287 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3288 ; MIPS32: sll [[T3]],[[T3]],0x18
3289 ; MIPS32: sll [[T6]],[[T6]],0x18
3290 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3291 ; MIPS32: xori [[T6]],[[T6]],0x1
3292 ; MIPS32: andi [[T6]],[[T6]],0xff
3293 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3294 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3295 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3296 ; MIPS32: srl [[T3]],a3,0x8
3297 ; MIPS32: andi [[T3]],[[T3]],0xff
3298 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3299 ; MIPS32: andi [[T9]],[[T9]],0xff
3300 ; MIPS32: sll [[T3]],[[T3]],0x18
3301 ; MIPS32: sll [[T9]],[[T9]],0x18
3302 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
3303 ; MIPS32: xori [[T9]],[[T9]],0x1
3304 ; MIPS32: andi [[T9]],[[T9]],0xff
3305 ; MIPS32: sll [[T9]],[[T9]],0x8
3306 ; MIPS32: lui [[T3]],0xffff
3307 ; MIPS32: ori [[T3]],[[T3]],0xff
3308 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3309 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3310 ; MIPS32: srl [[T3]],a3,0x10
3311 ; MIPS32: andi [[T3]],[[T3]],0xff
3312 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3313 ; MIPS32: andi [[T6]],[[T6]],0xff
3314 ; MIPS32: sll [[T3]],[[T3]],0x18
3315 ; MIPS32: sll [[T6]],[[T6]],0x18
3316 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3317 ; MIPS32: xori [[T6]],[[T6]],0x1
3318 ; MIPS32: andi [[T6]],[[T6]],0xff
3319 ; MIPS32: sll [[T6]],[[T6]],0x10
3320 ; MIPS32: lui [[T3]],0xff00
3321 ; MIPS32: ori [[T3]],[[T3]],0xffff
3322 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3323 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3324 ; MIPS32: srl [[T12:.*]],a3,0x18
3325 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3326 ; MIPS32: sll [[T12]],[[T12]],0x18
3327 ; MIPS32: sll [[T13]],[[T13]],0x18
3328 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
3329 ; MIPS32: xori [[T13]],[[T13]],0x1
3330 ; MIPS32: srl [[T13]],[[T13]],0x18
3331 ; MIPS32: sll [[T6]],[[T6]],0x8
3332 ; MIPS32: srl [[T6]],[[T6]],0x8
3333 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
3334 } 3627 }
3335 3628
3336 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) { 3629 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) {
3337 entry: 3630 entry:
3338 %res = icmp slt <16 x i8> %a, %b 3631 %res = icmp slt <16 x i8> %a, %b
3339 ret <16 x i1> %res 3632 ret <16 x i1> %res
3340 ; CHECK-LABEL: test_icmp_v16i8_slt 3633 ; CHECK-LABEL: test_icmp_v16i8_slt
3341 ; CHECK: pcmpgtb 3634 ; CHECK: pcmpgtb
3342 3635
3343 ; MIPS32-LABEL: test_icmp_v16i8_slt 3636 ; MIPS32-LABEL: test_icmp_v16i8_slt
3344 ; MIPS32: lw [[BV_E0:.*]], 3637 ; MIPS32: lw [[T0:.*]],
3345 ; MIPS32: lw [[BV_E1:.*]], 3638 ; MIPS32: lw [[T1:.*]],
3346 ; MIPS32: lw [[BV_E2:.*]], 3639 ; MIPS32: lw [[T2:.*]],
3347 ; MIPS32: lw [[BV_E3:.*]], 3640 ; MIPS32: lw [[T3:.*]],
3348 ; MIPS32: move [[TV_E0:.*]],zero 3641 ; MIPS32: move [[T4:.*]],zero
3349 ; MIPS32: move [[TV_E1:.*]],zero 3642 ; MIPS32: move [[T5:.*]],zero
3350 ; MIPS32: move [[TV_E2:.*]],zero 3643 ; MIPS32: move [[T6:.*]],zero
3351 ; MIPS32: move [[TV_E3:.*]],zero 3644 ; MIPS32: move [[T7:.*]],zero
3352 ; MIPS32: andi [[T0:.*]],a0,0xff 3645 ; MIPS32: move [[T8:.*]],a0
3353 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 3646 ; MIPS32: andi [[T8]],[[T8]],0xff
3354 ; MIPS32: sll [[T0]],[[T0]],0x18 3647 ; MIPS32: move [[T9:.*]],[[T0]]
3355 ; MIPS32: sll [[T1]],[[T1]],0x18 3648 ; MIPS32: andi [[T9]],[[T9]],0xff
3356 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 3649 ; MIPS32: sll [[T8]],[[T8]],0x18
3357 ; MIPS32: andi [[T0]],[[T0]],0xff 3650 ; MIPS32: sll [[T9]],[[T9]],0x18
3358 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 3651 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
3359 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 3652 ; MIPS32: andi [[T8]],[[T8]],0xff
3360 ; MIPS32: or [[T0]],[[T0]],[[T2]] 3653 ; MIPS32: srl [[T4]],[[T4]],0x8
3361 ; MIPS32: srl [[T2]],a0,0x8 3654 ; MIPS32: sll [[T4]],[[T4]],0x8
3362 ; MIPS32: andi [[T2]],[[T2]],0xff 3655 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3363 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 3656 ; MIPS32: move [[T4]],a0
3364 ; MIPS32: andi [[T1]],[[T1]],0xff 3657 ; MIPS32: srl [[T4]],[[T4]],0x8
3365 ; MIPS32: sll [[T2]],[[T2]],0x18 3658 ; MIPS32: andi [[T4]],[[T4]],0xff
3366 ; MIPS32: sll [[T1]],[[T1]],0x18 3659 ; MIPS32: move [[T9]],[[T0]]
3367 ; MIPS32: slt [[T2]],[[T2]],[[T1]] 3660 ; MIPS32: srl [[T9]],[[T9]],0x8
3368 ; MIPS32: andi [[T2]],[[T2]],0xff 3661 ; MIPS32: andi [[T9]],[[T9]],0xff
3369 ; MIPS32: sll [[T2]],[[T2]],0x8 3662 ; MIPS32: sll [[T4]],[[T4]],0x18
3370 ; MIPS32: lui [[T1]],0xffff 3663 ; MIPS32: sll [[T9]],[[T9]],0x18
3371 ; MIPS32: ori [[T1]],[[T1]],0xff 3664 ; MIPS32: slt [[T4]],[[T4]],[[T9]]
3372 ; MIPS32: and [[T0]],[[T0]],[[T1]] 3665 ; MIPS32: andi [[T4]],[[T4]],0xff
3373 ; MIPS32: or [[T2]],[[T2]],[[T0]] 3666 ; MIPS32: sll [[T4]],[[T4]],0x8
3374 ; MIPS32: srl [[T0]],a0,0x10 3667 ; MIPS32: lui [[T9]],0xffff
3375 ; MIPS32: andi [[T0]],[[T0]],0xff 3668 ; MIPS32: ori [[T9]],[[T9]],0xff
3376 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 3669 ; MIPS32: and [[T8]],[[T8]],[[T9]]
3377 ; MIPS32: andi [[T1]],[[T1]],0xff 3670 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3378 ; MIPS32: sll [[T0]],[[T0]],0x18 3671 ; MIPS32: move [[T8]],a0
3379 ; MIPS32: sll [[T1]],[[T1]],0x18 3672 ; MIPS32: srl [[T8]],[[T8]],0x10
3380 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 3673 ; MIPS32: andi [[T8]],[[T8]],0xff
3674 ; MIPS32: move [[T9]],[[T0]]
3675 ; MIPS32: srl [[T9]],[[T9]],0x10
3676 ; MIPS32: andi [[T9]],[[T9]],0xff
3677 ; MIPS32: sll [[T8]],[[T8]],0x18
3678 ; MIPS32: sll [[T9]],[[T9]],0x18
3679 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
3680 ; MIPS32: andi [[T8]],[[T8]],0xff
3681 ; MIPS32: sll [[T8]],[[T8]],0x10
3682 ; MIPS32: lui [[T9]],0xff00
3683 ; MIPS32: ori [[T9]],[[T9]],0xffff
3684 ; MIPS32: and [[T4]],[[T4]],[[T9]]
3685 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3686 ; MIPS32: srl [[T10:.*]],a0,0x18
3687 ; MIPS32: srl [[T0]],[[T0]],0x18
3688 ; MIPS32: sll [[T10]],[[T10]],0x18
3689 ; MIPS32: sll [[T0]],[[T0]],0x18
3690 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
3691 ; MIPS32: srl [[T10]],[[T10]],0x18
3692 ; MIPS32: sll [[T8]],[[T8]],0x8
3693 ; MIPS32: srl [[T8]],[[T8]],0x8
3694 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3695 ; MIPS32: move [[T0]],a1
3696 ; MIPS32: andi [[T0]],[[T0]],0xff
3697 ; MIPS32: move [[T4]],[[T1]]
3698 ; MIPS32: andi [[T4]],[[T4]],0xff
3699 ; MIPS32: sll [[T0]],[[T0]],0x18
3700 ; MIPS32: sll [[T4]],[[T4]],0x18
3701 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
3702 ; MIPS32: andi [[T0]],[[T0]],0xff
3703 ; MIPS32: srl [[T5]],[[T5]],0x8
3704 ; MIPS32: sll [[T5]],[[T5]],0x8
3705 ; MIPS32: or [[T0]],[[T0]],[[T5]]
3706 ; MIPS32: move [[T4]],a1
3707 ; MIPS32: srl [[T4]],[[T4]],0x8
3708 ; MIPS32: andi [[T4]],[[T4]],0xff
3709 ; MIPS32: move [[T5]],[[T1]]
3710 ; MIPS32: srl [[T5]],[[T5]],0x8
3711 ; MIPS32: andi [[T5]],[[T5]],0xff
3712 ; MIPS32: sll [[T4]],[[T4]],0x18
3713 ; MIPS32: sll [[T5]],[[T5]],0x18
3714 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
3715 ; MIPS32: andi [[T4]],[[T4]],0xff
3716 ; MIPS32: sll [[T4]],[[T4]],0x8
3717 ; MIPS32: lui [[T5]],0xffff
3718 ; MIPS32: ori [[T5]],[[T5]],0xff
3719 ; MIPS32: and [[T0]],[[T0]],[[T5]]
3720 ; MIPS32: or [[T4]],[[T4]],[[T0]]
3721 ; MIPS32: move [[T0]],a1
3722 ; MIPS32: srl [[T0]],[[T0]],0x10
3723 ; MIPS32: andi [[T0]],[[T0]],0xff
3724 ; MIPS32: move [[T5]],[[T1]]
3725 ; MIPS32: srl [[T5]],[[T5]],0x10
3726 ; MIPS32: andi [[T5]],[[T5]],0xff
3727 ; MIPS32: sll [[T0]],[[T0]],0x18
3728 ; MIPS32: sll [[T5]],[[T5]],0x18
3729 ; MIPS32: slt [[T0]],[[T0]],[[T5]]
3381 ; MIPS32: andi [[T0]],[[T0]],0xff 3730 ; MIPS32: andi [[T0]],[[T0]],0xff
3382 ; MIPS32: sll [[T0]],[[T0]],0x10 3731 ; MIPS32: sll [[T0]],[[T0]],0x10
3383 ; MIPS32: lui [[T1]],0xff00 3732 ; MIPS32: lui [[T5]],0xff00
3384 ; MIPS32: ori [[T1]],[[T1]],0xffff 3733 ; MIPS32: ori [[T5]],[[T5]],0xffff
3385 ; MIPS32: and [[T2]],[[T2]],[[T1]] 3734 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3386 ; MIPS32: or [[T0]],[[T0]],[[T2]] 3735 ; MIPS32: or [[T0]],[[T0]],[[T4]]
3387 ; MIPS32: srl [[T3:.*]],a0,0x18 3736 ; MIPS32: srl [[T11:.*]],a1,0x18
3388 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 3737 ; MIPS32: srl [[T1]],[[T1]],0x18
3389 ; MIPS32: sll [[T3]],[[T3]],0x18 3738 ; MIPS32: sll [[T11]],[[T11]],0x18
3390 ; MIPS32: sll [[T4]],[[T4]],0x18 3739 ; MIPS32: sll [[T1]],[[T1]],0x18
3391 ; MIPS32: slt [[T3]],[[T3]],[[T4]] 3740 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
3392 ; MIPS32: srl [[T3]],[[T3]],0x18 3741 ; MIPS32: srl [[T11]],[[T11]],0x18
3393 ; MIPS32: sll [[T0]],[[T0]],0x8 3742 ; MIPS32: sll [[T0]],[[T0]],0x8
3394 ; MIPS32: srl [[T0]],[[T0]],0x8 3743 ; MIPS32: srl [[T0]],[[T0]],0x8
3395 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 3744 ; MIPS32: or [[T11]],[[T11]],[[T0]]
3396 ; MIPS32: andi [[T4]],a1,0xff 3745 ; MIPS32: move [[T0]],a2
3397 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 3746 ; MIPS32: andi [[T0]],[[T0]],0xff
3398 ; MIPS32: sll [[T4]],[[T4]],0x18 3747 ; MIPS32: move [[T1]],[[T2]]
3748 ; MIPS32: andi [[T1]],[[T1]],0xff
3749 ; MIPS32: sll [[T0]],[[T0]],0x18
3750 ; MIPS32: sll [[T1]],[[T1]],0x18
3751 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
3752 ; MIPS32: andi [[T0]],[[T0]],0xff
3753 ; MIPS32: srl [[T6]],[[T6]],0x8
3754 ; MIPS32: sll [[T6]],[[T6]],0x8
3755 ; MIPS32: or [[T0]],[[T0]],[[T6]]
3756 ; MIPS32: move [[T1]],a2
3757 ; MIPS32: srl [[T1]],[[T1]],0x8
3758 ; MIPS32: andi [[T1]],[[T1]],0xff
3759 ; MIPS32: move [[T4]],[[T2]]
3760 ; MIPS32: srl [[T4]],[[T4]],0x8
3761 ; MIPS32: andi [[T4]],[[T4]],0xff
3762 ; MIPS32: sll [[T1]],[[T1]],0x18
3763 ; MIPS32: sll [[T4]],[[T4]],0x18
3764 ; MIPS32: slt [[T1]],[[T1]],[[T4]]
3765 ; MIPS32: andi [[T1]],[[T1]],0xff
3766 ; MIPS32: sll [[T1]],[[T1]],0x8
3767 ; MIPS32: lui [[T4]],0xffff
3768 ; MIPS32: ori [[T4]],[[T4]],0xff
3769 ; MIPS32: and [[T0]],[[T0]],[[T4]]
3770 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3771 ; MIPS32: move [[T0]],a2
3772 ; MIPS32: srl [[T0]],[[T0]],0x10
3773 ; MIPS32: andi [[T0]],[[T0]],0xff
3774 ; MIPS32: move [[T4]],[[T2]]
3775 ; MIPS32: srl [[T4]],[[T4]],0x10
3776 ; MIPS32: andi [[T4]],[[T4]],0xff
3777 ; MIPS32: sll [[T0]],[[T0]],0x18
3778 ; MIPS32: sll [[T4]],[[T4]],0x18
3779 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
3780 ; MIPS32: andi [[T0]],[[T0]],0xff
3781 ; MIPS32: sll [[T0]],[[T0]],0x10
3782 ; MIPS32: lui [[T4]],0xff00
3783 ; MIPS32: ori [[T4]],[[T4]],0xffff
3784 ; MIPS32: and [[T1]],[[T1]],[[T4]]
3785 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3786 ; MIPS32: srl [[T12:.*]],a2,0x18
3787 ; MIPS32: srl [[T2]],[[T2]],0x18
3788 ; MIPS32: sll [[T12]],[[T12]],0x18
3399 ; MIPS32: sll [[T2]],[[T2]],0x18 3789 ; MIPS32: sll [[T2]],[[T2]],0x18
3400 ; MIPS32: slt [[T4]],[[T4]],[[T2]] 3790 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
3401 ; MIPS32: andi [[T4]],[[T4]],0xff 3791 ; MIPS32: srl [[T12]],[[T12]],0x18
3402 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 3792 ; MIPS32: sll [[T0]],[[T0]],0x8
3403 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 3793 ; MIPS32: srl [[T0]],[[T0]],0x8
3404 ; MIPS32: or [[T4]],[[T4]],[[T5]] 3794 ; MIPS32: or [[T12]],[[T12]],[[T0]]
3405 ; MIPS32: srl [[T2]],a1,0x8 3795 ; MIPS32: move [[T0]],a3
3796 ; MIPS32: andi [[T0]],[[T0]],0xff
3797 ; MIPS32: move [[T1]],[[T3]]
3798 ; MIPS32: andi [[T1]],[[T1]],0xff
3799 ; MIPS32: sll [[T0]],[[T0]],0x18
3800 ; MIPS32: sll [[T1]],[[T1]],0x18
3801 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
3802 ; MIPS32: andi [[T0]],[[T0]],0xff
3803 ; MIPS32: srl [[T7]],[[T7]],0x8
3804 ; MIPS32: sll [[T7]],[[T7]],0x8
3805 ; MIPS32: or [[T0]],[[T0]],[[T7]]
3806 ; MIPS32: move [[T1]],a3
3807 ; MIPS32: srl [[T1]],[[T1]],0x8
3808 ; MIPS32: andi [[T1]],[[T1]],0xff
3809 ; MIPS32: move [[T2]],[[T3]]
3810 ; MIPS32: srl [[T2]],[[T2]],0x8
3406 ; MIPS32: andi [[T2]],[[T2]],0xff 3811 ; MIPS32: andi [[T2]],[[T2]],0xff
3407 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 3812 ; MIPS32: sll [[T1]],[[T1]],0x18
3408 ; MIPS32: andi [[T5]],[[T5]],0xff
3409 ; MIPS32: sll [[T2]],[[T2]],0x18 3813 ; MIPS32: sll [[T2]],[[T2]],0x18
3410 ; MIPS32: sll [[T5]],[[T5]],0x18 3814 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
3411 ; MIPS32: slt [[T2]],[[T2]],[[T5]] 3815 ; MIPS32: andi [[T1]],[[T1]],0xff
3412 ; MIPS32: andi [[T2]],[[T2]],0xff 3816 ; MIPS32: sll [[T1]],[[T1]],0x8
3413 ; MIPS32: sll [[T2]],[[T2]],0x8
3414 ; MIPS32: lui [[T5]],0xffff
3415 ; MIPS32: ori [[T5]],[[T5]],0xff
3416 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3417 ; MIPS32: or [[T2]],[[T2]],[[T4]]
3418 ; MIPS32: srl [[T4]],a1,0x10
3419 ; MIPS32: andi [[T4]],[[T4]],0xff
3420 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
3421 ; MIPS32: andi [[T5]],[[T5]],0xff
3422 ; MIPS32: sll [[T4]],[[T4]],0x18
3423 ; MIPS32: sll [[T5]],[[T5]],0x18
3424 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
3425 ; MIPS32: andi [[T4]],[[T4]],0xff
3426 ; MIPS32: sll [[T4]],[[T4]],0x10
3427 ; MIPS32: lui [[T5]],0xff00
3428 ; MIPS32: ori [[T5]],[[T5]],0xffff
3429 ; MIPS32: and [[T2]],[[T2]],[[T5]]
3430 ; MIPS32: or [[T4]],[[T4]],[[T2]]
3431 ; MIPS32: srl [[T6:.*]],a1,0x18
3432 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3433 ; MIPS32: sll [[T6]],[[T6]],0x18
3434 ; MIPS32: sll [[T7]],[[T7]],0x18
3435 ; MIPS32: slt [[T6]],[[T6]],[[T7]]
3436 ; MIPS32: srl [[T6]],[[T6]],0x18
3437 ; MIPS32: sll [[T4]],[[T4]],0x8
3438 ; MIPS32: srl [[T4]],[[T4]],0x8
3439 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
3440 ; MIPS32: andi [[T4]],a2,0xff
3441 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
3442 ; MIPS32: sll [[T4]],[[T4]],0x18
3443 ; MIPS32: sll [[T7]],[[T7]],0x18
3444 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
3445 ; MIPS32: andi [[T4]],[[T4]],0xff
3446 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3447 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3448 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3449 ; MIPS32: srl [[T7]],a2,0x8
3450 ; MIPS32: andi [[T7]],[[T7]],0xff
3451 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3452 ; MIPS32: andi [[T2]],[[T2]],0xff
3453 ; MIPS32: sll [[T7]],[[T7]],0x18
3454 ; MIPS32: sll [[T2]],[[T2]],0x18
3455 ; MIPS32: slt [[T7]],[[T7]],[[T2]]
3456 ; MIPS32: andi [[T7]],[[T7]],0xff
3457 ; MIPS32: sll [[T7]],[[T7]],0x8
3458 ; MIPS32: lui [[T2]],0xffff 3817 ; MIPS32: lui [[T2]],0xffff
3459 ; MIPS32: ori [[T2]],[[T2]],0xff 3818 ; MIPS32: ori [[T2]],[[T2]],0xff
3460 ; MIPS32: and [[T4]],[[T4]],[[T2]] 3819 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3461 ; MIPS32: or [[T7]],[[T7]],[[T4]] 3820 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3462 ; MIPS32: srl [[T4]],a2,0x10 3821 ; MIPS32: move [[T0]],a3
3463 ; MIPS32: andi [[T4]],[[T4]],0xff 3822 ; MIPS32: srl [[T0]],[[T0]],0x10
3464 ; MIPS32: srl [[T2]],[[BV_E2]],0x10 3823 ; MIPS32: andi [[T0]],[[T0]],0xff
3824 ; MIPS32: move [[T2]],[[T3]]
3825 ; MIPS32: srl [[T2]],[[T2]],0x10
3465 ; MIPS32: andi [[T2]],[[T2]],0xff 3826 ; MIPS32: andi [[T2]],[[T2]],0xff
3466 ; MIPS32: sll [[T4]],[[T4]],0x18 3827 ; MIPS32: sll [[T0]],[[T0]],0x18
3467 ; MIPS32: sll [[T2]],[[T2]],0x18 3828 ; MIPS32: sll [[T2]],[[T2]],0x18
3468 ; MIPS32: slt [[T4]],[[T4]],[[T2]] 3829 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
3469 ; MIPS32: andi [[T4]],[[T4]],0xff 3830 ; MIPS32: andi [[T0]],[[T0]],0xff
3470 ; MIPS32: sll [[T4]],[[T4]],0x10 3831 ; MIPS32: sll [[T0]],[[T0]],0x10
3471 ; MIPS32: lui [[T2]],0xff00 3832 ; MIPS32: lui [[T2]],0xff00
3472 ; MIPS32: ori [[T2]],[[T2]],0xffff 3833 ; MIPS32: ori [[T2]],[[T2]],0xffff
3473 ; MIPS32: and [[T7]],[[T7]],[[T2]] 3834 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3474 ; MIPS32: or [[T4]],[[T4]],[[T7]] 3835 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3475 ; MIPS32: srl [[T9:.*]],a2,0x18 3836 ; MIPS32: srl [[T13:.*]],a3,0x18
3476 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 3837 ; MIPS32: srl [[T3]],[[T3]],0x18
3477 ; MIPS32: sll [[T9]],[[T9]],0x18
3478 ; MIPS32: sll [[T10]],[[T10]],0x18
3479 ; MIPS32: slt [[T9]],[[T9]],[[T10]]
3480 ; MIPS32: srl [[T9]],[[T9]],0x18
3481 ; MIPS32: sll [[T4]],[[T4]],0x8
3482 ; MIPS32: srl [[T4]],[[T4]],0x8
3483 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
3484 ; MIPS32: andi [[T4]],a3,0xff
3485 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
3486 ; MIPS32: sll [[T4]],[[T4]],0x18
3487 ; MIPS32: sll [[T7]],[[T7]],0x18
3488 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
3489 ; MIPS32: andi [[T4]],[[T4]],0xff
3490 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3491 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3492 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3493 ; MIPS32: srl [[T7]],a3,0x8
3494 ; MIPS32: andi [[T7]],[[T7]],0xff
3495 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
3496 ; MIPS32: andi [[T10]],[[T10]],0xff
3497 ; MIPS32: sll [[T7]],[[T7]],0x18
3498 ; MIPS32: sll [[T10]],[[T10]],0x18
3499 ; MIPS32: slt [[T7]],[[T7]],[[T10]]
3500 ; MIPS32: andi [[T7]],[[T7]],0xff
3501 ; MIPS32: sll [[T7]],[[T7]],0x8
3502 ; MIPS32: lui [[T10]],0xffff
3503 ; MIPS32: ori [[T10]],[[T10]],0xff
3504 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3505 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3506 ; MIPS32: srl [[T4]],a3,0x10
3507 ; MIPS32: andi [[T4]],[[T4]],0xff
3508 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
3509 ; MIPS32: andi [[T10]],[[T10]],0xff
3510 ; MIPS32: sll [[T4]],[[T4]],0x18
3511 ; MIPS32: sll [[T10]],[[T10]],0x18
3512 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3513 ; MIPS32: andi [[T4]],[[T4]],0xff
3514 ; MIPS32: sll [[T4]],[[T4]],0x10
3515 ; MIPS32: lui [[T10]],0xff00
3516 ; MIPS32: ori [[T10]],[[T10]],0xffff
3517 ; MIPS32: and [[T7]],[[T7]],[[T10]]
3518 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3519 ; MIPS32: srl [[T12:.*]],a3,0x18
3520 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3521 ; MIPS32: sll [[T12]],[[T12]],0x18
3522 ; MIPS32: sll [[T13]],[[T13]],0x18 3838 ; MIPS32: sll [[T13]],[[T13]],0x18
3523 ; MIPS32: slt [[T12]],[[T12]],[[T13]] 3839 ; MIPS32: sll [[T3]],[[T3]],0x18
3524 ; MIPS32: srl [[T12]],[[T12]],0x18 3840 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
3525 ; MIPS32: sll [[T4]],[[T4]],0x8 3841 ; MIPS32: srl [[T13]],[[T13]],0x18
3526 ; MIPS32: srl [[T4]],[[T4]],0x8 3842 ; MIPS32: sll [[T0]],[[T0]],0x8
3527 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 3843 ; MIPS32: srl [[T0]],[[T0]],0x8
3844 ; MIPS32: or [[T13]],[[T13]],[[T0]]
3845 ; MIPS32: move v0,[[T10]]
3846 ; MIPS32: move v1,[[T11]]
3847 ; MIPS32: move a0,[[T12]]
3848 ; MIPS32: move a1,[[T13]]
3528 } 3849 }
3529 3850
3530 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) { 3851 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) {
3531 entry: 3852 entry:
3532 %res = icmp uge <16 x i8> %a, %b 3853 %res = icmp uge <16 x i8> %a, %b
3533 ret <16 x i1> %res 3854 ret <16 x i1> %res
3534 ; CHECK-LABEL: test_icmp_v16i8_uge 3855 ; CHECK-LABEL: test_icmp_v16i8_uge
3535 ; CHECK: pxor 3856 ; CHECK: pxor
3536 ; CHECK: pcmpgtb 3857 ; CHECK: pcmpgtb
3537 ; CHECK: pxor 3858 ; CHECK: pxor
3538 3859
3539 ; MIPS32-LABEL: test_icmp_v16i8_uge 3860 ; MIPS32-LABEL: test_icmp_v16i8_uge
3540 ; MIPS32: lw [[BV_E0:.*]], 3861 ; MIPS32: lw [[T0:.*]],
3541 ; MIPS32: lw [[BV_E1:.*]], 3862 ; MIPS32: lw [[T1:.*]],
3542 ; MIPS32: lw [[BV_E2:.*]], 3863 ; MIPS32: lw [[T2:.*]],
3543 ; MIPS32: lw [[BV_E3:.*]], 3864 ; MIPS32: lw [[T3:.*]],
3544 ; MIPS32: move [[TV_E0:.*]],zero 3865 ; MIPS32: move [[T4:.*]],zero
3545 ; MIPS32: move [[TV_E1:.*]],zero 3866 ; MIPS32: move [[T5:.*]],zero
3546 ; MIPS32: move [[TV_E2:.*]],zero 3867 ; MIPS32: move [[T6:.*]],zero
3547 ; MIPS32: move [[TV_E3:.*]],zero 3868 ; MIPS32: move [[T7:.*]],zero
3548 ; MIPS32: andi [[T0:.*]],a0,0xff 3869 ; MIPS32: move [[T8:.*]],a0
3549 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 3870 ; MIPS32: andi [[T8]],[[T8]],0xff
3871 ; MIPS32: move [[T9:.*]],[[T0]]
3872 ; MIPS32: andi [[T9]],[[T9]],0xff
3873 ; MIPS32: sll [[T8]],[[T8]],0x18
3874 ; MIPS32: sll [[T9]],[[T9]],0x18
3875 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
3876 ; MIPS32: xori [[T8]],[[T8]],0x1
3877 ; MIPS32: andi [[T8]],[[T8]],0xff
3878 ; MIPS32: srl [[T4]],[[T4]],0x8
3879 ; MIPS32: sll [[T4]],[[T4]],0x8
3880 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3881 ; MIPS32: move [[T4]],a0
3882 ; MIPS32: srl [[T4]],[[T4]],0x8
3883 ; MIPS32: andi [[T4]],[[T4]],0xff
3884 ; MIPS32: move [[T9]],[[T0]]
3885 ; MIPS32: srl [[T9]],[[T9]],0x8
3886 ; MIPS32: andi [[T9]],[[T9]],0xff
3887 ; MIPS32: sll [[T4]],[[T4]],0x18
3888 ; MIPS32: sll [[T9]],[[T9]],0x18
3889 ; MIPS32: sltu [[T4]],[[T4]],[[T9]]
3890 ; MIPS32: xori [[T4]],[[T4]],0x1
3891 ; MIPS32: andi [[T4]],[[T4]],0xff
3892 ; MIPS32: sll [[T4]],[[T4]],0x8
3893 ; MIPS32: lui [[T9]],0xffff
3894 ; MIPS32: ori [[T9]],[[T9]],0xff
3895 ; MIPS32: and [[T8]],[[T8]],[[T9]]
3896 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3897 ; MIPS32: move [[T8]],a0
3898 ; MIPS32: srl [[T8]],[[T8]],0x10
3899 ; MIPS32: andi [[T8]],[[T8]],0xff
3900 ; MIPS32: move [[T9]],[[T0]]
3901 ; MIPS32: srl [[T9]],[[T9]],0x10
3902 ; MIPS32: andi [[T9]],[[T9]],0xff
3903 ; MIPS32: sll [[T8]],[[T8]],0x18
3904 ; MIPS32: sll [[T9]],[[T9]],0x18
3905 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
3906 ; MIPS32: xori [[T8]],[[T8]],0x1
3907 ; MIPS32: andi [[T8]],[[T8]],0xff
3908 ; MIPS32: sll [[T8]],[[T8]],0x10
3909 ; MIPS32: lui [[T9]],0xff00
3910 ; MIPS32: ori [[T9]],[[T9]],0xffff
3911 ; MIPS32: and [[T4]],[[T4]],[[T9]]
3912 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3913 ; MIPS32: srl [[T10:.*]],a0,0x18
3914 ; MIPS32: srl [[T0]],[[T0]],0x18
3915 ; MIPS32: sll [[T10]],[[T10]],0x18
3916 ; MIPS32: sll [[T0]],[[T0]],0x18
3917 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
3918 ; MIPS32: xori [[T10]],[[T10]],0x1
3919 ; MIPS32: srl [[T10]],[[T10]],0x18
3920 ; MIPS32: sll [[T8]],[[T8]],0x8
3921 ; MIPS32: srl [[T8]],[[T8]],0x8
3922 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3923 ; MIPS32: move [[T0]],a1
3924 ; MIPS32: andi [[T0]],[[T0]],0xff
3925 ; MIPS32: move [[T4]],[[T1]]
3926 ; MIPS32: andi [[T4]],[[T4]],0xff
3927 ; MIPS32: sll [[T0]],[[T0]],0x18
3928 ; MIPS32: sll [[T4]],[[T4]],0x18
3929 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
3930 ; MIPS32: xori [[T0]],[[T0]],0x1
3931 ; MIPS32: andi [[T0]],[[T0]],0xff
3932 ; MIPS32: srl [[T5]],[[T5]],0x8
3933 ; MIPS32: sll [[T5]],[[T5]],0x8
3934 ; MIPS32: or [[T0]],[[T0]],[[T5]]
3935 ; MIPS32: move [[T4]],a1
3936 ; MIPS32: srl [[T4]],[[T4]],0x8
3937 ; MIPS32: andi [[T4]],[[T4]],0xff
3938 ; MIPS32: move [[T5]],[[T1]]
3939 ; MIPS32: srl [[T5]],[[T5]],0x8
3940 ; MIPS32: andi [[T5]],[[T5]],0xff
3941 ; MIPS32: sll [[T4]],[[T4]],0x18
3942 ; MIPS32: sll [[T5]],[[T5]],0x18
3943 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
3944 ; MIPS32: xori [[T4]],[[T4]],0x1
3945 ; MIPS32: andi [[T4]],[[T4]],0xff
3946 ; MIPS32: sll [[T4]],[[T4]],0x8
3947 ; MIPS32: lui [[T5]],0xffff
3948 ; MIPS32: ori [[T5]],[[T5]],0xff
3949 ; MIPS32: and [[T0]],[[T0]],[[T5]]
3950 ; MIPS32: or [[T4]],[[T4]],[[T0]]
3951 ; MIPS32: move [[T0]],a1
3952 ; MIPS32: srl [[T0]],[[T0]],0x10
3953 ; MIPS32: andi [[T0]],[[T0]],0xff
3954 ; MIPS32: move [[T5]],[[T1]]
3955 ; MIPS32: srl [[T5]],[[T5]],0x10
3956 ; MIPS32: andi [[T5]],[[T5]],0xff
3957 ; MIPS32: sll [[T0]],[[T0]],0x18
3958 ; MIPS32: sll [[T5]],[[T5]],0x18
3959 ; MIPS32: sltu [[T0]],[[T0]],[[T5]]
3960 ; MIPS32: xori [[T0]],[[T0]],0x1
3961 ; MIPS32: andi [[T0]],[[T0]],0xff
3962 ; MIPS32: sll [[T0]],[[T0]],0x10
3963 ; MIPS32: lui [[T5]],0xff00
3964 ; MIPS32: ori [[T5]],[[T5]],0xffff
3965 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3966 ; MIPS32: or [[T0]],[[T0]],[[T4]]
3967 ; MIPS32: srl [[T11:.*]],a1,0x18
3968 ; MIPS32: srl [[T1]],[[T1]],0x18
3969 ; MIPS32: sll [[T11]],[[T11]],0x18
3970 ; MIPS32: sll [[T1]],[[T1]],0x18
3971 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
3972 ; MIPS32: xori [[T11]],[[T11]],0x1
3973 ; MIPS32: srl [[T11]],[[T11]],0x18
3974 ; MIPS32: sll [[T0]],[[T0]],0x8
3975 ; MIPS32: srl [[T0]],[[T0]],0x8
3976 ; MIPS32: or [[T11]],[[T11]],[[T0]]
3977 ; MIPS32: move [[T0]],a2
3978 ; MIPS32: andi [[T0]],[[T0]],0xff
3979 ; MIPS32: move [[T1]],[[T2]]
3980 ; MIPS32: andi [[T1]],[[T1]],0xff
3550 ; MIPS32: sll [[T0]],[[T0]],0x18 3981 ; MIPS32: sll [[T0]],[[T0]],0x18
3551 ; MIPS32: sll [[T1]],[[T1]],0x18 3982 ; MIPS32: sll [[T1]],[[T1]],0x18
3552 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 3983 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
3553 ; MIPS32: xori [[T0]],[[T0]],0x1 3984 ; MIPS32: xori [[T0]],[[T0]],0x1
3554 ; MIPS32: andi [[T0]],[[T0]],0xff 3985 ; MIPS32: andi [[T0]],[[T0]],0xff
3555 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 3986 ; MIPS32: srl [[T6]],[[T6]],0x8
3556 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 3987 ; MIPS32: sll [[T6]],[[T6]],0x8
3557 ; MIPS32: or [[T0]],[[T0]],[[T2]] 3988 ; MIPS32: or [[T0]],[[T0]],[[T6]]
3558 ; MIPS32: srl [[T2]],a0,0x8 3989 ; MIPS32: move [[T1]],a2
3559 ; MIPS32: andi [[T2]],[[T2]],0xff 3990 ; MIPS32: srl [[T1]],[[T1]],0x8
3560 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
3561 ; MIPS32: andi [[T1]],[[T1]],0xff 3991 ; MIPS32: andi [[T1]],[[T1]],0xff
3992 ; MIPS32: move [[T4]],[[T2]]
3993 ; MIPS32: srl [[T4]],[[T4]],0x8
3994 ; MIPS32: andi [[T4]],[[T4]],0xff
3995 ; MIPS32: sll [[T1]],[[T1]],0x18
3996 ; MIPS32: sll [[T4]],[[T4]],0x18
3997 ; MIPS32: sltu [[T1]],[[T1]],[[T4]]
3998 ; MIPS32: xori [[T1]],[[T1]],0x1
3999 ; MIPS32: andi [[T1]],[[T1]],0xff
4000 ; MIPS32: sll [[T1]],[[T1]],0x8
4001 ; MIPS32: lui [[T4]],0xffff
4002 ; MIPS32: ori [[T4]],[[T4]],0xff
4003 ; MIPS32: and [[T0]],[[T0]],[[T4]]
4004 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4005 ; MIPS32: move [[T0]],a2
4006 ; MIPS32: srl [[T0]],[[T0]],0x10
4007 ; MIPS32: andi [[T0]],[[T0]],0xff
4008 ; MIPS32: move [[T4]],[[T2]]
4009 ; MIPS32: srl [[T4]],[[T4]],0x10
4010 ; MIPS32: andi [[T4]],[[T4]],0xff
4011 ; MIPS32: sll [[T0]],[[T0]],0x18
4012 ; MIPS32: sll [[T4]],[[T4]],0x18
4013 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
4014 ; MIPS32: xori [[T0]],[[T0]],0x1
4015 ; MIPS32: andi [[T0]],[[T0]],0xff
4016 ; MIPS32: sll [[T0]],[[T0]],0x10
4017 ; MIPS32: lui [[T4]],0xff00
4018 ; MIPS32: ori [[T4]],[[T4]],0xffff
4019 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4020 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4021 ; MIPS32: srl [[T12:.*]],a2,0x18
4022 ; MIPS32: srl [[T2]],[[T2]],0x18
4023 ; MIPS32: sll [[T12]],[[T12]],0x18
3562 ; MIPS32: sll [[T2]],[[T2]],0x18 4024 ; MIPS32: sll [[T2]],[[T2]],0x18
3563 ; MIPS32: sll [[T1]],[[T1]],0x18 4025 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
3564 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 4026 ; MIPS32: xori [[T12]],[[T12]],0x1
3565 ; MIPS32: xori [[T2]],[[T2]],0x1 4027 ; MIPS32: srl [[T12]],[[T12]],0x18
3566 ; MIPS32: andi [[T2]],[[T2]],0xff 4028 ; MIPS32: sll [[T0]],[[T0]],0x8
3567 ; MIPS32: sll [[T2]],[[T2]],0x8 4029 ; MIPS32: srl [[T0]],[[T0]],0x8
3568 ; MIPS32: lui [[T1]],0xffff 4030 ; MIPS32: or [[T12]],[[T12]],[[T0]]
3569 ; MIPS32: ori [[T1]],[[T1]],0xff 4031 ; MIPS32: move [[T0]],a3
3570 ; MIPS32: and [[T0]],[[T0]],[[T1]] 4032 ; MIPS32: andi [[T0]],[[T0]],0xff
3571 ; MIPS32: or [[T2]],[[T2]],[[T0]] 4033 ; MIPS32: move [[T1]],[[T3]]
3572 ; MIPS32: srl [[T0]],a0,0x10
3573 ; MIPS32: andi [[T0]],[[T0]],0xff
3574 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3575 ; MIPS32: andi [[T1]],[[T1]],0xff 4034 ; MIPS32: andi [[T1]],[[T1]],0xff
3576 ; MIPS32: sll [[T0]],[[T0]],0x18 4035 ; MIPS32: sll [[T0]],[[T0]],0x18
3577 ; MIPS32: sll [[T1]],[[T1]],0x18 4036 ; MIPS32: sll [[T1]],[[T1]],0x18
3578 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4037 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
3579 ; MIPS32: xori [[T0]],[[T0]],0x1 4038 ; MIPS32: xori [[T0]],[[T0]],0x1
3580 ; MIPS32: andi [[T0]],[[T0]],0xff 4039 ; MIPS32: andi [[T0]],[[T0]],0xff
4040 ; MIPS32: srl [[T7]],[[T7]],0x8
4041 ; MIPS32: sll [[T7]],[[T7]],0x8
4042 ; MIPS32: or [[T0]],[[T0]],[[T7]]
4043 ; MIPS32: move [[T1]],a3
4044 ; MIPS32: srl [[T1]],[[T1]],0x8
4045 ; MIPS32: andi [[T1]],[[T1]],0xff
4046 ; MIPS32: move [[T2]],[[T3]]
4047 ; MIPS32: srl [[T2]],[[T2]],0x8
4048 ; MIPS32: andi [[T2]],[[T2]],0xff
4049 ; MIPS32: sll [[T1]],[[T1]],0x18
4050 ; MIPS32: sll [[T2]],[[T2]],0x18
4051 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
4052 ; MIPS32: xori [[T1]],[[T1]],0x1
4053 ; MIPS32: andi [[T1]],[[T1]],0xff
4054 ; MIPS32: sll [[T1]],[[T1]],0x8
4055 ; MIPS32: lui [[T2]],0xffff
4056 ; MIPS32: ori [[T2]],[[T2]],0xff
4057 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4058 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4059 ; MIPS32: move [[T0]],a3
4060 ; MIPS32: srl [[T0]],[[T0]],0x10
4061 ; MIPS32: andi [[T0]],[[T0]],0xff
4062 ; MIPS32: move [[T2]],[[T3]]
4063 ; MIPS32: srl [[T2]],[[T2]],0x10
4064 ; MIPS32: andi [[T2]],[[T2]],0xff
4065 ; MIPS32: sll [[T0]],[[T0]],0x18
4066 ; MIPS32: sll [[T2]],[[T2]],0x18
4067 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
4068 ; MIPS32: xori [[T0]],[[T0]],0x1
4069 ; MIPS32: andi [[T0]],[[T0]],0xff
3581 ; MIPS32: sll [[T0]],[[T0]],0x10 4070 ; MIPS32: sll [[T0]],[[T0]],0x10
3582 ; MIPS32: lui [[T1]],0xff00 4071 ; MIPS32: lui [[T2]],0xff00
3583 ; MIPS32: ori [[T1]],[[T1]],0xffff 4072 ; MIPS32: ori [[T2]],[[T2]],0xffff
3584 ; MIPS32: and [[T2]],[[T2]],[[T1]] 4073 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3585 ; MIPS32: or [[T0]],[[T0]],[[T2]] 4074 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3586 ; MIPS32: srl [[T3:.*]],a0,0x18 4075 ; MIPS32: srl [[T13:.*]],a3,0x18
3587 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 4076 ; MIPS32: srl [[T3]],[[T3]],0x18
4077 ; MIPS32: sll [[T13]],[[T13]],0x18
3588 ; MIPS32: sll [[T3]],[[T3]],0x18 4078 ; MIPS32: sll [[T3]],[[T3]],0x18
3589 ; MIPS32: sll [[T4]],[[T4]],0x18 4079 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
3590 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 4080 ; MIPS32: xori [[T13]],[[T13]],0x1
3591 ; MIPS32: xori [[T3]],[[T3]],0x1 4081 ; MIPS32: srl [[T13]],[[T13]],0x18
3592 ; MIPS32: srl [[T3]],[[T3]],0x18
3593 ; MIPS32: sll [[T0]],[[T0]],0x8 4082 ; MIPS32: sll [[T0]],[[T0]],0x8
3594 ; MIPS32: srl [[T0]],[[T0]],0x8 4083 ; MIPS32: srl [[T0]],[[T0]],0x8
3595 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 4084 ; MIPS32: or [[T13]],[[T13]],[[T0]]
3596 ; MIPS32: andi [[T4]],a1,0xff 4085 ; MIPS32: move v0,[[T10]]
3597 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 4086 ; MIPS32: move v1,[[T11]]
3598 ; MIPS32: sll [[T4]],[[T4]],0x18 4087 ; MIPS32: move a0,[[T12]]
3599 ; MIPS32: sll [[T2]],[[T2]],0x18 4088 ; MIPS32: move a1,[[T13]]
3600 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
3601 ; MIPS32: xori [[T4]],[[T4]],0x1
3602 ; MIPS32: andi [[T4]],[[T4]],0xff
3603 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3604 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3605 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3606 ; MIPS32: srl [[T2]],a1,0x8
3607 ; MIPS32: andi [[T2]],[[T2]],0xff
3608 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3609 ; MIPS32: andi [[T5]],[[T5]],0xff
3610 ; MIPS32: sll [[T2]],[[T2]],0x18
3611 ; MIPS32: sll [[T5]],[[T5]],0x18
3612 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
3613 ; MIPS32: xori [[T2]],[[T2]],0x1
3614 ; MIPS32: andi [[T2]],[[T2]],0xff
3615 ; MIPS32: sll [[T2]],[[T2]],0x8
3616 ; MIPS32: lui [[T5]],0xffff
3617 ; MIPS32: ori [[T5]],[[T5]],0xff
3618 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3619 ; MIPS32: or [[T2]],[[T2]],[[T4]]
3620 ; MIPS32: srl [[T4]],a1,0x10
3621 ; MIPS32: andi [[T4]],[[T4]],0xff
3622 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
3623 ; MIPS32: andi [[T5]],[[T5]],0xff
3624 ; MIPS32: sll [[T4]],[[T4]],0x18
3625 ; MIPS32: sll [[T5]],[[T5]],0x18
3626 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
3627 ; MIPS32: xori [[T4]],[[T4]],0x1
3628 ; MIPS32: andi [[T4]],[[T4]],0xff
3629 ; MIPS32: sll [[T4]],[[T4]],0x10
3630 ; MIPS32: lui [[T5]],0xff00
3631 ; MIPS32: ori [[T5]],[[T5]],0xffff
3632 ; MIPS32: and [[T2]],[[T2]],[[T5]]
3633 ; MIPS32: or [[T4]],[[T4]],[[T2]]
3634 ; MIPS32: srl [[T6:.*]],a1,0x18
3635 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3636 ; MIPS32: sll [[T6]],[[T6]],0x18
3637 ; MIPS32: sll [[T7]],[[T7]],0x18
3638 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
3639 ; MIPS32: xori [[T6]],[[T6]],0x1
3640 ; MIPS32: srl [[T6]],[[T6]],0x18
3641 ; MIPS32: sll [[T4]],[[T4]],0x8
3642 ; MIPS32: srl [[T4]],[[T4]],0x8
3643 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
3644 ; MIPS32: andi [[T4]],a2,0xff
3645 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
3646 ; MIPS32: sll [[T4]],[[T4]],0x18
3647 ; MIPS32: sll [[T7]],[[T7]],0x18
3648 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
3649 ; MIPS32: xori [[T4]],[[T4]],0x1
3650 ; MIPS32: andi [[T4]],[[T4]],0xff
3651 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3652 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3653 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3654 ; MIPS32: srl [[T7]],a2,0x8
3655 ; MIPS32: andi [[T7]],[[T7]],0xff
3656 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3657 ; MIPS32: andi [[T2]],[[T2]],0xff
3658 ; MIPS32: sll [[T7]],[[T7]],0x18
3659 ; MIPS32: sll [[T2]],[[T2]],0x18
3660 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
3661 ; MIPS32: xori [[T7]],[[T7]],0x1
3662 ; MIPS32: andi [[T7]],[[T7]],0xff
3663 ; MIPS32: sll [[T7]],[[T7]],0x8
3664 ; MIPS32: lui [[T2]],0xffff
3665 ; MIPS32: ori [[T2]],[[T2]],0xff
3666 ; MIPS32: and [[T4]],[[T4]],[[T2]]
3667 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3668 ; MIPS32: srl [[T4]],a2,0x10
3669 ; MIPS32: andi [[T4]],[[T4]],0xff
3670 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
3671 ; MIPS32: andi [[T2]],[[T2]],0xff
3672 ; MIPS32: sll [[T4]],[[T4]],0x18
3673 ; MIPS32: sll [[T2]],[[T2]],0x18
3674 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
3675 ; MIPS32: xori [[T4]],[[T4]],0x1
3676 ; MIPS32: andi [[T4]],[[T4]],0xff
3677 ; MIPS32: sll [[T4]],[[T4]],0x10
3678 ; MIPS32: lui [[T2]],0xff00
3679 ; MIPS32: ori [[T2]],[[T2]],0xffff
3680 ; MIPS32: and [[T7]],[[T7]],[[T2]]
3681 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3682 ; MIPS32: srl [[T9:.*]],a2,0x18
3683 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3684 ; MIPS32: sll [[T9]],[[T9]],0x18
3685 ; MIPS32: sll [[T10]],[[T10]],0x18
3686 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
3687 ; MIPS32: xori [[T9]],[[T9]],0x1
3688 ; MIPS32: srl [[T9]],[[T9]],0x18
3689 ; MIPS32: sll [[T4]],[[T4]],0x8
3690 ; MIPS32: srl [[T4]],[[T4]],0x8
3691 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
3692 ; MIPS32: andi [[T4]],a3,0xff
3693 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
3694 ; MIPS32: sll [[T4]],[[T4]],0x18
3695 ; MIPS32: sll [[T7]],[[T7]],0x18
3696 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
3697 ; MIPS32: xori [[T4]],[[T4]],0x1
3698 ; MIPS32: andi [[T4]],[[T4]],0xff
3699 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3700 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3701 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3702 ; MIPS32: srl [[T7]],a3,0x8
3703 ; MIPS32: andi [[T7]],[[T7]],0xff
3704 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
3705 ; MIPS32: andi [[T10]],[[T10]],0xff
3706 ; MIPS32: sll [[T7]],[[T7]],0x18
3707 ; MIPS32: sll [[T10]],[[T10]],0x18
3708 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
3709 ; MIPS32: xori [[T7]],[[T7]],0x1
3710 ; MIPS32: andi [[T7]],[[T7]],0xff
3711 ; MIPS32: sll [[T7]],[[T7]],0x8
3712 ; MIPS32: lui [[T10]],0xffff
3713 ; MIPS32: ori [[T10]],[[T10]],0xff
3714 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3715 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3716 ; MIPS32: srl [[T4]],a3,0x10
3717 ; MIPS32: andi [[T4]],[[T4]],0xff
3718 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
3719 ; MIPS32: andi [[T10]],[[T10]],0xff
3720 ; MIPS32: sll [[T4]],[[T4]],0x18
3721 ; MIPS32: sll [[T10]],[[T10]],0x18
3722 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
3723 ; MIPS32: xori [[T4]],[[T4]],0x1
3724 ; MIPS32: andi [[T4]],[[T4]],0xff
3725 ; MIPS32: sll [[T4]],[[T4]],0x10
3726 ; MIPS32: lui [[T10]],0xff00
3727 ; MIPS32: ori [[T10]],[[T10]],0xffff
3728 ; MIPS32: and [[T7]],[[T7]],[[T10]]
3729 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3730 ; MIPS32: srl [[T12:.*]],a3,0x18
3731 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3732 ; MIPS32: sll [[T12]],[[T12]],0x18
3733 ; MIPS32: sll [[T13]],[[T13]],0x18
3734 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
3735 ; MIPS32: xori [[T12]],[[T12]],0x1
3736 ; MIPS32: srl [[T12]],[[T12]],0x18
3737 ; MIPS32: sll [[T4]],[[T4]],0x8
3738 ; MIPS32: srl [[T4]],[[T4]],0x8
3739 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
3740 } 4089 }
3741 4090
3742 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) { 4091 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) {
3743 entry: 4092 entry:
3744 %res = icmp ugt <16 x i8> %a, %b 4093 %res = icmp ugt <16 x i8> %a, %b
3745 ret <16 x i1> %res 4094 ret <16 x i1> %res
3746 ; CHECK-LABEL: test_icmp_v16i8_ugt 4095 ; CHECK-LABEL: test_icmp_v16i8_ugt
3747 ; CHECK: pxor 4096 ; CHECK: pxor
3748 ; CHECK: pcmpgtb 4097 ; CHECK: pcmpgtb
3749 4098
3750 ; MIPS32-LABEL: test_icmp_v16i8_ugt 4099 ; MIPS32-LABEL: test_icmp_v16i8_ugt
3751 ; MIPS32: lw [[BV_E0:.*]], 4100 ; MIPS32: lw [[T0:.*]],
3752 ; MIPS32: lw [[BV_E1:.*]], 4101 ; MIPS32: lw [[T1:.*]],
3753 ; MIPS32: lw [[BV_E2:.*]], 4102 ; MIPS32: lw [[T2:.*]],
3754 ; MIPS32: lw [[BV_E3:.*]], 4103 ; MIPS32: lw [[T3:.*]],
3755 ; MIPS32: move [[TV_E0:.*]],zero 4104 ; MIPS32: move [[T4:.*]],zero
3756 ; MIPS32: move [[TV_E1:.*]],zero 4105 ; MIPS32: move [[T5:.*]],zero
3757 ; MIPS32: move [[TV_E2:.*]],zero 4106 ; MIPS32: move [[T6:.*]],zero
3758 ; MIPS32: move [[TV_E3:.*]],zero 4107 ; MIPS32: move [[T7:.*]],zero
3759 ; MIPS32: andi [[T0:.*]],a0,0xff 4108 ; MIPS32: move [[T8:.*]],a0
3760 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 4109 ; MIPS32: andi [[T8]],[[T8]],0xff
3761 ; MIPS32: sll [[T0]],[[T0]],0x18 4110 ; MIPS32: move [[T9:.*]],[[T0]]
3762 ; MIPS32: sll [[T1]],[[T1]],0x18 4111 ; MIPS32: andi [[T9]],[[T9]],0xff
3763 ; MIPS32: sltu [[T1]],[[T1]],[[T0]] 4112 ; MIPS32: sll [[T8]],[[T8]],0x18
3764 ; MIPS32: andi [[T1]],[[T1]],0xff 4113 ; MIPS32: sll [[T9]],[[T9]],0x18
3765 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 4114 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
3766 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 4115 ; MIPS32: andi [[T9]],[[T9]],0xff
3767 ; MIPS32: or [[T1]],[[T1]],[[T2]] 4116 ; MIPS32: srl [[T4]],[[T4]],0x8
3768 ; MIPS32: srl [[T2]],a0,0x8 4117 ; MIPS32: sll [[T4]],[[T4]],0x8
3769 ; MIPS32: andi [[T2]],[[T2]],0xff 4118 ; MIPS32: or [[T9]],[[T9]],[[T4]]
3770 ; MIPS32: srl [[T0]],[[BV_E0]],0x8 4119 ; MIPS32: move [[T4]],a0
3771 ; MIPS32: andi [[T0]],[[T0]],0xff 4120 ; MIPS32: srl [[T4]],[[T4]],0x8
3772 ; MIPS32: sll [[T2]],[[T2]],0x18 4121 ; MIPS32: andi [[T4]],[[T4]],0xff
3773 ; MIPS32: sll [[T0]],[[T0]],0x18 4122 ; MIPS32: move [[T8]],[[T0]]
3774 ; MIPS32: sltu [[T0]],[[T0]],[[T2]] 4123 ; MIPS32: srl [[T8]],[[T8]],0x8
3775 ; MIPS32: andi [[T0]],[[T0]],0xff 4124 ; MIPS32: andi [[T8]],[[T8]],0xff
3776 ; MIPS32: sll [[T0]],[[T0]],0x8 4125 ; MIPS32: sll [[T4]],[[T4]],0x18
3777 ; MIPS32: lui [[T2]],0xffff 4126 ; MIPS32: sll [[T8]],[[T8]],0x18
3778 ; MIPS32: ori [[T2]],[[T2]],0xff 4127 ; MIPS32: sltu [[T8]],[[T8]],[[T4]]
3779 ; MIPS32: and [[T1]],[[T1]],[[T2]] 4128 ; MIPS32: andi [[T8]],[[T8]],0xff
3780 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4129 ; MIPS32: sll [[T8]],[[T8]],0x8
3781 ; MIPS32: srl [[T2]],a0,0x10 4130 ; MIPS32: lui [[T4]],0xffff
3782 ; MIPS32: andi [[T2]],[[T2]],0xff 4131 ; MIPS32: ori [[T4]],[[T4]],0xff
3783 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 4132 ; MIPS32: and [[T9]],[[T9]],[[T4]]
3784 ; MIPS32: andi [[T1]],[[T1]],0xff 4133 ; MIPS32: or [[T8]],[[T8]],[[T9]]
3785 ; MIPS32: sll [[T2]],[[T2]],0x18 4134 ; MIPS32: move [[T4]],a0
3786 ; MIPS32: sll [[T1]],[[T1]],0x18 4135 ; MIPS32: srl [[T4]],[[T4]],0x10
3787 ; MIPS32: sltu [[T1]],[[T1]],[[T2]] 4136 ; MIPS32: andi [[T4]],[[T4]],0xff
3788 ; MIPS32: andi [[T1]],[[T1]],0xff 4137 ; MIPS32: move [[T9]],[[T0]]
3789 ; MIPS32: sll [[T1]],[[T1]],0x10 4138 ; MIPS32: srl [[T9]],[[T9]],0x10
3790 ; MIPS32: lui [[T2]],0xff00 4139 ; MIPS32: andi [[T9]],[[T9]],0xff
3791 ; MIPS32: ori [[T2]],[[T2]],0xffff 4140 ; MIPS32: sll [[T4]],[[T4]],0x18
3792 ; MIPS32: and [[T0]],[[T0]],[[T2]] 4141 ; MIPS32: sll [[T9]],[[T9]],0x18
3793 ; MIPS32: or [[T1]],[[T1]],[[T0]] 4142 ; MIPS32: sltu [[T9]],[[T9]],[[T4]]
3794 ; MIPS32: srl [[T3:.*]],a0,0x18 4143 ; MIPS32: andi [[T9]],[[T9]],0xff
3795 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 4144 ; MIPS32: sll [[T9]],[[T9]],0x10
3796 ; MIPS32: sll [[T3]],[[T3]],0x18 4145 ; MIPS32: lui [[T4]],0xff00
3797 ; MIPS32: sll [[T4]],[[T4]],0x18 4146 ; MIPS32: ori [[T4]],[[T4]],0xffff
3798 ; MIPS32: sltu [[T4]],[[T4]],[[T3]] 4147 ; MIPS32: and [[T8]],[[T8]],[[T4]]
3799 ; MIPS32: srl [[T4]],[[T4]],0x18 4148 ; MIPS32: or [[T9]],[[T9]],[[T8]]
3800 ; MIPS32: sll [[T1]],[[T1]],0x8 4149 ; MIPS32: srl [[T10:.*]],a0,0x18
3801 ; MIPS32: srl [[T1]],[[T1]],0x8 4150 ; MIPS32: srl [[T0]],[[T0]],0x18
3802 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 4151 ; MIPS32: sll [[T10]],[[T10]],0x18
3803 ; MIPS32: andi [[T3]],a1,0xff 4152 ; MIPS32: sll [[T0]],[[T0]],0x18
3804 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 4153 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
3805 ; MIPS32: sll [[T3]],[[T3]],0x18 4154 ; MIPS32: srl [[T0]],[[T0]],0x18
3806 ; MIPS32: sll [[T2]],[[T2]],0x18 4155 ; MIPS32: sll [[T9]],[[T9]],0x8
3807 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 4156 ; MIPS32: srl [[T9]],[[T9]],0x8
3808 ; MIPS32: andi [[T2]],[[T2]],0xff 4157 ; MIPS32: or v0,[[T0]],[[T9]]
3809 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 4158 ; MIPS32: move [[T10]],a1
3810 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 4159 ; MIPS32: andi [[T10]],[[T10]],0xff
3811 ; MIPS32: or [[T2]],[[T2]],[[T5]] 4160 ; MIPS32: move [[T4]],[[T1]]
3812 ; MIPS32: srl [[T3]],a1,0x8 4161 ; MIPS32: andi [[T4]],[[T4]],0xff
3813 ; MIPS32: andi [[T3]],[[T3]],0xff 4162 ; MIPS32: sll [[T10]],[[T10]],0x18
3814 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 4163 ; MIPS32: sll [[T4]],[[T4]],0x18
4164 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4165 ; MIPS32: andi [[T4]],[[T4]],0xff
4166 ; MIPS32: srl [[T5]],[[T5]],0x8
4167 ; MIPS32: sll [[T5]],[[T5]],0x8
4168 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4169 ; MIPS32: move [[T10]],a1
4170 ; MIPS32: srl [[T10]],[[T10]],0x8
4171 ; MIPS32: andi [[T10]],[[T10]],0xff
4172 ; MIPS32: move [[T5]],[[T1]]
4173 ; MIPS32: srl [[T5]],[[T5]],0x8
3815 ; MIPS32: andi [[T5]],[[T5]],0xff 4174 ; MIPS32: andi [[T5]],[[T5]],0xff
3816 ; MIPS32: sll [[T3]],[[T3]],0x18 4175 ; MIPS32: sll [[T10]],[[T10]],0x18
3817 ; MIPS32: sll [[T5]],[[T5]],0x18 4176 ; MIPS32: sll [[T5]],[[T5]],0x18
3818 ; MIPS32: sltu [[T5]],[[T5]],[[T3]] 4177 ; MIPS32: sltu [[T5]],[[T5]],[[T10]]
3819 ; MIPS32: andi [[T5]],[[T5]],0xff 4178 ; MIPS32: andi [[T5]],[[T5]],0xff
3820 ; MIPS32: sll [[T5]],[[T5]],0x8 4179 ; MIPS32: sll [[T5]],[[T5]],0x8
3821 ; MIPS32: lui [[T3]],0xffff 4180 ; MIPS32: lui [[T10]],0xffff
3822 ; MIPS32: ori [[T3]],[[T3]],0xff 4181 ; MIPS32: ori [[T10]],[[T10]],0xff
3823 ; MIPS32: and [[T2]],[[T2]],[[T3]] 4182 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3824 ; MIPS32: or [[T5]],[[T5]],[[T2]] 4183 ; MIPS32: or [[T5]],[[T5]],[[T4]]
3825 ; MIPS32: srl [[T3]],a1,0x10 4184 ; MIPS32: move [[T10]],a1
3826 ; MIPS32: andi [[T3]],[[T3]],0xff 4185 ; MIPS32: srl [[T10]],[[T10]],0x10
3827 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 4186 ; MIPS32: andi [[T10]],[[T10]],0xff
3828 ; MIPS32: andi [[T2]],[[T2]],0xff 4187 ; MIPS32: move [[T4]],[[T1]]
4188 ; MIPS32: srl [[T4]],[[T4]],0x10
4189 ; MIPS32: andi [[T4]],[[T4]],0xff
4190 ; MIPS32: sll [[T10]],[[T10]],0x18
4191 ; MIPS32: sll [[T4]],[[T4]],0x18
4192 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4193 ; MIPS32: andi [[T4]],[[T4]],0xff
4194 ; MIPS32: sll [[T4]],[[T4]],0x10
4195 ; MIPS32: lui [[T10]],0xff00
4196 ; MIPS32: ori [[T10]],[[T10]],0xffff
4197 ; MIPS32: and [[T5]],[[T5]],[[T10]]
4198 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4199 ; MIPS32: srl [[T11:.*]],a1,0x18
4200 ; MIPS32: srl [[T1]],[[T1]],0x18
4201 ; MIPS32: sll [[T11]],[[T11]],0x18
4202 ; MIPS32: sll [[T1]],[[T1]],0x18
4203 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
4204 ; MIPS32: srl [[T1]],[[T1]],0x18
4205 ; MIPS32: sll [[T4]],[[T4]],0x8
4206 ; MIPS32: srl [[T4]],[[T4]],0x8
4207 ; MIPS32: or v1,[[T1]],[[T4]]
4208 ; MIPS32: move [[T10]],a2
4209 ; MIPS32: andi [[T10]],[[T10]],0xff
4210 ; MIPS32: move [[T11]],[[T2]]
4211 ; MIPS32: andi [[T11]],[[T11]],0xff
4212 ; MIPS32: sll [[T10]],[[T10]],0x18
4213 ; MIPS32: sll [[T11]],[[T11]],0x18
4214 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4215 ; MIPS32: andi [[T11]],[[T11]],0xff
4216 ; MIPS32: srl [[T6]],[[T6]],0x8
4217 ; MIPS32: sll [[T6]],[[T6]],0x8
4218 ; MIPS32: or [[T11]],[[T11]],[[T6]]
4219 ; MIPS32: move [[T10]],a2
4220 ; MIPS32: srl [[T10]],[[T10]],0x8
4221 ; MIPS32: andi [[T10]],[[T10]],0xff
4222 ; MIPS32: move [[T4]],[[T2]]
4223 ; MIPS32: srl [[T4]],[[T4]],0x8
4224 ; MIPS32: andi [[T4]],[[T4]],0xff
4225 ; MIPS32: sll [[T10]],[[T10]],0x18
4226 ; MIPS32: sll [[T4]],[[T4]],0x18
4227 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4228 ; MIPS32: andi [[T4]],[[T4]],0xff
4229 ; MIPS32: sll [[T4]],[[T4]],0x8
4230 ; MIPS32: lui [[T10]],0xffff
4231 ; MIPS32: ori [[T10]],[[T10]],0xff
4232 ; MIPS32: and [[T11]],[[T11]],[[T10]]
4233 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4234 ; MIPS32: move [[T10]],a2
4235 ; MIPS32: srl [[T10]],[[T10]],0x10
4236 ; MIPS32: andi [[T10]],[[T10]],0xff
4237 ; MIPS32: move [[T11]],[[T2]]
4238 ; MIPS32: srl [[T11]],[[T11]],0x10
4239 ; MIPS32: andi [[T11]],[[T11]],0xff
4240 ; MIPS32: sll [[T10]],[[T10]],0x18
4241 ; MIPS32: sll [[T11]],[[T11]],0x18
4242 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4243 ; MIPS32: andi [[T11]],[[T11]],0xff
4244 ; MIPS32: sll [[T11]],[[T11]],0x10
4245 ; MIPS32: lui [[T10]],0xff00
4246 ; MIPS32: ori [[T10]],[[T10]],0xffff
4247 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4248 ; MIPS32: or [[T11]],[[T11]],[[T4]]
4249 ; MIPS32: srl [[T12:.*]],a2,0x18
4250 ; MIPS32: srl [[T2]],[[T2]],0x18
4251 ; MIPS32: sll [[T12]],[[T12]],0x18
4252 ; MIPS32: sll [[T2]],[[T2]],0x18
4253 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
4254 ; MIPS32: srl [[T2]],[[T2]],0x18
4255 ; MIPS32: sll [[T11]],[[T11]],0x8
4256 ; MIPS32: srl [[T11]],[[T11]],0x8
4257 ; MIPS32: or [[T2]],[[T2]],[[T11]]
4258 ; MIPS32: move [[T10]],a3
4259 ; MIPS32: andi [[T10]],[[T10]],0xff
4260 ; MIPS32: move [[T11]],[[T3]]
4261 ; MIPS32: andi [[T11]],[[T11]],0xff
4262 ; MIPS32: sll [[T10]],[[T10]],0x18
4263 ; MIPS32: sll [[T11]],[[T11]],0x18
4264 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4265 ; MIPS32: andi [[T11]],[[T11]],0xff
4266 ; MIPS32: srl [[T7]],[[T7]],0x8
4267 ; MIPS32: sll [[T7]],[[T7]],0x8
4268 ; MIPS32: or [[T11]],[[T11]],[[T7]]
4269 ; MIPS32: move [[T10]],a3
4270 ; MIPS32: srl [[T10]],[[T10]],0x8
4271 ; MIPS32: andi [[T10]],[[T10]],0xff
4272 ; MIPS32: move [[T12]],[[T3]]
4273 ; MIPS32: srl [[T12]],[[T12]],0x8
4274 ; MIPS32: andi [[T12]],[[T12]],0xff
4275 ; MIPS32: sll [[T10]],[[T10]],0x18
4276 ; MIPS32: sll [[T12]],[[T12]],0x18
4277 ; MIPS32: sltu [[T12]],[[T12]],[[T10]]
4278 ; MIPS32: andi [[T12]],[[T12]],0xff
4279 ; MIPS32: sll [[T12]],[[T12]],0x8
4280 ; MIPS32: lui [[T10]],0xffff
4281 ; MIPS32: ori [[T10]],[[T10]],0xff
4282 ; MIPS32: and [[T11]],[[T11]],[[T10]]
4283 ; MIPS32: or [[T12]],[[T12]],[[T11]]
4284 ; MIPS32: move [[T10]],a3
4285 ; MIPS32: srl [[T10]],[[T10]],0x10
4286 ; MIPS32: andi [[T10]],[[T10]],0xff
4287 ; MIPS32: move [[T11]],[[T3]]
4288 ; MIPS32: srl [[T11]],[[T11]],0x10
4289 ; MIPS32: andi [[T11]],[[T11]],0xff
4290 ; MIPS32: sll [[T10]],[[T10]],0x18
4291 ; MIPS32: sll [[T11]],[[T11]],0x18
4292 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4293 ; MIPS32: andi [[T11]],[[T11]],0xff
4294 ; MIPS32: sll [[T11]],[[T11]],0x10
4295 ; MIPS32: lui [[T10]],0xff00
4296 ; MIPS32: ori [[T10]],[[T10]],0xffff
4297 ; MIPS32: and [[T12]],[[T12]],[[T10]]
4298 ; MIPS32: or [[T11]],[[T11]],[[T12]]
4299 ; MIPS32: srl [[T13:.*]],a3,0x18
4300 ; MIPS32: srl [[T3]],[[T3]],0x18
4301 ; MIPS32: sll [[T13]],[[T13]],0x18
3829 ; MIPS32: sll [[T3]],[[T3]],0x18 4302 ; MIPS32: sll [[T3]],[[T3]],0x18
3830 ; MIPS32: sll [[T2]],[[T2]],0x18 4303 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
3831 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 4304 ; MIPS32: srl [[T3]],[[T3]],0x18
3832 ; MIPS32: andi [[T2]],[[T2]],0xff 4305 ; MIPS32: sll [[T11]],[[T11]],0x8
3833 ; MIPS32: sll [[T2]],[[T2]],0x10 4306 ; MIPS32: srl [[T11]],[[T11]],0x8
3834 ; MIPS32: lui [[T3]],0xff00 4307 ; MIPS32: or [[T3]],[[T3]],[[T11]]
3835 ; MIPS32: ori [[T3]],[[T3]],0xffff 4308 ; MIPS32: move a0,[[T2]]
3836 ; MIPS32: and [[T5]],[[T5]],[[T3]] 4309 ; MIPS32: move a1,[[T3]]
3837 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3838 ; MIPS32: srl [[T6:.*]],a1,0x18
3839 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3840 ; MIPS32: sll [[T6]],[[T6]],0x18
3841 ; MIPS32: sll [[T7]],[[T7]],0x18
3842 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
3843 ; MIPS32: srl [[T7]],[[T7]],0x18
3844 ; MIPS32: sll [[T2]],[[T2]],0x8
3845 ; MIPS32: srl [[T2]],[[T2]],0x8
3846 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3847 ; MIPS32: andi [[T3]],a2,0xff
3848 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3849 ; MIPS32: sll [[T3]],[[T3]],0x18
3850 ; MIPS32: sll [[T6]],[[T6]],0x18
3851 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3852 ; MIPS32: andi [[T6]],[[T6]],0xff
3853 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3854 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3855 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3856 ; MIPS32: srl [[T3]],a2,0x8
3857 ; MIPS32: andi [[T3]],[[T3]],0xff
3858 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3859 ; MIPS32: andi [[T2]],[[T2]],0xff
3860 ; MIPS32: sll [[T3]],[[T3]],0x18
3861 ; MIPS32: sll [[T2]],[[T2]],0x18
3862 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
3863 ; MIPS32: andi [[T2]],[[T2]],0xff
3864 ; MIPS32: sll [[T2]],[[T2]],0x8
3865 ; MIPS32: lui [[T3]],0xffff
3866 ; MIPS32: ori [[T3]],[[T3]],0xff
3867 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3868 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3869 ; MIPS32: srl [[T3]],a2,0x10
3870 ; MIPS32: andi [[T3]],[[T3]],0xff
3871 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3872 ; MIPS32: andi [[T6]],[[T6]],0xff
3873 ; MIPS32: sll [[T3]],[[T3]],0x18
3874 ; MIPS32: sll [[T6]],[[T6]],0x18
3875 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3876 ; MIPS32: andi [[T6]],[[T6]],0xff
3877 ; MIPS32: sll [[T6]],[[T6]],0x10
3878 ; MIPS32: lui [[T3]],0xff00
3879 ; MIPS32: ori [[T3]],[[T3]],0xffff
3880 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3881 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3882 ; MIPS32: srl [[T9:.*]],a2,0x18
3883 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3884 ; MIPS32: sll [[T9]],[[T9]],0x18
3885 ; MIPS32: sll [[T10]],[[T10]],0x18
3886 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
3887 ; MIPS32: srl [[T10]],[[T10]],0x18
3888 ; MIPS32: sll [[T6]],[[T6]],0x8
3889 ; MIPS32: srl [[T6]],[[T6]],0x8
3890 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3891 ; MIPS32: andi [[T3]],a3,0xff
3892 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3893 ; MIPS32: sll [[T3]],[[T3]],0x18
3894 ; MIPS32: sll [[T6]],[[T6]],0x18
3895 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3896 ; MIPS32: andi [[T6]],[[T6]],0xff
3897 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3898 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3899 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3900 ; MIPS32: srl [[T3]],a3,0x8
3901 ; MIPS32: andi [[T3]],[[T3]],0xff
3902 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3903 ; MIPS32: andi [[T9]],[[T9]],0xff
3904 ; MIPS32: sll [[T3]],[[T3]],0x18
3905 ; MIPS32: sll [[T9]],[[T9]],0x18
3906 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
3907 ; MIPS32: andi [[T9]],[[T9]],0xff
3908 ; MIPS32: sll [[T9]],[[T9]],0x8
3909 ; MIPS32: lui [[T3]],0xffff
3910 ; MIPS32: ori [[T3]],[[T3]],0xff
3911 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3912 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3913 ; MIPS32: srl [[T3]],a3,0x10
3914 ; MIPS32: andi [[T3]],[[T3]],0xff
3915 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3916 ; MIPS32: andi [[T6]],[[T6]],0xff
3917 ; MIPS32: sll [[T3]],[[T3]],0x18
3918 ; MIPS32: sll [[T6]],[[T6]],0x18
3919 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3920 ; MIPS32: andi [[T6]],[[T6]],0xff
3921 ; MIPS32: sll [[T6]],[[T6]],0x10
3922 ; MIPS32: lui [[T3]],0xff00
3923 ; MIPS32: ori [[T3]],[[T3]],0xffff
3924 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3925 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3926 ; MIPS32: srl [[T12:.*]],a3,0x18
3927 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3928 ; MIPS32: sll [[T12]],[[T12]],0x18
3929 ; MIPS32: sll [[T13]],[[T13]],0x18
3930 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
3931 ; MIPS32: srl [[T13]],[[T13]],0x18
3932 ; MIPS32: sll [[T6]],[[T6]],0x8
3933 ; MIPS32: srl [[T6]],[[T6]],0x8
3934 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
3935 } 4310 }
3936 4311
3937 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) { 4312 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) {
3938 entry: 4313 entry:
3939 %res = icmp ule <16 x i8> %a, %b 4314 %res = icmp ule <16 x i8> %a, %b
3940 ret <16 x i1> %res 4315 ret <16 x i1> %res
3941 ; CHECK-LABEL: test_icmp_v16i8_ule 4316 ; CHECK-LABEL: test_icmp_v16i8_ule
3942 ; CHECK: pxor 4317 ; CHECK: pxor
3943 ; CHECK: pcmpgtb 4318 ; CHECK: pcmpgtb
3944 ; CHECK: pxor 4319 ; CHECK: pxor
3945 4320
3946 ; MIPS32-LABEL: test_icmp_v16i8_ule 4321 ; MIPS32-LABEL: test_icmp_v16i8_ule
3947 ; MIPS32: lw [[BV_E0:.*]], 4322 ; MIPS32: lw [[T0:.*]],
3948 ; MIPS32: lw [[BV_E1:.*]], 4323 ; MIPS32: lw [[T1:.*]],
3949 ; MIPS32: lw [[BV_E2:.*]], 4324 ; MIPS32: lw [[T2:.*]],
3950 ; MIPS32: lw [[BV_E3:.*]], 4325 ; MIPS32: lw [[T3:.*]],
3951 ; MIPS32: move [[TV_E0:.*]],zero 4326 ; MIPS32: move [[T4:.*]],zero
3952 ; MIPS32: move [[TV_E1:.*]],zero 4327 ; MIPS32: move [[T5:.*]],zero
3953 ; MIPS32: move [[TV_E2:.*]],zero 4328 ; MIPS32: move [[T6:.*]],zero
3954 ; MIPS32: move [[TV_E3:.*]],zero 4329 ; MIPS32: move [[T7:.*]],zero
3955 ; MIPS32: andi [[T0:.*]],a0,0xff 4330 ; MIPS32: move [[T8:.*]],a0
3956 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 4331 ; MIPS32: andi [[T8]],[[T8]],0xff
3957 ; MIPS32: sll [[T0]],[[T0]],0x18 4332 ; MIPS32: move [[T9:.*]],[[T0]]
3958 ; MIPS32: sll [[T1]],[[T1]],0x18 4333 ; MIPS32: andi [[T9]],[[T9]],0xff
3959 ; MIPS32: sltu [[T1]],[[T1]],[[T0]] 4334 ; MIPS32: sll [[T8]],[[T8]],0x18
3960 ; MIPS32: xori [[T1]],[[T1]],0x1 4335 ; MIPS32: sll [[T9]],[[T9]],0x18
3961 ; MIPS32: andi [[T1]],[[T1]],0xff 4336 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
3962 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 4337 ; MIPS32: xori [[T9]],[[T9]],0x1
3963 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 4338 ; MIPS32: andi [[T9]],[[T9]],0xff
3964 ; MIPS32: or [[T1]],[[T1]],[[T2]] 4339 ; MIPS32: srl [[T4]],[[T4]],0x8
3965 ; MIPS32: srl [[T2]],a0,0x8 4340 ; MIPS32: sll [[T4]],[[T4]],0x8
3966 ; MIPS32: andi [[T2]],[[T2]],0xff 4341 ; MIPS32: or [[T9]],[[T9]],[[T4]]
3967 ; MIPS32: srl [[T0]],[[BV_E0]],0x8 4342 ; MIPS32: move [[T4]],a0
3968 ; MIPS32: andi [[T0]],[[T0]],0xff 4343 ; MIPS32: srl [[T4]],[[T4]],0x8
3969 ; MIPS32: sll [[T2]],[[T2]],0x18 4344 ; MIPS32: andi [[T4]],[[T4]],0xff
3970 ; MIPS32: sll [[T0]],[[T0]],0x18 4345 ; MIPS32: move [[T8]],[[T0]]
3971 ; MIPS32: sltu [[T0]],[[T0]],[[T2]] 4346 ; MIPS32: srl [[T8]],[[T8]],0x8
4347 ; MIPS32: andi [[T8]],[[T8]],0xff
4348 ; MIPS32: sll [[T4]],[[T4]],0x18
4349 ; MIPS32: sll [[T8]],[[T8]],0x18
4350 ; MIPS32: sltu [[T8]],[[T8]],[[T4]]
4351 ; MIPS32: xori [[T8]],[[T8]],0x1
4352 ; MIPS32: andi [[T8]],[[T8]],0xff
4353 ; MIPS32: sll [[T8]],[[T8]],0x8
4354 ; MIPS32: lui [[T4]],0xffff
4355 ; MIPS32: ori [[T4]],[[T4]],0xff
4356 ; MIPS32: and [[T9]],[[T9]],[[T4]]
4357 ; MIPS32: or [[T8]],[[T8]],[[T9]]
4358 ; MIPS32: move [[T4]],a0
4359 ; MIPS32: srl [[T4]],[[T4]],0x10
4360 ; MIPS32: andi [[T4]],[[T4]],0xff
4361 ; MIPS32: move [[T9]],[[T0]]
4362 ; MIPS32: srl [[T9]],[[T9]],0x10
4363 ; MIPS32: andi [[T9]],[[T9]],0xff
4364 ; MIPS32: sll [[T4]],[[T4]],0x18
4365 ; MIPS32: sll [[T9]],[[T9]],0x18
4366 ; MIPS32: sltu [[T9]],[[T9]],[[T4]]
4367 ; MIPS32: xori [[T9]],[[T9]],0x1
4368 ; MIPS32: andi [[T9]],[[T9]],0xff
4369 ; MIPS32: sll [[T9]],[[T9]],0x10
4370 ; MIPS32: lui [[T4]],0xff00
4371 ; MIPS32: ori [[T4]],[[T4]],0xffff
4372 ; MIPS32: and [[T8]],[[T8]],[[T4]]
4373 ; MIPS32: or [[T9]],[[T9]],[[T8]]
4374 ; MIPS32: srl [[T10:.*]],a0,0x18
4375 ; MIPS32: srl [[T0]],[[T0]],0x18
4376 ; MIPS32: sll [[T10]],[[T10]],0x18
4377 ; MIPS32: sll [[T0]],[[T0]],0x18
4378 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
3972 ; MIPS32: xori [[T0]],[[T0]],0x1 4379 ; MIPS32: xori [[T0]],[[T0]],0x1
3973 ; MIPS32: andi [[T0]],[[T0]],0xff 4380 ; MIPS32: srl [[T0]],[[T0]],0x18
3974 ; MIPS32: sll [[T0]],[[T0]],0x8 4381 ; MIPS32: sll [[T9]],[[T9]],0x8
3975 ; MIPS32: lui [[T2]],0xffff 4382 ; MIPS32: srl [[T9]],[[T9]],0x8
3976 ; MIPS32: ori [[T2]],[[T2]],0xff 4383 ; MIPS32: or v0,[[T0]],[[T9]]
3977 ; MIPS32: and [[T1]],[[T1]],[[T2]] 4384 ; MIPS32: move [[T10]],a1
3978 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4385 ; MIPS32: andi [[T10]],[[T10]],0xff
3979 ; MIPS32: srl [[T2]],a0,0x10 4386 ; MIPS32: move [[T4]],[[T1]]
3980 ; MIPS32: andi [[T2]],[[T2]],0xff 4387 ; MIPS32: andi [[T4]],[[T4]],0xff
3981 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 4388 ; MIPS32: sll [[T10]],[[T10]],0x18
3982 ; MIPS32: andi [[T1]],[[T1]],0xff 4389 ; MIPS32: sll [[T4]],[[T4]],0x18
3983 ; MIPS32: sll [[T2]],[[T2]],0x18 4390 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
3984 ; MIPS32: sll [[T1]],[[T1]],0x18
3985 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
3986 ; MIPS32: xori [[T1]],[[T1]],0x1
3987 ; MIPS32: andi [[T1]],[[T1]],0xff
3988 ; MIPS32: sll [[T1]],[[T1]],0x10
3989 ; MIPS32: lui [[T2]],0xff00
3990 ; MIPS32: ori [[T2]],[[T2]],0xffff
3991 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3992 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3993 ; MIPS32: srl [[T3:.*]],a0,0x18
3994 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3995 ; MIPS32: sll [[T3]],[[T3]],0x18
3996 ; MIPS32: sll [[T4]],[[T4]],0x18
3997 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
3998 ; MIPS32: xori [[T4]],[[T4]],0x1 4391 ; MIPS32: xori [[T4]],[[T4]],0x1
3999 ; MIPS32: srl [[T4]],[[T4]],0x18 4392 ; MIPS32: andi [[T4]],[[T4]],0xff
4000 ; MIPS32: sll [[T1]],[[T1]],0x8 4393 ; MIPS32: srl [[T5]],[[T5]],0x8
4001 ; MIPS32: srl [[T1]],[[T1]],0x8 4394 ; MIPS32: sll [[T5]],[[T5]],0x8
4002 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] 4395 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4003 ; MIPS32: andi [[T3]],a1,0xff 4396 ; MIPS32: move [[T10]],a1
4004 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 4397 ; MIPS32: srl [[T10]],[[T10]],0x8
4005 ; MIPS32: sll [[T3]],[[T3]],0x18 4398 ; MIPS32: andi [[T10]],[[T10]],0xff
4006 ; MIPS32: sll [[T2]],[[T2]],0x18 4399 ; MIPS32: move [[T5]],[[T1]]
4007 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 4400 ; MIPS32: srl [[T5]],[[T5]],0x8
4008 ; MIPS32: xori [[T2]],[[T2]],0x1
4009 ; MIPS32: andi [[T2]],[[T2]],0xff
4010 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4011 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
4012 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4013 ; MIPS32: srl [[T3]],a1,0x8
4014 ; MIPS32: andi [[T3]],[[T3]],0xff
4015 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4016 ; MIPS32: andi [[T5]],[[T5]],0xff 4401 ; MIPS32: andi [[T5]],[[T5]],0xff
4017 ; MIPS32: sll [[T3]],[[T3]],0x18 4402 ; MIPS32: sll [[T10]],[[T10]],0x18
4018 ; MIPS32: sll [[T5]],[[T5]],0x18 4403 ; MIPS32: sll [[T5]],[[T5]],0x18
4019 ; MIPS32: sltu [[T5]],[[T5]],[[T3]] 4404 ; MIPS32: sltu [[T5]],[[T5]],[[T10]]
4020 ; MIPS32: xori [[T5]],[[T5]],0x1 4405 ; MIPS32: xori [[T5]],[[T5]],0x1
4021 ; MIPS32: andi [[T5]],[[T5]],0xff 4406 ; MIPS32: andi [[T5]],[[T5]],0xff
4022 ; MIPS32: sll [[T5]],[[T5]],0x8 4407 ; MIPS32: sll [[T5]],[[T5]],0x8
4023 ; MIPS32: lui [[T3]],0xffff 4408 ; MIPS32: lui [[T10]],0xffff
4024 ; MIPS32: ori [[T3]],[[T3]],0xff 4409 ; MIPS32: ori [[T10]],[[T10]],0xff
4025 ; MIPS32: and [[T2]],[[T2]],[[T3]] 4410 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4026 ; MIPS32: or [[T5]],[[T5]],[[T2]] 4411 ; MIPS32: or [[T5]],[[T5]],[[T4]]
4027 ; MIPS32: srl [[T3]],a1,0x10 4412 ; MIPS32: move [[T10]],a1
4028 ; MIPS32: andi [[T3]],[[T3]],0xff 4413 ; MIPS32: srl [[T10]],[[T10]],0x10
4029 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 4414 ; MIPS32: andi [[T10]],[[T10]],0xff
4030 ; MIPS32: andi [[T2]],[[T2]],0xff 4415 ; MIPS32: move [[T4]],[[T1]]
4416 ; MIPS32: srl [[T4]],[[T4]],0x10
4417 ; MIPS32: andi [[T4]],[[T4]],0xff
4418 ; MIPS32: sll [[T10]],[[T10]],0x18
4419 ; MIPS32: sll [[T4]],[[T4]],0x18
4420 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4421 ; MIPS32: xori [[T4]],[[T4]],0x1
4422 ; MIPS32: andi [[T4]],[[T4]],0xff
4423 ; MIPS32: sll [[T4]],[[T4]],0x10
4424 ; MIPS32: lui [[T10]],0xff00
4425 ; MIPS32: ori [[T10]],[[T10]],0xffff
4426 ; MIPS32: and [[T5]],[[T5]],[[T10]]
4427 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4428 ; MIPS32: srl [[T11:.*]],a1,0x18
4429 ; MIPS32: srl [[T1]],[[T1]],0x18
4430 ; MIPS32: sll [[T11]],[[T11]],0x18
4431 ; MIPS32: sll [[T1]],[[T1]],0x18
4432 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
4433 ; MIPS32: xori [[T1]],[[T1]],0x1
4434 ; MIPS32: srl [[T1]],[[T1]],0x18
4435 ; MIPS32: sll [[T4]],[[T4]],0x8
4436 ; MIPS32: srl [[T4]],[[T4]],0x8
4437 ; MIPS32: or v1,[[T1]],[[T4]]
4438 ; MIPS32: move [[T10]],a2
4439 ; MIPS32: andi [[T10]],[[T10]],0xff
4440 ; MIPS32: move [[T11]],[[T2]]
4441 ; MIPS32: andi [[T11]],[[T11]],0xff
4442 ; MIPS32: sll [[T10]],[[T10]],0x18
4443 ; MIPS32: sll [[T11]],[[T11]],0x18
4444 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4445 ; MIPS32: xori [[T11]],[[T11]],0x1
4446 ; MIPS32: andi [[T11]],[[T11]],0xff
4447 ; MIPS32: srl [[T6]],[[T6]],0x8
4448 ; MIPS32: sll [[T6]],[[T6]],0x8
4449 ; MIPS32: or [[T11]],[[T11]],[[T6]]
4450 ; MIPS32: move [[T10]],a2
4451 ; MIPS32: srl [[T10]],[[T10]],0x8
4452 ; MIPS32: andi [[T10]],[[T10]],0xff
4453 ; MIPS32: move [[T4]],[[T2]]
4454 ; MIPS32: srl [[T4]],[[T4]],0x8
4455 ; MIPS32: andi [[T4]],[[T4]],0xff
4456 ; MIPS32: sll [[T10]],[[T10]],0x18
4457 ; MIPS32: sll [[T4]],[[T4]],0x18
4458 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4459 ; MIPS32: xori [[T4]],[[T4]],0x1
4460 ; MIPS32: andi [[T4]],[[T4]],0xff
4461 ; MIPS32: sll [[T4]],[[T4]],0x8
4462 ; MIPS32: lui [[T10]],0xffff
4463 ; MIPS32: ori [[T10]],[[T10]],0xff
4464 ; MIPS32: and [[T11]],[[T11]],[[T10]]
4465 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4466 ; MIPS32: move [[T10]],a2
4467 ; MIPS32: srl [[T10]],[[T10]],0x10
4468 ; MIPS32: andi [[T10]],[[T10]],0xff
4469 ; MIPS32: move [[T11]],[[T2]]
4470 ; MIPS32: srl [[T11]],[[T11]],0x10
4471 ; MIPS32: andi [[T11]],[[T11]],0xff
4472 ; MIPS32: sll [[T10]],[[T10]],0x18
4473 ; MIPS32: sll [[T11]],[[T11]],0x18
4474 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4475 ; MIPS32: xori [[T11]],[[T11]],0x1
4476 ; MIPS32: andi [[T11]],[[T11]],0xff
4477 ; MIPS32: sll [[T11]],[[T11]],0x10
4478 ; MIPS32: lui [[T10]],0xff00
4479 ; MIPS32: ori [[T10]],[[T10]],0xffff
4480 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4481 ; MIPS32: or [[T11]],[[T11]],[[T4]]
4482 ; MIPS32: srl [[T12:.*]],a2,0x18
4483 ; MIPS32: srl [[T2]],[[T2]],0x18
4484 ; MIPS32: sll [[T12]],[[T12]],0x18
4485 ; MIPS32: sll [[T2]],[[T2]],0x18
4486 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
4487 ; MIPS32: xori [[T2]],[[T2]],0x1
4488 ; MIPS32: srl [[T2]],[[T2]],0x18
4489 ; MIPS32: sll [[T11]],[[T11]],0x8
4490 ; MIPS32: srl [[T11]],[[T11]],0x8
4491 ; MIPS32: or [[T2]],[[T2]],[[T11]]
4492 ; MIPS32: move [[T10]],a3
4493 ; MIPS32: andi [[T10]],[[T10]],0xff
4494 ; MIPS32: move [[T11]],[[T3]]
4495 ; MIPS32: andi [[T11]],[[T11]],0xff
4496 ; MIPS32: sll [[T10]],[[T10]],0x18
4497 ; MIPS32: sll [[T11]],[[T11]],0x18
4498 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4499 ; MIPS32: xori [[T11]],[[T11]],0x1
4500 ; MIPS32: andi [[T11]],[[T11]],0xff
4501 ; MIPS32: srl [[T7]],[[T7]],0x8
4502 ; MIPS32: sll [[T7]],[[T7]],0x8
4503 ; MIPS32: or [[T11]],[[T11]],[[T7]]
4504 ; MIPS32: move [[T10]],a3
4505 ; MIPS32: srl [[T10]],[[T10]],0x8
4506 ; MIPS32: andi [[T10]],[[T10]],0xff
4507 ; MIPS32: move [[T12]],[[T3]]
4508 ; MIPS32: srl [[T12]],[[T12]],0x8
4509 ; MIPS32: andi [[T12]],[[T12]],0xff
4510 ; MIPS32: sll [[T10]],[[T10]],0x18
4511 ; MIPS32: sll [[T12]],[[T12]],0x18
4512 ; MIPS32: sltu [[T12]],[[T12]],[[T10]]
4513 ; MIPS32: xori [[T12]],[[T12]],0x1
4514 ; MIPS32: andi [[T12]],[[T12]],0xff
4515 ; MIPS32: sll [[T12]],[[T12]],0x8
4516 ; MIPS32: lui [[T10]],0xffff
4517 ; MIPS32: ori [[T10]],[[T10]],0xff
4518 ; MIPS32: and [[T11]],[[T11]],[[T10]]
4519 ; MIPS32: or [[T12]],[[T12]],[[T11]]
4520 ; MIPS32: move [[T10]],a3
4521 ; MIPS32: srl [[T10]],[[T10]],0x10
4522 ; MIPS32: andi [[T10]],[[T10]],0xff
4523 ; MIPS32: move [[T11]],[[T3]]
4524 ; MIPS32: srl [[T11]],[[T11]],0x10
4525 ; MIPS32: andi [[T11]],[[T11]],0xff
4526 ; MIPS32: sll [[T10]],[[T10]],0x18
4527 ; MIPS32: sll [[T11]],[[T11]],0x18
4528 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
4529 ; MIPS32: xori [[T11]],[[T11]],0x1
4530 ; MIPS32: andi [[T11]],[[T11]],0xff
4531 ; MIPS32: sll [[T11]],[[T11]],0x10
4532 ; MIPS32: lui [[T10]],0xff00
4533 ; MIPS32: ori [[T10]],[[T10]],0xffff
4534 ; MIPS32: and [[T12]],[[T12]],[[T10]]
4535 ; MIPS32: or [[T11]],[[T11]],[[T12]]
4536 ; MIPS32: srl [[T13:.*]],a3,0x18
4537 ; MIPS32: srl [[T3]],[[T3]],0x18
4538 ; MIPS32: sll [[T13]],[[T13]],0x18
4031 ; MIPS32: sll [[T3]],[[T3]],0x18 4539 ; MIPS32: sll [[T3]],[[T3]],0x18
4032 ; MIPS32: sll [[T2]],[[T2]],0x18 4540 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
4033 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 4541 ; MIPS32: xori [[T3]],[[T3]],0x1
4034 ; MIPS32: xori [[T2]],[[T2]],0x1 4542 ; MIPS32: srl [[T3]],[[T3]],0x18
4035 ; MIPS32: andi [[T2]],[[T2]],0xff 4543 ; MIPS32: sll [[T11]],[[T11]],0x8
4036 ; MIPS32: sll [[T2]],[[T2]],0x10 4544 ; MIPS32: srl [[T11]],[[T11]],0x8
4037 ; MIPS32: lui [[T3]],0xff00 4545 ; MIPS32: or [[T3]],[[T3]],[[T11]]
4038 ; MIPS32: ori [[T3]],[[T3]],0xffff 4546 ; MIPS32: move a0,[[T2]]
4039 ; MIPS32: and [[T5]],[[T5]],[[T3]] 4547 ; MIPS32: move a1,[[T3]]
4040 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4041 ; MIPS32: srl [[T6:.*]],a1,0x18
4042 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4043 ; MIPS32: sll [[T6]],[[T6]],0x18
4044 ; MIPS32: sll [[T7]],[[T7]],0x18
4045 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
4046 ; MIPS32: xori [[T7]],[[T7]],0x1
4047 ; MIPS32: srl [[T7]],[[T7]],0x18
4048 ; MIPS32: sll [[T2]],[[T2]],0x8
4049 ; MIPS32: srl [[T2]],[[T2]],0x8
4050 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
4051 ; MIPS32: andi [[T3]],a2,0xff
4052 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
4053 ; MIPS32: sll [[T3]],[[T3]],0x18
4054 ; MIPS32: sll [[T6]],[[T6]],0x18
4055 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4056 ; MIPS32: xori [[T6]],[[T6]],0x1
4057 ; MIPS32: andi [[T6]],[[T6]],0xff
4058 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4059 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
4060 ; MIPS32: or [[T6]],[[T6]],[[T8]]
4061 ; MIPS32: srl [[T3]],a2,0x8
4062 ; MIPS32: andi [[T3]],[[T3]],0xff
4063 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4064 ; MIPS32: andi [[T2]],[[T2]],0xff
4065 ; MIPS32: sll [[T3]],[[T3]],0x18
4066 ; MIPS32: sll [[T2]],[[T2]],0x18
4067 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
4068 ; MIPS32: xori [[T2]],[[T2]],0x1
4069 ; MIPS32: andi [[T2]],[[T2]],0xff
4070 ; MIPS32: sll [[T2]],[[T2]],0x8
4071 ; MIPS32: lui [[T3]],0xffff
4072 ; MIPS32: ori [[T3]],[[T3]],0xff
4073 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4074 ; MIPS32: or [[T2]],[[T2]],[[T6]]
4075 ; MIPS32: srl [[T3]],a2,0x10
4076 ; MIPS32: andi [[T3]],[[T3]],0xff
4077 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
4078 ; MIPS32: andi [[T6]],[[T6]],0xff
4079 ; MIPS32: sll [[T3]],[[T3]],0x18
4080 ; MIPS32: sll [[T6]],[[T6]],0x18
4081 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4082 ; MIPS32: xori [[T6]],[[T6]],0x1
4083 ; MIPS32: andi [[T6]],[[T6]],0xff
4084 ; MIPS32: sll [[T6]],[[T6]],0x10
4085 ; MIPS32: lui [[T3]],0xff00
4086 ; MIPS32: ori [[T3]],[[T3]],0xffff
4087 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4088 ; MIPS32: or [[T6]],[[T6]],[[T2]]
4089 ; MIPS32: srl [[T9:.*]],a2,0x18
4090 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4091 ; MIPS32: sll [[T9]],[[T9]],0x18
4092 ; MIPS32: sll [[T10]],[[T10]],0x18
4093 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
4094 ; MIPS32: xori [[T10]],[[T10]],0x1
4095 ; MIPS32: srl [[T10]],[[T10]],0x18
4096 ; MIPS32: sll [[T6]],[[T6]],0x8
4097 ; MIPS32: srl [[T6]],[[T6]],0x8
4098 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
4099 ; MIPS32: andi [[T3]],a3,0xff
4100 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
4101 ; MIPS32: sll [[T3]],[[T3]],0x18
4102 ; MIPS32: sll [[T6]],[[T6]],0x18
4103 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4104 ; MIPS32: xori [[T6]],[[T6]],0x1
4105 ; MIPS32: andi [[T6]],[[T6]],0xff
4106 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4107 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
4108 ; MIPS32: or [[T6]],[[T6]],[[T11]]
4109 ; MIPS32: srl [[T3]],a3,0x8
4110 ; MIPS32: andi [[T3]],[[T3]],0xff
4111 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
4112 ; MIPS32: andi [[T9]],[[T9]],0xff
4113 ; MIPS32: sll [[T3]],[[T3]],0x18
4114 ; MIPS32: sll [[T9]],[[T9]],0x18
4115 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
4116 ; MIPS32: xori [[T9]],[[T9]],0x1
4117 ; MIPS32: andi [[T9]],[[T9]],0xff
4118 ; MIPS32: sll [[T9]],[[T9]],0x8
4119 ; MIPS32: lui [[T3]],0xffff
4120 ; MIPS32: ori [[T3]],[[T3]],0xff
4121 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4122 ; MIPS32: or [[T9]],[[T9]],[[T6]]
4123 ; MIPS32: srl [[T3]],a3,0x10
4124 ; MIPS32: andi [[T3]],[[T3]],0xff
4125 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
4126 ; MIPS32: andi [[T6]],[[T6]],0xff
4127 ; MIPS32: sll [[T3]],[[T3]],0x18
4128 ; MIPS32: sll [[T6]],[[T6]],0x18
4129 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4130 ; MIPS32: xori [[T6]],[[T6]],0x1
4131 ; MIPS32: andi [[T6]],[[T6]],0xff
4132 ; MIPS32: sll [[T6]],[[T6]],0x10
4133 ; MIPS32: lui [[T3]],0xff00
4134 ; MIPS32: ori [[T3]],[[T3]],0xffff
4135 ; MIPS32: and [[T9]],[[T9]],[[T3]]
4136 ; MIPS32: or [[T6]],[[T6]],[[T9]]
4137 ; MIPS32: srl [[T12:.*]],a3,0x18
4138 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4139 ; MIPS32: sll [[T12]],[[T12]],0x18
4140 ; MIPS32: sll [[T13]],[[T13]],0x18
4141 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
4142 ; MIPS32: xori [[T13]],[[T13]],0x1
4143 ; MIPS32: srl [[T13]],[[T13]],0x18
4144 ; MIPS32: sll [[T6]],[[T6]],0x8
4145 ; MIPS32: srl [[T6]],[[T6]],0x8
4146 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
4147 } 4548 }
4148 4549
4149 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) { 4550 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) {
4150 entry: 4551 entry:
4151 %res = icmp ult <16 x i8> %a, %b 4552 %res = icmp ult <16 x i8> %a, %b
4152 ret <16 x i1> %res 4553 ret <16 x i1> %res
4153 ; CHECK-LABEL: test_icmp_v16i8_ult 4554 ; CHECK-LABEL: test_icmp_v16i8_ult
4154 ; CHECK: pxor 4555 ; CHECK: pxor
4155 ; CHECK: pcmpgtb 4556 ; CHECK: pcmpgtb
4156 4557
4157 ; MIPS32-LABEL: test_icmp_v16i8_ult 4558 ; MIPS32-LABEL: test_icmp_v16i8_ult
4158 ; MIPS32: lw [[BV_E0:.*]], 4559 ; MIPS32: lw [[T0:.*]],
4159 ; MIPS32: lw [[BV_E1:.*]], 4560 ; MIPS32: lw [[T1:.*]],
4160 ; MIPS32: lw [[BV_E2:.*]], 4561 ; MIPS32: lw [[T2:.*]],
4161 ; MIPS32: lw [[BV_E3:.*]], 4562 ; MIPS32: lw [[T3:.*]],
4162 ; MIPS32: move [[TV_E0:.*]],zero 4563 ; MIPS32: move [[T4:.*]],zero
4163 ; MIPS32: move [[TV_E1:.*]],zero 4564 ; MIPS32: move [[T5:.*]],zero
4164 ; MIPS32: move [[TV_E2:.*]],zero 4565 ; MIPS32: move [[T6:.*]],zero
4165 ; MIPS32: move [[TV_E3:.*]],zero 4566 ; MIPS32: move [[T7:.*]],zero
4166 ; MIPS32: andi [[T0:.*]],a0,0xff 4567 ; MIPS32: move [[T8:.*]],a0
4167 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 4568 ; MIPS32: andi [[T8]],[[T8]],0xff
4168 ; MIPS32: sll [[T0]],[[T0]],0x18 4569 ; MIPS32: move [[T9:.*]],[[T0]]
4169 ; MIPS32: sll [[T1]],[[T1]],0x18 4570 ; MIPS32: andi [[T9]],[[T9]],0xff
4170 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4571 ; MIPS32: sll [[T8]],[[T8]],0x18
4171 ; MIPS32: andi [[T0]],[[T0]],0xff 4572 ; MIPS32: sll [[T9]],[[T9]],0x18
4172 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 4573 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
4173 ; MIPS32: sll [[T2]],[[TV_E0]],0x8 4574 ; MIPS32: andi [[T8]],[[T8]],0xff
4174 ; MIPS32: or [[T0]],[[T0]],[[T2]] 4575 ; MIPS32: srl [[T4]],[[T4]],0x8
4175 ; MIPS32: srl [[T2]],a0,0x8 4576 ; MIPS32: sll [[T4]],[[T4]],0x8
4176 ; MIPS32: andi [[T2]],[[T2]],0xff 4577 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4177 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 4578 ; MIPS32: move [[T4]],a0
4178 ; MIPS32: andi [[T1]],[[T1]],0xff 4579 ; MIPS32: srl [[T4]],[[T4]],0x8
4179 ; MIPS32: sll [[T2]],[[T2]],0x18 4580 ; MIPS32: andi [[T4]],[[T4]],0xff
4180 ; MIPS32: sll [[T1]],[[T1]],0x18 4581 ; MIPS32: move [[T9]],[[T0]]
4181 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 4582 ; MIPS32: srl [[T9]],[[T9]],0x8
4182 ; MIPS32: andi [[T2]],[[T2]],0xff 4583 ; MIPS32: andi [[T9]],[[T9]],0xff
4183 ; MIPS32: sll [[T2]],[[T2]],0x8 4584 ; MIPS32: sll [[T4]],[[T4]],0x18
4184 ; MIPS32: lui [[T1]],0xffff 4585 ; MIPS32: sll [[T9]],[[T9]],0x18
4185 ; MIPS32: ori [[T1]],[[T1]],0xff 4586 ; MIPS32: sltu [[T4]],[[T4]],[[T9]]
4186 ; MIPS32: and [[T0]],[[T0]],[[T1]] 4587 ; MIPS32: andi [[T4]],[[T4]],0xff
4187 ; MIPS32: or [[T2]],[[T2]],[[T0]] 4588 ; MIPS32: sll [[T4]],[[T4]],0x8
4188 ; MIPS32: srl [[T0]],a0,0x10 4589 ; MIPS32: lui [[T9]],0xffff
4189 ; MIPS32: andi [[T0]],[[T0]],0xff 4590 ; MIPS32: ori [[T9]],[[T9]],0xff
4190 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 4591 ; MIPS32: and [[T8]],[[T8]],[[T9]]
4191 ; MIPS32: andi [[T1]],[[T1]],0xff 4592 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4192 ; MIPS32: sll [[T0]],[[T0]],0x18 4593 ; MIPS32: move [[T8]],a0
4193 ; MIPS32: sll [[T1]],[[T1]],0x18 4594 ; MIPS32: srl [[T8]],[[T8]],0x10
4194 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4595 ; MIPS32: andi [[T8]],[[T8]],0xff
4596 ; MIPS32: move [[T9]],[[T0]]
4597 ; MIPS32: srl [[T9]],[[T9]],0x10
4598 ; MIPS32: andi [[T9]],[[T9]],0xff
4599 ; MIPS32: sll [[T8]],[[T8]],0x18
4600 ; MIPS32: sll [[T9]],[[T9]],0x18
4601 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
4602 ; MIPS32: andi [[T8]],[[T8]],0xff
4603 ; MIPS32: sll [[T8]],[[T8]],0x10
4604 ; MIPS32: lui [[T9]],0xff00
4605 ; MIPS32: ori [[T9]],[[T9]],0xffff
4606 ; MIPS32: and [[T4]],[[T4]],[[T9]]
4607 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4608 ; MIPS32: srl [[T10:.*]],a0,0x18
4609 ; MIPS32: srl [[T0]],[[T0]],0x18
4610 ; MIPS32: sll [[T10]],[[T10]],0x18
4611 ; MIPS32: sll [[T0]],[[T0]],0x18
4612 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
4613 ; MIPS32: srl [[T10]],[[T10]],0x18
4614 ; MIPS32: sll [[T8]],[[T8]],0x8
4615 ; MIPS32: srl [[T8]],[[T8]],0x8
4616 ; MIPS32: or [[T10]],[[T10]],[[T8]]
4617 ; MIPS32: move [[T0]],a1
4618 ; MIPS32: andi [[T0]],[[T0]],0xff
4619 ; MIPS32: move [[T4]],[[T1]]
4620 ; MIPS32: andi [[T4]],[[T4]],0xff
4621 ; MIPS32: sll [[T0]],[[T0]],0x18
4622 ; MIPS32: sll [[T4]],[[T4]],0x18
4623 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
4624 ; MIPS32: andi [[T0]],[[T0]],0xff
4625 ; MIPS32: srl [[T5]],[[T5]],0x8
4626 ; MIPS32: sll [[T5]],[[T5]],0x8
4627 ; MIPS32: or [[T0]],[[T0]],[[T5]]
4628 ; MIPS32: move [[T4]],a1
4629 ; MIPS32: srl [[T4]],[[T4]],0x8
4630 ; MIPS32: andi [[T4]],[[T4]],0xff
4631 ; MIPS32: move [[T5]],[[T1]]
4632 ; MIPS32: srl [[T5]],[[T5]],0x8
4633 ; MIPS32: andi [[T5]],[[T5]],0xff
4634 ; MIPS32: sll [[T4]],[[T4]],0x18
4635 ; MIPS32: sll [[T5]],[[T5]],0x18
4636 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
4637 ; MIPS32: andi [[T4]],[[T4]],0xff
4638 ; MIPS32: sll [[T4]],[[T4]],0x8
4639 ; MIPS32: lui [[T5]],0xffff
4640 ; MIPS32: ori [[T5]],[[T5]],0xff
4641 ; MIPS32: and [[T0]],[[T0]],[[T5]]
4642 ; MIPS32: or [[T4]],[[T4]],[[T0]]
4643 ; MIPS32: move [[T0]],a1
4644 ; MIPS32: srl [[T0]],[[T0]],0x10
4645 ; MIPS32: andi [[T0]],[[T0]],0xff
4646 ; MIPS32: move [[T5]],[[T1]]
4647 ; MIPS32: srl [[T5]],[[T5]],0x10
4648 ; MIPS32: andi [[T5]],[[T5]],0xff
4649 ; MIPS32: sll [[T0]],[[T0]],0x18
4650 ; MIPS32: sll [[T5]],[[T5]],0x18
4651 ; MIPS32: sltu [[T0]],[[T0]],[[T5]]
4195 ; MIPS32: andi [[T0]],[[T0]],0xff 4652 ; MIPS32: andi [[T0]],[[T0]],0xff
4196 ; MIPS32: sll [[T0]],[[T0]],0x10 4653 ; MIPS32: sll [[T0]],[[T0]],0x10
4197 ; MIPS32: lui [[T1]],0xff00 4654 ; MIPS32: lui [[T5]],0xff00
4198 ; MIPS32: ori [[T1]],[[T1]],0xffff 4655 ; MIPS32: ori [[T5]],[[T5]],0xffff
4199 ; MIPS32: and [[T2]],[[T2]],[[T1]] 4656 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4200 ; MIPS32: or [[T0]],[[T0]],[[T2]] 4657 ; MIPS32: or [[T0]],[[T0]],[[T4]]
4201 ; MIPS32: srl [[T3:.*]],a0,0x18 4658 ; MIPS32: srl [[T11:.*]],a1,0x18
4202 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 4659 ; MIPS32: srl [[T1]],[[T1]],0x18
4203 ; MIPS32: sll [[T3]],[[T3]],0x18 4660 ; MIPS32: sll [[T11]],[[T11]],0x18
4204 ; MIPS32: sll [[T4]],[[T4]],0x18 4661 ; MIPS32: sll [[T1]],[[T1]],0x18
4205 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 4662 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
4206 ; MIPS32: srl [[T3]],[[T3]],0x18 4663 ; MIPS32: srl [[T11]],[[T11]],0x18
4207 ; MIPS32: sll [[T0]],[[T0]],0x8 4664 ; MIPS32: sll [[T0]],[[T0]],0x8
4208 ; MIPS32: srl [[T0]],[[T0]],0x8 4665 ; MIPS32: srl [[T0]],[[T0]],0x8
4209 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 4666 ; MIPS32: or [[T11]],[[T11]],[[T0]]
4210 ; MIPS32: andi [[T4]],a1,0xff 4667 ; MIPS32: move [[T0]],a2
4211 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 4668 ; MIPS32: andi [[T0]],[[T0]],0xff
4212 ; MIPS32: sll [[T4]],[[T4]],0x18 4669 ; MIPS32: move [[T1]],[[T2]]
4670 ; MIPS32: andi [[T1]],[[T1]],0xff
4671 ; MIPS32: sll [[T0]],[[T0]],0x18
4672 ; MIPS32: sll [[T1]],[[T1]],0x18
4673 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
4674 ; MIPS32: andi [[T0]],[[T0]],0xff
4675 ; MIPS32: srl [[T6]],[[T6]],0x8
4676 ; MIPS32: sll [[T6]],[[T6]],0x8
4677 ; MIPS32: or [[T0]],[[T0]],[[T6]]
4678 ; MIPS32: move [[T1]],a2
4679 ; MIPS32: srl [[T1]],[[T1]],0x8
4680 ; MIPS32: andi [[T1]],[[T1]],0xff
4681 ; MIPS32: move [[T4]],[[T2]]
4682 ; MIPS32: srl [[T4]],[[T4]],0x8
4683 ; MIPS32: andi [[T4]],[[T4]],0xff
4684 ; MIPS32: sll [[T1]],[[T1]],0x18
4685 ; MIPS32: sll [[T4]],[[T4]],0x18
4686 ; MIPS32: sltu [[T1]],[[T1]],[[T4]]
4687 ; MIPS32: andi [[T1]],[[T1]],0xff
4688 ; MIPS32: sll [[T1]],[[T1]],0x8
4689 ; MIPS32: lui [[T4]],0xffff
4690 ; MIPS32: ori [[T4]],[[T4]],0xff
4691 ; MIPS32: and [[T0]],[[T0]],[[T4]]
4692 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4693 ; MIPS32: move [[T0]],a2
4694 ; MIPS32: srl [[T0]],[[T0]],0x10
4695 ; MIPS32: andi [[T0]],[[T0]],0xff
4696 ; MIPS32: move [[T4]],[[T2]]
4697 ; MIPS32: srl [[T4]],[[T4]],0x10
4698 ; MIPS32: andi [[T4]],[[T4]],0xff
4699 ; MIPS32: sll [[T0]],[[T0]],0x18
4700 ; MIPS32: sll [[T4]],[[T4]],0x18
4701 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
4702 ; MIPS32: andi [[T0]],[[T0]],0xff
4703 ; MIPS32: sll [[T0]],[[T0]],0x10
4704 ; MIPS32: lui [[T4]],0xff00
4705 ; MIPS32: ori [[T4]],[[T4]],0xffff
4706 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4707 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4708 ; MIPS32: srl [[T12:.*]],a2,0x18
4709 ; MIPS32: srl [[T2]],[[T2]],0x18
4710 ; MIPS32: sll [[T12]],[[T12]],0x18
4213 ; MIPS32: sll [[T2]],[[T2]],0x18 4711 ; MIPS32: sll [[T2]],[[T2]],0x18
4214 ; MIPS32: sltu [[T4]],[[T4]],[[T2]] 4712 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
4215 ; MIPS32: andi [[T4]],[[T4]],0xff 4713 ; MIPS32: srl [[T12]],[[T12]],0x18
4216 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 4714 ; MIPS32: sll [[T0]],[[T0]],0x8
4217 ; MIPS32: sll [[T5]],[[TV_E1]],0x8 4715 ; MIPS32: srl [[T0]],[[T0]],0x8
4218 ; MIPS32: or [[T4]],[[T4]],[[T5]] 4716 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4219 ; MIPS32: srl [[T2]],a1,0x8 4717 ; MIPS32: move [[T0]],a3
4718 ; MIPS32: andi [[T0]],[[T0]],0xff
4719 ; MIPS32: move [[T1]],[[T3]]
4720 ; MIPS32: andi [[T1]],[[T1]],0xff
4721 ; MIPS32: sll [[T0]],[[T0]],0x18
4722 ; MIPS32: sll [[T1]],[[T1]],0x18
4723 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
4724 ; MIPS32: andi [[T0]],[[T0]],0xff
4725 ; MIPS32: srl [[T7]],[[T7]],0x8
4726 ; MIPS32: sll [[T7]],[[T7]],0x8
4727 ; MIPS32: or [[T0]],[[T0]],[[T7]]
4728 ; MIPS32: move [[T1]],a3
4729 ; MIPS32: srl [[T1]],[[T1]],0x8
4730 ; MIPS32: andi [[T1]],[[T1]],0xff
4731 ; MIPS32: move [[T2]],[[T3]]
4732 ; MIPS32: srl [[T2]],[[T2]],0x8
4220 ; MIPS32: andi [[T2]],[[T2]],0xff 4733 ; MIPS32: andi [[T2]],[[T2]],0xff
4221 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 4734 ; MIPS32: sll [[T1]],[[T1]],0x18
4222 ; MIPS32: andi [[T5]],[[T5]],0xff
4223 ; MIPS32: sll [[T2]],[[T2]],0x18 4735 ; MIPS32: sll [[T2]],[[T2]],0x18
4224 ; MIPS32: sll [[T5]],[[T5]],0x18 4736 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
4225 ; MIPS32: sltu [[T2]],[[T2]],[[T5]] 4737 ; MIPS32: andi [[T1]],[[T1]],0xff
4226 ; MIPS32: andi [[T2]],[[T2]],0xff 4738 ; MIPS32: sll [[T1]],[[T1]],0x8
4227 ; MIPS32: sll [[T2]],[[T2]],0x8
4228 ; MIPS32: lui [[T5]],0xffff
4229 ; MIPS32: ori [[T5]],[[T5]],0xff
4230 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4231 ; MIPS32: or [[T2]],[[T2]],[[T4]]
4232 ; MIPS32: srl [[T4]],a1,0x10
4233 ; MIPS32: andi [[T4]],[[T4]],0xff
4234 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
4235 ; MIPS32: andi [[T5]],[[T5]],0xff
4236 ; MIPS32: sll [[T4]],[[T4]],0x18
4237 ; MIPS32: sll [[T5]],[[T5]],0x18
4238 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
4239 ; MIPS32: andi [[T4]],[[T4]],0xff
4240 ; MIPS32: sll [[T4]],[[T4]],0x10
4241 ; MIPS32: lui [[T5]],0xff00
4242 ; MIPS32: ori [[T5]],[[T5]],0xffff
4243 ; MIPS32: and [[T2]],[[T2]],[[T5]]
4244 ; MIPS32: or [[T4]],[[T4]],[[T2]]
4245 ; MIPS32: srl [[T6:.*]],a1,0x18
4246 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4247 ; MIPS32: sll [[T6]],[[T6]],0x18
4248 ; MIPS32: sll [[T7]],[[T7]],0x18
4249 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
4250 ; MIPS32: srl [[T6]],[[T6]],0x18
4251 ; MIPS32: sll [[T4]],[[T4]],0x8
4252 ; MIPS32: srl [[T4]],[[T4]],0x8
4253 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
4254 ; MIPS32: andi [[T4]],a2,0xff
4255 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
4256 ; MIPS32: sll [[T4]],[[T4]],0x18
4257 ; MIPS32: sll [[T7]],[[T7]],0x18
4258 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
4259 ; MIPS32: andi [[T4]],[[T4]],0xff
4260 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4261 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
4262 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4263 ; MIPS32: srl [[T7]],a2,0x8
4264 ; MIPS32: andi [[T7]],[[T7]],0xff
4265 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4266 ; MIPS32: andi [[T2]],[[T2]],0xff
4267 ; MIPS32: sll [[T7]],[[T7]],0x18
4268 ; MIPS32: sll [[T2]],[[T2]],0x18
4269 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
4270 ; MIPS32: andi [[T7]],[[T7]],0xff
4271 ; MIPS32: sll [[T7]],[[T7]],0x8
4272 ; MIPS32: lui [[T2]],0xffff 4739 ; MIPS32: lui [[T2]],0xffff
4273 ; MIPS32: ori [[T2]],[[T2]],0xff 4740 ; MIPS32: ori [[T2]],[[T2]],0xff
4274 ; MIPS32: and [[T4]],[[T4]],[[T2]] 4741 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4275 ; MIPS32: or [[T7]],[[T7]],[[T4]] 4742 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4276 ; MIPS32: srl [[T4]],a2,0x10 4743 ; MIPS32: move [[T0]],a3
4277 ; MIPS32: andi [[T4]],[[T4]],0xff 4744 ; MIPS32: srl [[T0]],[[T0]],0x10
4278 ; MIPS32: srl [[T2]],[[BV_E2]],0x10 4745 ; MIPS32: andi [[T0]],[[T0]],0xff
4746 ; MIPS32: move [[T2]],[[T3]]
4747 ; MIPS32: srl [[T2]],[[T2]],0x10
4279 ; MIPS32: andi [[T2]],[[T2]],0xff 4748 ; MIPS32: andi [[T2]],[[T2]],0xff
4280 ; MIPS32: sll [[T4]],[[T4]],0x18 4749 ; MIPS32: sll [[T0]],[[T0]],0x18
4281 ; MIPS32: sll [[T2]],[[T2]],0x18 4750 ; MIPS32: sll [[T2]],[[T2]],0x18
4282 ; MIPS32: sltu [[T4]],[[T4]],[[T2]] 4751 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
4283 ; MIPS32: andi [[T4]],[[T4]],0xff 4752 ; MIPS32: andi [[T0]],[[T0]],0xff
4284 ; MIPS32: sll [[T4]],[[T4]],0x10 4753 ; MIPS32: sll [[T0]],[[T0]],0x10
4285 ; MIPS32: lui [[T2]],0xff00 4754 ; MIPS32: lui [[T2]],0xff00
4286 ; MIPS32: ori [[T2]],[[T2]],0xffff 4755 ; MIPS32: ori [[T2]],[[T2]],0xffff
4287 ; MIPS32: and [[T7]],[[T7]],[[T2]] 4756 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4288 ; MIPS32: or [[T4]],[[T4]],[[T7]] 4757 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4289 ; MIPS32: srl [[T9:.*]],a2,0x18 4758 ; MIPS32: srl [[T13:.*]],a3,0x18
4290 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 4759 ; MIPS32: srl [[T3]],[[T3]],0x18
4291 ; MIPS32: sll [[T9]],[[T9]],0x18
4292 ; MIPS32: sll [[T10]],[[T10]],0x18
4293 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
4294 ; MIPS32: srl [[T9]],[[T9]],0x18
4295 ; MIPS32: sll [[T4]],[[T4]],0x8
4296 ; MIPS32: srl [[T4]],[[T4]],0x8
4297 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4298 ; MIPS32: andi [[T4]],a3,0xff
4299 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4300 ; MIPS32: sll [[T4]],[[T4]],0x18
4301 ; MIPS32: sll [[T7]],[[T7]],0x18
4302 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
4303 ; MIPS32: andi [[T4]],[[T4]],0xff
4304 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4305 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
4306 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4307 ; MIPS32: srl [[T7]],a3,0x8
4308 ; MIPS32: andi [[T7]],[[T7]],0xff
4309 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4310 ; MIPS32: andi [[T10]],[[T10]],0xff
4311 ; MIPS32: sll [[T7]],[[T7]],0x18
4312 ; MIPS32: sll [[T10]],[[T10]],0x18
4313 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
4314 ; MIPS32: andi [[T7]],[[T7]],0xff
4315 ; MIPS32: sll [[T7]],[[T7]],0x8
4316 ; MIPS32: lui [[T10]],0xffff
4317 ; MIPS32: ori [[T10]],[[T10]],0xff
4318 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4319 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4320 ; MIPS32: srl [[T4]],a3,0x10
4321 ; MIPS32: andi [[T4]],[[T4]],0xff
4322 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4323 ; MIPS32: andi [[T10]],[[T10]],0xff
4324 ; MIPS32: sll [[T4]],[[T4]],0x18
4325 ; MIPS32: sll [[T10]],[[T10]],0x18
4326 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4327 ; MIPS32: andi [[T4]],[[T4]],0xff
4328 ; MIPS32: sll [[T4]],[[T4]],0x10
4329 ; MIPS32: lui [[T10]],0xff00
4330 ; MIPS32: ori [[T10]],[[T10]],0xffff
4331 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4332 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4333 ; MIPS32: srl [[T12:.*]],a3,0x18
4334 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4335 ; MIPS32: sll [[T12]],[[T12]],0x18
4336 ; MIPS32: sll [[T13]],[[T13]],0x18 4760 ; MIPS32: sll [[T13]],[[T13]],0x18
4337 ; MIPS32: sltu [[T12]],[[T12]],[[T13]] 4761 ; MIPS32: sll [[T3]],[[T3]],0x18
4338 ; MIPS32: srl [[T12]],[[T12]],0x18 4762 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
4339 ; MIPS32: sll [[T4]],[[T4]],0x8 4763 ; MIPS32: srl [[T13]],[[T13]],0x18
4340 ; MIPS32: srl [[T4]],[[T4]],0x8 4764 ; MIPS32: sll [[T0]],[[T0]],0x8
4341 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 4765 ; MIPS32: srl [[T0]],[[T0]],0x8
4766 ; MIPS32: or [[T13]],[[T13]],[[T0]]
4767 ; MIPS32: move v0,[[T10]]
4768 ; MIPS32: move v1,[[T11]]
4769 ; MIPS32: move a0,[[T12]]
4770 ; MIPS32: move a1,[[T13]]
4342 } 4771 }
4343 4772
4344 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) { 4773 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) {
4345 entry: 4774 entry:
4346 %res = icmp eq <16 x i1> %a, %b 4775 %res = icmp eq <16 x i1> %a, %b
4347 ret <16 x i1> %res 4776 ret <16 x i1> %res
4348 ; CHECK-LABEL: test_icmp_v16i1_eq 4777 ; CHECK-LABEL: test_icmp_v16i1_eq
4349 ; CHECK: pcmpeqb 4778 ; CHECK: pcmpeqb
4350 4779
4351 ; MIPS32-LABEL: test_icmp_v16i1_eq 4780 ; MIPS32-LABEL: test_icmp_v16i1_eq
4352 ; MIPS32: lw [[BV_E0:.*]], 4781 ; MIPS32: lw [[T0:.*]],
4353 ; MIPS32: lw [[BV_E1:.*]], 4782 ; MIPS32: lw [[T1:.*]],
4354 ; MIPS32: lw [[BV_E2:.*]], 4783 ; MIPS32: lw [[T2:.*]],
4355 ; MIPS32: lw [[BV_E3:.*]], 4784 ; MIPS32: lw [[T3:.*]],
4356 ; MIPS32: move [[TV_E0:.*]],zero 4785 ; MIPS32: move [[T4:.*]],zero
4357 ; MIPS32: move [[TV_E1:.*]],zero 4786 ; MIPS32: move [[T5:.*]],zero
4358 ; MIPS32: move [[TV_E2:.*]],zero 4787 ; MIPS32: move [[T6:.*]],zero
4359 ; MIPS32: move [[TV_E3:.*]],zero 4788 ; MIPS32: move [[T7:.*]],zero
4360 ; MIPS32: andi [[T0:.*]],a0,0xff 4789 ; MIPS32: move [[T8:.*]],a0
4790 ; MIPS32: andi [[T8]],[[T8]],0xff
4791 ; MIPS32: andi [[T8]],[[T8]],0x1
4792 ; MIPS32: move [[T9:.*]],[[T0]]
4793 ; MIPS32: andi [[T9]],[[T9]],0xff
4794 ; MIPS32: andi [[T9]],[[T9]],0x1
4795 ; MIPS32: sll [[T8]],[[T8]],0x1f
4796 ; MIPS32: sll [[T9]],[[T9]],0x1f
4797 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
4798 ; MIPS32: sltiu [[T8]],[[T8]],1
4799 ; MIPS32: andi [[T8]],[[T8]],0xff
4800 ; MIPS32: srl [[T4]],[[T4]],0x8
4801 ; MIPS32: sll [[T4]],[[T4]],0x8
4802 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4803 ; MIPS32: move [[T4]],a0
4804 ; MIPS32: srl [[T4]],[[T4]],0x8
4805 ; MIPS32: andi [[T4]],[[T4]],0xff
4806 ; MIPS32: andi [[T4]],[[T4]],0x1
4807 ; MIPS32: move [[T9]],[[T0]]
4808 ; MIPS32: srl [[T9]],[[T9]],0x8
4809 ; MIPS32: andi [[T9]],[[T9]],0xff
4810 ; MIPS32: andi [[T9]],[[T9]],0x1
4811 ; MIPS32: sll [[T4]],[[T4]],0x1f
4812 ; MIPS32: sll [[T9]],[[T9]],0x1f
4813 ; MIPS32: xor [[T4]],[[T4]],[[T9]]
4814 ; MIPS32: sltiu [[T4]],[[T4]],1
4815 ; MIPS32: andi [[T4]],[[T4]],0xff
4816 ; MIPS32: sll [[T4]],[[T4]],0x8
4817 ; MIPS32: lui [[T9]],0xffff
4818 ; MIPS32: ori [[T9]],[[T9]],0xff
4819 ; MIPS32: and [[T8]],[[T8]],[[T9]]
4820 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4821 ; MIPS32: move [[T8]],a0
4822 ; MIPS32: srl [[T8]],[[T8]],0x10
4823 ; MIPS32: andi [[T8]],[[T8]],0xff
4824 ; MIPS32: andi [[T8]],[[T8]],0x1
4825 ; MIPS32: move [[T9]],[[T0]]
4826 ; MIPS32: srl [[T9]],[[T9]],0x10
4827 ; MIPS32: andi [[T9]],[[T9]],0xff
4828 ; MIPS32: andi [[T9]],[[T9]],0x1
4829 ; MIPS32: sll [[T8]],[[T8]],0x1f
4830 ; MIPS32: sll [[T9]],[[T9]],0x1f
4831 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
4832 ; MIPS32: sltiu [[T8]],[[T8]],1
4833 ; MIPS32: andi [[T8]],[[T8]],0xff
4834 ; MIPS32: sll [[T8]],[[T8]],0x10
4835 ; MIPS32: lui [[T9]],0xff00
4836 ; MIPS32: ori [[T9]],[[T9]],0xffff
4837 ; MIPS32: and [[T4]],[[T4]],[[T9]]
4838 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4839 ; MIPS32: srl [[T10:.*]],a0,0x18
4840 ; MIPS32: andi [[T10]],[[T10]],0x1
4841 ; MIPS32: srl [[T0]],[[T0]],0x18
4361 ; MIPS32: andi [[T0]],[[T0]],0x1 4842 ; MIPS32: andi [[T0]],[[T0]],0x1
4362 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 4843 ; MIPS32: sll [[T10]],[[T10]],0x1f
4363 ; MIPS32: andi [[T1]],[[T1]],0x1
4364 ; MIPS32: sll [[T0]],[[T0]],0x1f 4844 ; MIPS32: sll [[T0]],[[T0]],0x1f
4365 ; MIPS32: sll [[T1]],[[T1]],0x1f 4845 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
4366 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 4846 ; MIPS32: sltiu [[T10]],[[T10]],1
4847 ; MIPS32: srl [[T10]],[[T10]],0x18
4848 ; MIPS32: sll [[T8]],[[T8]],0x8
4849 ; MIPS32: srl [[T8]],[[T8]],0x8
4850 ; MIPS32: or [[T10]],[[T10]],[[T8]]
4851 ; MIPS32: move [[T0]],a1
4852 ; MIPS32: andi [[T0]],[[T0]],0xff
4853 ; MIPS32: andi [[T0]],[[T0]],0x1
4854 ; MIPS32: move [[T4]],[[T1]]
4855 ; MIPS32: andi [[T4]],[[T4]],0xff
4856 ; MIPS32: andi [[T4]],[[T4]],0x1
4857 ; MIPS32: sll [[T0]],[[T0]],0x1f
4858 ; MIPS32: sll [[T4]],[[T4]],0x1f
4859 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
4367 ; MIPS32: sltiu [[T0]],[[T0]],1 4860 ; MIPS32: sltiu [[T0]],[[T0]],1
4368 ; MIPS32: andi [[T0]],[[T0]],0xff 4861 ; MIPS32: andi [[T0]],[[T0]],0xff
4369 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 4862 ; MIPS32: srl [[T5]],[[T5]],0x8
4370 ; MIPS32: sll [[T2]],[[T2]],0x8
4371 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4372 ; MIPS32: srl [[T2]],a0,0x8
4373 ; MIPS32: andi [[T2]],[[T2]],0xff
4374 ; MIPS32: andi [[T2]],[[T2]],0x1
4375 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
4376 ; MIPS32: andi [[T1]],[[T1]],0xff
4377 ; MIPS32: andi [[T1]],[[T1]],0x1
4378 ; MIPS32: sll [[T2]],[[T2]],0x1f
4379 ; MIPS32: sll [[T1]],[[T1]],0x1f
4380 ; MIPS32: xor [[T2]],[[T2]],[[T1]]
4381 ; MIPS32: sltiu [[T2]],[[T2]],1
4382 ; MIPS32: andi [[T2]],[[T2]],0xff
4383 ; MIPS32: sll [[T2]],[[T2]],0x8
4384 ; MIPS32: lui [[T1]],0xffff
4385 ; MIPS32: ori [[T1]],[[T1]],0xff
4386 ; MIPS32: and [[T0]],[[T0]],[[T1]]
4387 ; MIPS32: or [[T2]],[[T2]],[[T0]]
4388 ; MIPS32: srl [[T0]],a0,0x10
4389 ; MIPS32: andi [[T0]],[[T0]],0xff
4390 ; MIPS32: andi [[T0]],[[T0]],0x1
4391 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4392 ; MIPS32: andi [[T1]],[[T1]],0xff
4393 ; MIPS32: andi [[T1]],[[T1]],0x1
4394 ; MIPS32: sll [[T0]],[[T0]],0x1f
4395 ; MIPS32: sll [[T1]],[[T1]],0x1f
4396 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4397 ; MIPS32: sltiu [[T0]],[[T0]],1
4398 ; MIPS32: andi [[T0]],[[T0]],0xff
4399 ; MIPS32: sll [[T0]],[[T0]],0x10
4400 ; MIPS32: lui [[T1]],0xff00
4401 ; MIPS32: ori [[T1]],[[T1]],0xffff
4402 ; MIPS32: and [[T2]],[[T2]],[[T1]]
4403 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4404 ; MIPS32: srl [[T3:.*]],a0,0x18
4405 ; MIPS32: andi [[T3]],[[T3]],0x1
4406 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4407 ; MIPS32: andi [[T4]],[[T4]],0x1
4408 ; MIPS32: sll [[T3]],[[T3]],0x1f
4409 ; MIPS32: sll [[T4]],[[T4]],0x1f
4410 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
4411 ; MIPS32: sltiu [[T3]],[[T3]],1
4412 ; MIPS32: srl [[T3]],[[T3]],0x18
4413 ; MIPS32: sll [[T0]],[[T0]],0x8
4414 ; MIPS32: srl [[T0]],[[T0]],0x8
4415 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
4416 ; MIPS32: andi [[T4]],a1,0xff
4417 ; MIPS32: andi [[T4]],[[T4]],0x1
4418 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4419 ; MIPS32: andi [[T2]],[[T2]],0x1
4420 ; MIPS32: sll [[T4]],[[T4]],0x1f
4421 ; MIPS32: sll [[T2]],[[T2]],0x1f
4422 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4423 ; MIPS32: sltiu [[T4]],[[T4]],1
4424 ; MIPS32: andi [[T4]],[[T4]],0xff
4425 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4426 ; MIPS32: sll [[T5]],[[T5]],0x8 4863 ; MIPS32: sll [[T5]],[[T5]],0x8
4427 ; MIPS32: or [[T4]],[[T4]],[[T5]] 4864 ; MIPS32: or [[T0]],[[T0]],[[T5]]
4428 ; MIPS32: srl [[T2]],a1,0x8 4865 ; MIPS32: move [[T4]],a1
4429 ; MIPS32: andi [[T2]],[[T2]],0xff 4866 ; MIPS32: srl [[T4]],[[T4]],0x8
4430 ; MIPS32: andi [[T2]],[[T2]],0x1
4431 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4432 ; MIPS32: andi [[T5]],[[T5]],0xff
4433 ; MIPS32: andi [[T5]],[[T5]],0x1
4434 ; MIPS32: sll [[T2]],[[T2]],0x1f
4435 ; MIPS32: sll [[T5]],[[T5]],0x1f
4436 ; MIPS32: xor [[T2]],[[T2]],[[T5]]
4437 ; MIPS32: sltiu [[T2]],[[T2]],1
4438 ; MIPS32: andi [[T2]],[[T2]],0xff
4439 ; MIPS32: sll [[T2]],[[T2]],0x8
4440 ; MIPS32: lui [[T5]],0xffff
4441 ; MIPS32: ori [[T5]],[[T5]],0xff
4442 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4443 ; MIPS32: or [[T2]],[[T2]],[[T4]]
4444 ; MIPS32: srl [[T4]],a1,0x10
4445 ; MIPS32: andi [[T4]],[[T4]],0xff 4867 ; MIPS32: andi [[T4]],[[T4]],0xff
4446 ; MIPS32: andi [[T4]],[[T4]],0x1 4868 ; MIPS32: andi [[T4]],[[T4]],0x1
4447 ; MIPS32: srl [[T5]],[[BV_E1]],0x10 4869 ; MIPS32: move [[T5]],[[T1]]
4870 ; MIPS32: srl [[T5]],[[T5]],0x8
4448 ; MIPS32: andi [[T5]],[[T5]],0xff 4871 ; MIPS32: andi [[T5]],[[T5]],0xff
4449 ; MIPS32: andi [[T5]],[[T5]],0x1 4872 ; MIPS32: andi [[T5]],[[T5]],0x1
4450 ; MIPS32: sll [[T4]],[[T4]],0x1f 4873 ; MIPS32: sll [[T4]],[[T4]],0x1f
4451 ; MIPS32: sll [[T5]],[[T5]],0x1f 4874 ; MIPS32: sll [[T5]],[[T5]],0x1f
4452 ; MIPS32: xor [[T4]],[[T4]],[[T5]] 4875 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
4453 ; MIPS32: sltiu [[T4]],[[T4]],1 4876 ; MIPS32: sltiu [[T4]],[[T4]],1
4454 ; MIPS32: andi [[T4]],[[T4]],0xff 4877 ; MIPS32: andi [[T4]],[[T4]],0xff
4455 ; MIPS32: sll [[T4]],[[T4]],0x10 4878 ; MIPS32: sll [[T4]],[[T4]],0x8
4879 ; MIPS32: lui [[T5]],0xffff
4880 ; MIPS32: ori [[T5]],[[T5]],0xff
4881 ; MIPS32: and [[T0]],[[T0]],[[T5]]
4882 ; MIPS32: or [[T4]],[[T4]],[[T0]]
4883 ; MIPS32: move [[T0]],a1
4884 ; MIPS32: srl [[T0]],[[T0]],0x10
4885 ; MIPS32: andi [[T0]],[[T0]],0xff
4886 ; MIPS32: andi [[T0]],[[T0]],0x1
4887 ; MIPS32: move [[T5]],[[T1]]
4888 ; MIPS32: srl [[T5]],[[T5]],0x10
4889 ; MIPS32: andi [[T5]],[[T5]],0xff
4890 ; MIPS32: andi [[T5]],[[T5]],0x1
4891 ; MIPS32: sll [[T0]],[[T0]],0x1f
4892 ; MIPS32: sll [[T5]],[[T5]],0x1f
4893 ; MIPS32: xor [[T0]],[[T0]],[[T5]]
4894 ; MIPS32: sltiu [[T0]],[[T0]],1
4895 ; MIPS32: andi [[T0]],[[T0]],0xff
4896 ; MIPS32: sll [[T0]],[[T0]],0x10
4456 ; MIPS32: lui [[T5]],0xff00 4897 ; MIPS32: lui [[T5]],0xff00
4457 ; MIPS32: ori [[T5]],[[T5]],0xffff 4898 ; MIPS32: ori [[T5]],[[T5]],0xffff
4458 ; MIPS32: and [[T2]],[[T2]],[[T5]] 4899 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4459 ; MIPS32: or [[T4]],[[T4]],[[T2]] 4900 ; MIPS32: or [[T0]],[[T0]],[[T4]]
4460 ; MIPS32: srl [[T6:.*]],a1,0x18 4901 ; MIPS32: srl [[T11:.*]],a1,0x18
4461 ; MIPS32: andi [[T6]],[[T6]],0x1 4902 ; MIPS32: andi [[T11]],[[T11]],0x1
4462 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 4903 ; MIPS32: srl [[T1]],[[T1]],0x18
4463 ; MIPS32: andi [[T7]],[[T7]],0x1 4904 ; MIPS32: andi [[T1]],[[T1]],0x1
4464 ; MIPS32: sll [[T6]],[[T6]],0x1f 4905 ; MIPS32: sll [[T11]],[[T11]],0x1f
4465 ; MIPS32: sll [[T7]],[[T7]],0x1f 4906 ; MIPS32: sll [[T1]],[[T1]],0x1f
4466 ; MIPS32: xor [[T6]],[[T6]],[[T7]] 4907 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
4467 ; MIPS32: sltiu [[T6]],[[T6]],1 4908 ; MIPS32: sltiu [[T11]],[[T11]],1
4468 ; MIPS32: srl [[T6]],[[T6]],0x18 4909 ; MIPS32: srl [[T11]],[[T11]],0x18
4469 ; MIPS32: sll [[T4]],[[T4]],0x8 4910 ; MIPS32: sll [[T0]],[[T0]],0x8
4911 ; MIPS32: srl [[T0]],[[T0]],0x8
4912 ; MIPS32: or [[T11]],[[T11]],[[T0]]
4913 ; MIPS32: move [[T0]],a2
4914 ; MIPS32: andi [[T0]],[[T0]],0xff
4915 ; MIPS32: andi [[T0]],[[T0]],0x1
4916 ; MIPS32: move [[T1]],[[T2]]
4917 ; MIPS32: andi [[T1]],[[T1]],0xff
4918 ; MIPS32: andi [[T1]],[[T1]],0x1
4919 ; MIPS32: sll [[T0]],[[T0]],0x1f
4920 ; MIPS32: sll [[T1]],[[T1]],0x1f
4921 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4922 ; MIPS32: sltiu [[T0]],[[T0]],1
4923 ; MIPS32: andi [[T0]],[[T0]],0xff
4924 ; MIPS32: srl [[T6]],[[T6]],0x8
4925 ; MIPS32: sll [[T6]],[[T6]],0x8
4926 ; MIPS32: or [[T0]],[[T0]],[[T6]]
4927 ; MIPS32: move [[T1]],a2
4928 ; MIPS32: srl [[T1]],[[T1]],0x8
4929 ; MIPS32: andi [[T1]],[[T1]],0xff
4930 ; MIPS32: andi [[T1]],[[T1]],0x1
4931 ; MIPS32: move [[T4]],[[T2]]
4470 ; MIPS32: srl [[T4]],[[T4]],0x8 4932 ; MIPS32: srl [[T4]],[[T4]],0x8
4471 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] 4933 ; MIPS32: andi [[T4]],[[T4]],0xff
4472 ; MIPS32: andi [[T4]],a2,0xff 4934 ; MIPS32: andi [[T4]],[[T4]],0x1
4473 ; MIPS32: andi [[T4]],[[T4]],0x1 4935 ; MIPS32: sll [[T1]],[[T1]],0x1f
4474 ; MIPS32: andi [[T7]],[[BV_E2]],0xff 4936 ; MIPS32: sll [[T4]],[[T4]],0x1f
4475 ; MIPS32: andi [[T7]],[[T7]],0x1 4937 ; MIPS32: xor [[T1]],[[T1]],[[T4]]
4476 ; MIPS32: sll [[T4]],[[T4]],0x1f 4938 ; MIPS32: sltiu [[T1]],[[T1]],1
4477 ; MIPS32: sll [[T7]],[[T7]],0x1f 4939 ; MIPS32: andi [[T1]],[[T1]],0xff
4478 ; MIPS32: xor [[T4]],[[T4]],[[T7]] 4940 ; MIPS32: sll [[T1]],[[T1]],0x8
4479 ; MIPS32: sltiu [[T4]],[[T4]],1 4941 ; MIPS32: lui [[T4]],0xffff
4480 ; MIPS32: andi [[T4]],[[T4]],0xff 4942 ; MIPS32: ori [[T4]],[[T4]],0xff
4481 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 4943 ; MIPS32: and [[T0]],[[T0]],[[T4]]
4482 ; MIPS32: sll [[T8]],[[T8]],0x8 4944 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4483 ; MIPS32: or [[T4]],[[T4]],[[T8]] 4945 ; MIPS32: move [[T0]],a2
4484 ; MIPS32: srl [[T7]],a2,0x8 4946 ; MIPS32: srl [[T0]],[[T0]],0x10
4485 ; MIPS32: andi [[T7]],[[T7]],0xff 4947 ; MIPS32: andi [[T0]],[[T0]],0xff
4486 ; MIPS32: andi [[T7]],[[T7]],0x1 4948 ; MIPS32: andi [[T0]],[[T0]],0x1
4487 ; MIPS32: srl [[T2]],[[BV_E2]],0x8 4949 ; MIPS32: move [[T4]],[[T2]]
4950 ; MIPS32: srl [[T4]],[[T4]],0x10
4951 ; MIPS32: andi [[T4]],[[T4]],0xff
4952 ; MIPS32: andi [[T4]],[[T4]],0x1
4953 ; MIPS32: sll [[T0]],[[T0]],0x1f
4954 ; MIPS32: sll [[T4]],[[T4]],0x1f
4955 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
4956 ; MIPS32: sltiu [[T0]],[[T0]],1
4957 ; MIPS32: andi [[T0]],[[T0]],0xff
4958 ; MIPS32: sll [[T0]],[[T0]],0x10
4959 ; MIPS32: lui [[T4]],0xff00
4960 ; MIPS32: ori [[T4]],[[T4]],0xffff
4961 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4962 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4963 ; MIPS32: srl [[T12:.*]],a2,0x18
4964 ; MIPS32: andi [[T12]],[[T12]],0x1
4965 ; MIPS32: srl [[T2]],[[T2]],0x18
4966 ; MIPS32: andi [[T2]],[[T2]],0x1
4967 ; MIPS32: sll [[T12]],[[T12]],0x1f
4968 ; MIPS32: sll [[T2]],[[T2]],0x1f
4969 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
4970 ; MIPS32: sltiu [[T12]],[[T12]],1
4971 ; MIPS32: srl [[T12]],[[T12]],0x18
4972 ; MIPS32: sll [[T0]],[[T0]],0x8
4973 ; MIPS32: srl [[T0]],[[T0]],0x8
4974 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4975 ; MIPS32: move [[T0]],a3
4976 ; MIPS32: andi [[T0]],[[T0]],0xff
4977 ; MIPS32: andi [[T0]],[[T0]],0x1
4978 ; MIPS32: move [[T1]],[[T3]]
4979 ; MIPS32: andi [[T1]],[[T1]],0xff
4980 ; MIPS32: andi [[T1]],[[T1]],0x1
4981 ; MIPS32: sll [[T0]],[[T0]],0x1f
4982 ; MIPS32: sll [[T1]],[[T1]],0x1f
4983 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4984 ; MIPS32: sltiu [[T0]],[[T0]],1
4985 ; MIPS32: andi [[T0]],[[T0]],0xff
4986 ; MIPS32: srl [[T7]],[[T7]],0x8
4987 ; MIPS32: sll [[T7]],[[T7]],0x8
4988 ; MIPS32: or [[T0]],[[T0]],[[T7]]
4989 ; MIPS32: move [[T1]],a3
4990 ; MIPS32: srl [[T1]],[[T1]],0x8
4991 ; MIPS32: andi [[T1]],[[T1]],0xff
4992 ; MIPS32: andi [[T1]],[[T1]],0x1
4993 ; MIPS32: move [[T2]],[[T3]]
4994 ; MIPS32: srl [[T2]],[[T2]],0x8
4488 ; MIPS32: andi [[T2]],[[T2]],0xff 4995 ; MIPS32: andi [[T2]],[[T2]],0xff
4489 ; MIPS32: andi [[T2]],[[T2]],0x1 4996 ; MIPS32: andi [[T2]],[[T2]],0x1
4490 ; MIPS32: sll [[T7]],[[T7]],0x1f 4997 ; MIPS32: sll [[T1]],[[T1]],0x1f
4491 ; MIPS32: sll [[T2]],[[T2]],0x1f 4998 ; MIPS32: sll [[T2]],[[T2]],0x1f
4492 ; MIPS32: xor [[T7]],[[T7]],[[T2]] 4999 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
4493 ; MIPS32: sltiu [[T7]],[[T7]],1 5000 ; MIPS32: sltiu [[T1]],[[T1]],1
4494 ; MIPS32: andi [[T7]],[[T7]],0xff 5001 ; MIPS32: andi [[T1]],[[T1]],0xff
4495 ; MIPS32: sll [[T7]],[[T7]],0x8 5002 ; MIPS32: sll [[T1]],[[T1]],0x8
4496 ; MIPS32: lui [[T2]],0xffff 5003 ; MIPS32: lui [[T2]],0xffff
4497 ; MIPS32: ori [[T2]],[[T2]],0xff 5004 ; MIPS32: ori [[T2]],[[T2]],0xff
4498 ; MIPS32: and [[T4]],[[T4]],[[T2]] 5005 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4499 ; MIPS32: or [[T7]],[[T7]],[[T4]] 5006 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4500 ; MIPS32: srl [[T4]],a2,0x10 5007 ; MIPS32: move [[T0]],a3
4501 ; MIPS32: andi [[T4]],[[T4]],0xff 5008 ; MIPS32: srl [[T0]],[[T0]],0x10
4502 ; MIPS32: andi [[T4]],[[T4]],0x1 5009 ; MIPS32: andi [[T0]],[[T0]],0xff
4503 ; MIPS32: srl [[T2]],[[BV_E2]],0x10 5010 ; MIPS32: andi [[T0]],[[T0]],0x1
5011 ; MIPS32: move [[T2]],[[T3]]
5012 ; MIPS32: srl [[T2]],[[T2]],0x10
4504 ; MIPS32: andi [[T2]],[[T2]],0xff 5013 ; MIPS32: andi [[T2]],[[T2]],0xff
4505 ; MIPS32: andi [[T2]],[[T2]],0x1 5014 ; MIPS32: andi [[T2]],[[T2]],0x1
4506 ; MIPS32: sll [[T4]],[[T4]],0x1f 5015 ; MIPS32: sll [[T0]],[[T0]],0x1f
4507 ; MIPS32: sll [[T2]],[[T2]],0x1f 5016 ; MIPS32: sll [[T2]],[[T2]],0x1f
4508 ; MIPS32: xor [[T4]],[[T4]],[[T2]] 5017 ; MIPS32: xor [[T0]],[[T0]],[[T2]]
4509 ; MIPS32: sltiu [[T4]],[[T4]],1 5018 ; MIPS32: sltiu [[T0]],[[T0]],1
4510 ; MIPS32: andi [[T4]],[[T4]],0xff 5019 ; MIPS32: andi [[T0]],[[T0]],0xff
4511 ; MIPS32: sll [[T4]],[[T4]],0x10 5020 ; MIPS32: sll [[T0]],[[T0]],0x10
4512 ; MIPS32: lui [[T2]],0xff00 5021 ; MIPS32: lui [[T2]],0xff00
4513 ; MIPS32: ori [[T2]],[[T2]],0xffff 5022 ; MIPS32: ori [[T2]],[[T2]],0xffff
4514 ; MIPS32: and [[T7]],[[T7]],[[T2]] 5023 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4515 ; MIPS32: or [[T4]],[[T4]],[[T7]] 5024 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4516 ; MIPS32: srl [[T9:.*]],a2,0x18 5025 ; MIPS32: srl [[T13:.*]],a3,0x18
4517 ; MIPS32: andi [[T9]],[[T9]],0x1
4518 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4519 ; MIPS32: andi [[T10]],[[T10]],0x1
4520 ; MIPS32: sll [[T9]],[[T9]],0x1f
4521 ; MIPS32: sll [[T10]],[[T10]],0x1f
4522 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
4523 ; MIPS32: sltiu [[T9]],[[T9]],1
4524 ; MIPS32: srl [[T9]],[[T9]],0x18
4525 ; MIPS32: sll [[T4]],[[T4]],0x8
4526 ; MIPS32: srl [[T4]],[[T4]],0x8
4527 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4528 ; MIPS32: andi [[T4]],a3,0xff
4529 ; MIPS32: andi [[T4]],[[T4]],0x1
4530 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4531 ; MIPS32: andi [[T7]],[[T7]],0x1
4532 ; MIPS32: sll [[T4]],[[T4]],0x1f
4533 ; MIPS32: sll [[T7]],[[T7]],0x1f
4534 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4535 ; MIPS32: sltiu [[T4]],[[T4]],1
4536 ; MIPS32: andi [[T4]],[[T4]],0xff
4537 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4538 ; MIPS32: sll [[T11]],[[T11]],0x8
4539 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4540 ; MIPS32: srl [[T7]],a3,0x8
4541 ; MIPS32: andi [[T7]],[[T7]],0xff
4542 ; MIPS32: andi [[T7]],[[T7]],0x1
4543 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4544 ; MIPS32: andi [[T10]],[[T10]],0xff
4545 ; MIPS32: andi [[T10]],[[T10]],0x1
4546 ; MIPS32: sll [[T7]],[[T7]],0x1f
4547 ; MIPS32: sll [[T10]],[[T10]],0x1f
4548 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
4549 ; MIPS32: sltiu [[T7]],[[T7]],1
4550 ; MIPS32: andi [[T7]],[[T7]],0xff
4551 ; MIPS32: sll [[T7]],[[T7]],0x8
4552 ; MIPS32: lui [[T10]],0xffff
4553 ; MIPS32: ori [[T10]],[[T10]],0xff
4554 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4555 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4556 ; MIPS32: srl [[T4]],a3,0x10
4557 ; MIPS32: andi [[T4]],[[T4]],0xff
4558 ; MIPS32: andi [[T4]],[[T4]],0x1
4559 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4560 ; MIPS32: andi [[T10]],[[T10]],0xff
4561 ; MIPS32: andi [[T10]],[[T10]],0x1
4562 ; MIPS32: sll [[T4]],[[T4]],0x1f
4563 ; MIPS32: sll [[T10]],[[T10]],0x1f
4564 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
4565 ; MIPS32: sltiu [[T4]],[[T4]],1
4566 ; MIPS32: andi [[T4]],[[T4]],0xff
4567 ; MIPS32: sll [[T4]],[[T4]],0x10
4568 ; MIPS32: lui [[T10]],0xff00
4569 ; MIPS32: ori [[T10]],[[T10]],0xffff
4570 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4571 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4572 ; MIPS32: srl [[T12:.*]],a3,0x18
4573 ; MIPS32: andi [[T12]],[[T12]],0x1
4574 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4575 ; MIPS32: andi [[T13]],[[T13]],0x1 5026 ; MIPS32: andi [[T13]],[[T13]],0x1
4576 ; MIPS32: sll [[T12]],[[T12]],0x1f 5027 ; MIPS32: srl [[T3]],[[T3]],0x18
5028 ; MIPS32: andi [[T3]],[[T3]],0x1
4577 ; MIPS32: sll [[T13]],[[T13]],0x1f 5029 ; MIPS32: sll [[T13]],[[T13]],0x1f
4578 ; MIPS32: xor [[T12]],[[T12]],[[T13]] 5030 ; MIPS32: sll [[T3]],[[T3]],0x1f
4579 ; MIPS32: sltiu [[T12]],[[T12]],1 5031 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
4580 ; MIPS32: srl [[T12]],[[T12]],0x18 5032 ; MIPS32: sltiu [[T13]],[[T13]],1
4581 ; MIPS32: sll [[T4]],[[T4]],0x8 5033 ; MIPS32: srl [[T13]],[[T13]],0x18
4582 ; MIPS32: srl [[T4]],[[T4]],0x8 5034 ; MIPS32: sll [[T0]],[[T0]],0x8
4583 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 5035 ; MIPS32: srl [[T0]],[[T0]],0x8
5036 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5037 ; MIPS32: move v0,[[T10]]
5038 ; MIPS32: move v1,[[T11]]
5039 ; MIPS32: move a0,[[T12]]
5040 ; MIPS32: move a1,[[T13]]
4584 } 5041 }
4585 5042
4586 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) { 5043 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) {
4587 entry: 5044 entry:
4588 %res = icmp ne <16 x i1> %a, %b 5045 %res = icmp ne <16 x i1> %a, %b
4589 ret <16 x i1> %res 5046 ret <16 x i1> %res
4590 ; CHECK-LABEL: test_icmp_v16i1_ne 5047 ; CHECK-LABEL: test_icmp_v16i1_ne
4591 ; CHECK: pcmpeqb 5048 ; CHECK: pcmpeqb
4592 ; CHECK: pxor 5049 ; CHECK: pxor
4593 5050
4594 ; MIPS32-LABEL: test_icmp_v16i1_ne 5051 ; MIPS32-LABEL: test_icmp_v16i1_ne
4595 ; MIPS32: lw [[BV_E0:.*]], 5052 ; MIPS32: lw [[T0:.*]],
4596 ; MIPS32: lw [[BV_E1:.*]], 5053 ; MIPS32: lw [[T1:.*]],
4597 ; MIPS32: lw [[BV_E2:.*]], 5054 ; MIPS32: lw [[T2:.*]],
4598 ; MIPS32: lw [[BV_E3:.*]], 5055 ; MIPS32: lw [[T3:.*]],
4599 ; MIPS32: move [[TV_E0:.*]],zero 5056 ; MIPS32: move [[T4:.*]],zero
4600 ; MIPS32: move [[TV_E1:.*]],zero 5057 ; MIPS32: move [[T5:.*]],zero
4601 ; MIPS32: move [[TV_E2:.*]],zero 5058 ; MIPS32: move [[T6:.*]],zero
4602 ; MIPS32: move [[TV_E3:.*]],zero 5059 ; MIPS32: move [[T7:.*]],zero
4603 ; MIPS32: andi [[T0:.*]],a0,0xff 5060 ; MIPS32: move [[T8:.*]],a0
4604 ; MIPS32: andi [[T0]],[[T0]],0x1 5061 ; MIPS32: andi [[T8]],[[T8]],0xff
4605 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 5062 ; MIPS32: andi [[T8]],[[T8]],0x1
4606 ; MIPS32: andi [[T1]],[[T1]],0x1 5063 ; MIPS32: move [[T9:.*]],[[T0]]
4607 ; MIPS32: sll [[T0]],[[T0]],0x1f 5064 ; MIPS32: andi [[T9]],[[T9]],0xff
4608 ; MIPS32: sll [[T1]],[[T1]],0x1f 5065 ; MIPS32: andi [[T9]],[[T9]],0x1
4609 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 5066 ; MIPS32: sll [[T8]],[[T8]],0x1f
5067 ; MIPS32: sll [[T9]],[[T9]],0x1f
5068 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
5069 ; MIPS32: sltu [[T8]],zero,[[T8]]
5070 ; MIPS32: andi [[T8]],[[T8]],0xff
5071 ; MIPS32: srl [[T4]],[[T4]],0x8
5072 ; MIPS32: sll [[T4]],[[T4]],0x8
5073 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5074 ; MIPS32: move [[T4]],a0
5075 ; MIPS32: srl [[T4]],[[T4]],0x8
5076 ; MIPS32: andi [[T4]],[[T4]],0xff
5077 ; MIPS32: andi [[T4]],[[T4]],0x1
5078 ; MIPS32: move [[T9]],[[T0]]
5079 ; MIPS32: srl [[T9]],[[T9]],0x8
5080 ; MIPS32: andi [[T9]],[[T9]],0xff
5081 ; MIPS32: andi [[T9]],[[T9]],0x1
5082 ; MIPS32: sll [[T4]],[[T4]],0x1f
5083 ; MIPS32: sll [[T9]],[[T9]],0x1f
5084 ; MIPS32: xor [[T4]],[[T4]],[[T9]]
5085 ; MIPS32: sltu [[T4]],zero,[[T4]]
5086 ; MIPS32: andi [[T4]],[[T4]],0xff
5087 ; MIPS32: sll [[T4]],[[T4]],0x8
5088 ; MIPS32: lui [[T9]],0xffff
5089 ; MIPS32: ori [[T9]],[[T9]],0xff
5090 ; MIPS32: and [[T8]],[[T8]],[[T9]]
5091 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5092 ; MIPS32: move [[T8]],a0
5093 ; MIPS32: srl [[T8]],[[T8]],0x10
5094 ; MIPS32: andi [[T8]],[[T8]],0xff
5095 ; MIPS32: andi [[T8]],[[T8]],0x1
5096 ; MIPS32: move [[T9]],[[T0]]
5097 ; MIPS32: srl [[T9]],[[T9]],0x10
5098 ; MIPS32: andi [[T9]],[[T9]],0xff
5099 ; MIPS32: andi [[T9]],[[T9]],0x1
5100 ; MIPS32: sll [[T8]],[[T8]],0x1f
5101 ; MIPS32: sll [[T9]],[[T9]],0x1f
5102 ; MIPS32: xor [[T8]],[[T8]],[[T9]]
5103 ; MIPS32: sltu [[T8]],zero,[[T8]]
5104 ; MIPS32: andi [[T8]],[[T8]],0xff
5105 ; MIPS32: sll [[T8]],[[T8]],0x10
5106 ; MIPS32: lui [[T9]],0xff00
5107 ; MIPS32: ori [[T9]],[[T9]],0xffff
5108 ; MIPS32: and [[T4]],[[T4]],[[T9]]
5109 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5110 ; MIPS32: srl [[T10:.*]],a0,0x18
5111 ; MIPS32: andi [[T10]],[[T10]],0x1
5112 ; MIPS32: srl [[T0]],[[T0]],0x18
5113 ; MIPS32: andi [[T0]],[[T0]],0x1
5114 ; MIPS32: sll [[T10]],[[T10]],0x1f
5115 ; MIPS32: sll [[T0]],[[T0]],0x1f
5116 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
5117 ; MIPS32: sltu [[T10]],zero,[[T10]]
5118 ; MIPS32: srl [[T10]],[[T10]],0x18
5119 ; MIPS32: sll [[T8]],[[T8]],0x8
5120 ; MIPS32: srl [[T8]],[[T8]],0x8
5121 ; MIPS32: or [[T10]],[[T10]],[[T8]]
5122 ; MIPS32: move [[T0]],a1
5123 ; MIPS32: andi [[T0]],[[T0]],0xff
5124 ; MIPS32: andi [[T0]],[[T0]],0x1
5125 ; MIPS32: move [[T4]],[[T1]]
5126 ; MIPS32: andi [[T4]],[[T4]],0xff
5127 ; MIPS32: andi [[T4]],[[T4]],0x1
5128 ; MIPS32: sll [[T0]],[[T0]],0x1f
5129 ; MIPS32: sll [[T4]],[[T4]],0x1f
5130 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
4610 ; MIPS32: sltu [[T0]],zero,[[T0]] 5131 ; MIPS32: sltu [[T0]],zero,[[T0]]
4611 ; MIPS32: andi [[T0]],[[T0]],0xff 5132 ; MIPS32: andi [[T0]],[[T0]],0xff
4612 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 5133 ; MIPS32: srl [[T5]],[[T5]],0x8
4613 ; MIPS32: sll [[T2]],[[T2]],0x8 5134 ; MIPS32: sll [[T5]],[[T5]],0x8
4614 ; MIPS32: or [[T0]],[[T0]],[[T2]] 5135 ; MIPS32: or [[T0]],[[T0]],[[T5]]
4615 ; MIPS32: srl [[T2]],a0,0x8 5136 ; MIPS32: move [[T4]],a1
4616 ; MIPS32: andi [[T2]],[[T2]],0xff 5137 ; MIPS32: srl [[T4]],[[T4]],0x8
4617 ; MIPS32: andi [[T2]],[[T2]],0x1 5138 ; MIPS32: andi [[T4]],[[T4]],0xff
4618 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 5139 ; MIPS32: andi [[T4]],[[T4]],0x1
4619 ; MIPS32: andi [[T1]],[[T1]],0xff 5140 ; MIPS32: move [[T5]],[[T1]]
4620 ; MIPS32: andi [[T1]],[[T1]],0x1 5141 ; MIPS32: srl [[T5]],[[T5]],0x8
4621 ; MIPS32: sll [[T2]],[[T2]],0x1f 5142 ; MIPS32: andi [[T5]],[[T5]],0xff
4622 ; MIPS32: sll [[T1]],[[T1]],0x1f 5143 ; MIPS32: andi [[T5]],[[T5]],0x1
4623 ; MIPS32: xor [[T2]],[[T2]],[[T1]] 5144 ; MIPS32: sll [[T4]],[[T4]],0x1f
4624 ; MIPS32: sltu [[T2]],zero,[[T2]] 5145 ; MIPS32: sll [[T5]],[[T5]],0x1f
4625 ; MIPS32: andi [[T2]],[[T2]],0xff 5146 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
4626 ; MIPS32: sll [[T2]],[[T2]],0x8 5147 ; MIPS32: sltu [[T4]],zero,[[T4]]
4627 ; MIPS32: lui [[T1]],0xffff 5148 ; MIPS32: andi [[T4]],[[T4]],0xff
4628 ; MIPS32: ori [[T1]],[[T1]],0xff 5149 ; MIPS32: sll [[T4]],[[T4]],0x8
4629 ; MIPS32: and [[T0]],[[T0]],[[T1]] 5150 ; MIPS32: lui [[T5]],0xffff
4630 ; MIPS32: or [[T2]],[[T2]],[[T0]] 5151 ; MIPS32: ori [[T5]],[[T5]],0xff
4631 ; MIPS32: srl [[T0]],a0,0x10 5152 ; MIPS32: and [[T0]],[[T0]],[[T5]]
4632 ; MIPS32: andi [[T0]],[[T0]],0xff 5153 ; MIPS32: or [[T4]],[[T4]],[[T0]]
4633 ; MIPS32: andi [[T0]],[[T0]],0x1 5154 ; MIPS32: move [[T0]],a1
4634 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 5155 ; MIPS32: srl [[T0]],[[T0]],0x10
4635 ; MIPS32: andi [[T1]],[[T1]],0xff 5156 ; MIPS32: andi [[T0]],[[T0]],0xff
4636 ; MIPS32: andi [[T1]],[[T1]],0x1 5157 ; MIPS32: andi [[T0]],[[T0]],0x1
4637 ; MIPS32: sll [[T0]],[[T0]],0x1f 5158 ; MIPS32: move [[T5]],[[T1]]
5159 ; MIPS32: srl [[T5]],[[T5]],0x10
5160 ; MIPS32: andi [[T5]],[[T5]],0xff
5161 ; MIPS32: andi [[T5]],[[T5]],0x1
5162 ; MIPS32: sll [[T0]],[[T0]],0x1f
5163 ; MIPS32: sll [[T5]],[[T5]],0x1f
5164 ; MIPS32: xor [[T0]],[[T0]],[[T5]]
5165 ; MIPS32: sltu [[T0]],zero,[[T0]]
5166 ; MIPS32: andi [[T0]],[[T0]],0xff
5167 ; MIPS32: sll [[T0]],[[T0]],0x10
5168 ; MIPS32: lui [[T5]],0xff00
5169 ; MIPS32: ori [[T5]],[[T5]],0xffff
5170 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5171 ; MIPS32: or [[T0]],[[T0]],[[T4]]
5172 ; MIPS32: srl [[T11:.*]],a1,0x18
5173 ; MIPS32: andi [[T11]],[[T11]],0x1
5174 ; MIPS32: srl [[T1]],[[T1]],0x18
5175 ; MIPS32: andi [[T1]],[[T1]],0x1
5176 ; MIPS32: sll [[T11]],[[T11]],0x1f
5177 ; MIPS32: sll [[T1]],[[T1]],0x1f
5178 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
5179 ; MIPS32: sltu [[T11]],zero,[[T11]]
5180 ; MIPS32: srl [[T11]],[[T11]],0x18
5181 ; MIPS32: sll [[T0]],[[T0]],0x8
5182 ; MIPS32: srl [[T0]],[[T0]],0x8
5183 ; MIPS32: or [[T11]],[[T11]],[[T0]]
5184 ; MIPS32: move [[T0]],a2
5185 ; MIPS32: andi [[T0]],[[T0]],0xff
5186 ; MIPS32: andi [[T0]],[[T0]],0x1
5187 ; MIPS32: move [[T1]],[[T2]]
5188 ; MIPS32: andi [[T1]],[[T1]],0xff
5189 ; MIPS32: andi [[T1]],[[T1]],0x1
5190 ; MIPS32: sll [[T0]],[[T0]],0x1f
4638 ; MIPS32: sll [[T1]],[[T1]],0x1f 5191 ; MIPS32: sll [[T1]],[[T1]],0x1f
4639 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 5192 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4640 ; MIPS32: sltu [[T0]],zero,[[T0]] 5193 ; MIPS32: sltu [[T0]],zero,[[T0]]
4641 ; MIPS32: andi [[T0]],[[T0]],0xff 5194 ; MIPS32: andi [[T0]],[[T0]],0xff
5195 ; MIPS32: srl [[T6]],[[T6]],0x8
5196 ; MIPS32: sll [[T6]],[[T6]],0x8
5197 ; MIPS32: or [[T0]],[[T0]],[[T6]]
5198 ; MIPS32: move [[T1]],a2
5199 ; MIPS32: srl [[T1]],[[T1]],0x8
5200 ; MIPS32: andi [[T1]],[[T1]],0xff
5201 ; MIPS32: andi [[T1]],[[T1]],0x1
5202 ; MIPS32: move [[T4]],[[T2]]
5203 ; MIPS32: srl [[T4]],[[T4]],0x8
5204 ; MIPS32: andi [[T4]],[[T4]],0xff
5205 ; MIPS32: andi [[T4]],[[T4]],0x1
5206 ; MIPS32: sll [[T1]],[[T1]],0x1f
5207 ; MIPS32: sll [[T4]],[[T4]],0x1f
5208 ; MIPS32: xor [[T1]],[[T1]],[[T4]]
5209 ; MIPS32: sltu [[T1]],zero,[[T1]]
5210 ; MIPS32: andi [[T1]],[[T1]],0xff
5211 ; MIPS32: sll [[T1]],[[T1]],0x8
5212 ; MIPS32: lui [[T4]],0xffff
5213 ; MIPS32: ori [[T4]],[[T4]],0xff
5214 ; MIPS32: and [[T0]],[[T0]],[[T4]]
5215 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5216 ; MIPS32: move [[T0]],a2
5217 ; MIPS32: srl [[T0]],[[T0]],0x10
5218 ; MIPS32: andi [[T0]],[[T0]],0xff
5219 ; MIPS32: andi [[T0]],[[T0]],0x1
5220 ; MIPS32: move [[T4]],[[T2]]
5221 ; MIPS32: srl [[T4]],[[T4]],0x10
5222 ; MIPS32: andi [[T4]],[[T4]],0xff
5223 ; MIPS32: andi [[T4]],[[T4]],0x1
5224 ; MIPS32: sll [[T0]],[[T0]],0x1f
5225 ; MIPS32: sll [[T4]],[[T4]],0x1f
5226 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
5227 ; MIPS32: sltu [[T0]],zero,[[T0]]
5228 ; MIPS32: andi [[T0]],[[T0]],0xff
4642 ; MIPS32: sll [[T0]],[[T0]],0x10 5229 ; MIPS32: sll [[T0]],[[T0]],0x10
4643 ; MIPS32: lui [[T1]],0xff00 5230 ; MIPS32: lui [[T4]],0xff00
4644 ; MIPS32: ori [[T1]],[[T1]],0xffff 5231 ; MIPS32: ori [[T4]],[[T4]],0xffff
4645 ; MIPS32: and [[T2]],[[T2]],[[T1]] 5232 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4646 ; MIPS32: or [[T0]],[[T0]],[[T2]] 5233 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4647 ; MIPS32: srl [[T3:.*]],a0,0x18 5234 ; MIPS32: srl [[T12:.*]],a2,0x18
4648 ; MIPS32: andi [[T3]],[[T3]],0x1 5235 ; MIPS32: andi [[T12]],[[T12]],0x1
4649 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 5236 ; MIPS32: srl [[T2]],[[T2]],0x18
4650 ; MIPS32: andi [[T4]],[[T4]],0x1 5237 ; MIPS32: andi [[T2]],[[T2]],0x1
4651 ; MIPS32: sll [[T3]],[[T3]],0x1f 5238 ; MIPS32: sll [[T12]],[[T12]],0x1f
4652 ; MIPS32: sll [[T4]],[[T4]],0x1f 5239 ; MIPS32: sll [[T2]],[[T2]],0x1f
4653 ; MIPS32: xor [[T3]],[[T3]],[[T4]] 5240 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
4654 ; MIPS32: sltu [[T3]],zero,[[T3]] 5241 ; MIPS32: sltu [[T12]],zero,[[T12]]
4655 ; MIPS32: srl [[T3]],[[T3]],0x18 5242 ; MIPS32: srl [[T12]],[[T12]],0x18
4656 ; MIPS32: sll [[T0]],[[T0]],0x8 5243 ; MIPS32: sll [[T0]],[[T0]],0x8
4657 ; MIPS32: srl [[T0]],[[T0]],0x8 5244 ; MIPS32: srl [[T0]],[[T0]],0x8
4658 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 5245 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4659 ; MIPS32: andi [[T4]],a1,0xff 5246 ; MIPS32: move [[T0]],a3
4660 ; MIPS32: andi [[T4]],[[T4]],0x1 5247 ; MIPS32: andi [[T0]],[[T0]],0xff
4661 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 5248 ; MIPS32: andi [[T0]],[[T0]],0x1
4662 ; MIPS32: andi [[T2]],[[T2]],0x1 5249 ; MIPS32: move [[T1]],[[T3]]
4663 ; MIPS32: sll [[T4]],[[T4]],0x1f 5250 ; MIPS32: andi [[T1]],[[T1]],0xff
4664 ; MIPS32: sll [[T2]],[[T2]],0x1f 5251 ; MIPS32: andi [[T1]],[[T1]],0x1
4665 ; MIPS32: xor [[T4]],[[T4]],[[T2]] 5252 ; MIPS32: sll [[T0]],[[T0]],0x1f
4666 ; MIPS32: sltu [[T4]],zero,[[T4]] 5253 ; MIPS32: sll [[T1]],[[T1]],0x1f
4667 ; MIPS32: andi [[T4]],[[T4]],0xff 5254 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4668 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 5255 ; MIPS32: sltu [[T0]],zero,[[T0]]
4669 ; MIPS32: sll [[T5]],[[T5]],0x8 5256 ; MIPS32: andi [[T0]],[[T0]],0xff
4670 ; MIPS32: or [[T4]],[[T4]],[[T5]] 5257 ; MIPS32: srl [[T7]],[[T7]],0x8
4671 ; MIPS32: srl [[T2]],a1,0x8 5258 ; MIPS32: sll [[T7]],[[T7]],0x8
5259 ; MIPS32: or [[T0]],[[T0]],[[T7]]
5260 ; MIPS32: move [[T1]],a3
5261 ; MIPS32: srl [[T1]],[[T1]],0x8
5262 ; MIPS32: andi [[T1]],[[T1]],0xff
5263 ; MIPS32: andi [[T1]],[[T1]],0x1
5264 ; MIPS32: move [[T2]],[[T3]]
5265 ; MIPS32: srl [[T2]],[[T2]],0x8
4672 ; MIPS32: andi [[T2]],[[T2]],0xff 5266 ; MIPS32: andi [[T2]],[[T2]],0xff
4673 ; MIPS32: andi [[T2]],[[T2]],0x1 5267 ; MIPS32: andi [[T2]],[[T2]],0x1
4674 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 5268 ; MIPS32: sll [[T1]],[[T1]],0x1f
4675 ; MIPS32: andi [[T5]],[[T5]],0xff
4676 ; MIPS32: andi [[T5]],[[T5]],0x1
4677 ; MIPS32: sll [[T2]],[[T2]],0x1f 5269 ; MIPS32: sll [[T2]],[[T2]],0x1f
4678 ; MIPS32: sll [[T5]],[[T5]],0x1f 5270 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
4679 ; MIPS32: xor [[T2]],[[T2]],[[T5]] 5271 ; MIPS32: sltu [[T1]],zero,[[T1]]
4680 ; MIPS32: sltu [[T2]],zero,[[T2]] 5272 ; MIPS32: andi [[T1]],[[T1]],0xff
4681 ; MIPS32: andi [[T2]],[[T2]],0xff 5273 ; MIPS32: sll [[T1]],[[T1]],0x8
4682 ; MIPS32: sll [[T2]],[[T2]],0x8 5274 ; MIPS32: lui [[T2]],0xffff
4683 ; MIPS32: lui [[T5]],0xffff 5275 ; MIPS32: ori [[T2]],[[T2]],0xff
4684 ; MIPS32: ori [[T5]],[[T5]],0xff 5276 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4685 ; MIPS32: and [[T4]],[[T4]],[[T5]] 5277 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4686 ; MIPS32: or [[T2]],[[T2]],[[T4]] 5278 ; MIPS32: move [[T0]],a3
4687 ; MIPS32: srl [[T4]],a1,0x10 5279 ; MIPS32: srl [[T0]],[[T0]],0x10
4688 ; MIPS32: andi [[T4]],[[T4]],0xff 5280 ; MIPS32: andi [[T0]],[[T0]],0xff
4689 ; MIPS32: andi [[T4]],[[T4]],0x1 5281 ; MIPS32: andi [[T0]],[[T0]],0x1
4690 ; MIPS32: srl [[T5]],[[BV_E1]],0x10 5282 ; MIPS32: move [[T2]],[[T3]]
4691 ; MIPS32: andi [[T5]],[[T5]],0xff 5283 ; MIPS32: srl [[T2]],[[T2]],0x10
4692 ; MIPS32: andi [[T5]],[[T5]],0x1
4693 ; MIPS32: sll [[T4]],[[T4]],0x1f
4694 ; MIPS32: sll [[T5]],[[T5]],0x1f
4695 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
4696 ; MIPS32: sltu [[T4]],zero,[[T4]]
4697 ; MIPS32: andi [[T4]],[[T4]],0xff
4698 ; MIPS32: sll [[T4]],[[T4]],0x10
4699 ; MIPS32: lui [[T5]],0xff00
4700 ; MIPS32: ori [[T5]],[[T5]],0xffff
4701 ; MIPS32: and [[T2]],[[T2]],[[T5]]
4702 ; MIPS32: or [[T4]],[[T4]],[[T2]]
4703 ; MIPS32: srl [[T6:.*]],a1,0x18
4704 ; MIPS32: andi [[T6]],[[T6]],0x1
4705 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4706 ; MIPS32: andi [[T7]],[[T7]],0x1
4707 ; MIPS32: sll [[T6]],[[T6]],0x1f
4708 ; MIPS32: sll [[T7]],[[T7]],0x1f
4709 ; MIPS32: xor [[T6]],[[T6]],[[T7]]
4710 ; MIPS32: sltu [[T6]],zero,[[T6]]
4711 ; MIPS32: srl [[T6]],[[T6]],0x18
4712 ; MIPS32: sll [[T4]],[[T4]],0x8
4713 ; MIPS32: srl [[T4]],[[T4]],0x8
4714 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
4715 ; MIPS32: andi [[T4]],a2,0xff
4716 ; MIPS32: andi [[T4]],[[T4]],0x1
4717 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
4718 ; MIPS32: andi [[T7]],[[T7]],0x1
4719 ; MIPS32: sll [[T4]],[[T4]],0x1f
4720 ; MIPS32: sll [[T7]],[[T7]],0x1f
4721 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4722 ; MIPS32: sltu [[T4]],zero,[[T4]]
4723 ; MIPS32: andi [[T4]],[[T4]],0xff
4724 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4725 ; MIPS32: sll [[T8]],[[T8]],0x8
4726 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4727 ; MIPS32: srl [[T7]],a2,0x8
4728 ; MIPS32: andi [[T7]],[[T7]],0xff
4729 ; MIPS32: andi [[T7]],[[T7]],0x1
4730 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4731 ; MIPS32: andi [[T2]],[[T2]],0xff 5284 ; MIPS32: andi [[T2]],[[T2]],0xff
4732 ; MIPS32: andi [[T2]],[[T2]],0x1 5285 ; MIPS32: andi [[T2]],[[T2]],0x1
4733 ; MIPS32: sll [[T7]],[[T7]],0x1f 5286 ; MIPS32: sll [[T0]],[[T0]],0x1f
4734 ; MIPS32: sll [[T2]],[[T2]],0x1f 5287 ; MIPS32: sll [[T2]],[[T2]],0x1f
4735 ; MIPS32: xor [[T7]],[[T7]],[[T2]] 5288 ; MIPS32: xor [[T0]],[[T0]],[[T2]]
4736 ; MIPS32: sltu [[T7]],zero,[[T7]] 5289 ; MIPS32: sltu [[T0]],zero,[[T0]]
4737 ; MIPS32: andi [[T7]],[[T7]],0xff 5290 ; MIPS32: andi [[T0]],[[T0]],0xff
4738 ; MIPS32: sll [[T7]],[[T7]],0x8 5291 ; MIPS32: sll [[T0]],[[T0]],0x10
4739 ; MIPS32: lui [[T2]],0xffff
4740 ; MIPS32: ori [[T2]],[[T2]],0xff
4741 ; MIPS32: and [[T4]],[[T4]],[[T2]]
4742 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4743 ; MIPS32: srl [[T4]],a2,0x10
4744 ; MIPS32: andi [[T4]],[[T4]],0xff
4745 ; MIPS32: andi [[T4]],[[T4]],0x1
4746 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
4747 ; MIPS32: andi [[T2]],[[T2]],0xff
4748 ; MIPS32: andi [[T2]],[[T2]],0x1
4749 ; MIPS32: sll [[T4]],[[T4]],0x1f
4750 ; MIPS32: sll [[T2]],[[T2]],0x1f
4751 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4752 ; MIPS32: sltu [[T4]],zero,[[T4]]
4753 ; MIPS32: andi [[T4]],[[T4]],0xff
4754 ; MIPS32: sll [[T4]],[[T4]],0x10
4755 ; MIPS32: lui [[T2]],0xff00 5292 ; MIPS32: lui [[T2]],0xff00
4756 ; MIPS32: ori [[T2]],[[T2]],0xffff 5293 ; MIPS32: ori [[T2]],[[T2]],0xffff
4757 ; MIPS32: and [[T7]],[[T7]],[[T2]] 5294 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4758 ; MIPS32: or [[T4]],[[T4]],[[T7]] 5295 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4759 ; MIPS32: srl [[T9:.*]],a2,0x18 5296 ; MIPS32: srl [[T13:.*]],a3,0x18
4760 ; MIPS32: andi [[T9]],[[T9]],0x1
4761 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4762 ; MIPS32: andi [[T10]],[[T10]],0x1
4763 ; MIPS32: sll [[T9]],[[T9]],0x1f
4764 ; MIPS32: sll [[T10]],[[T10]],0x1f
4765 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
4766 ; MIPS32: sltu [[T9]],zero,[[T9]]
4767 ; MIPS32: srl [[T9]],[[T9]],0x18
4768 ; MIPS32: sll [[T4]],[[T4]],0x8
4769 ; MIPS32: srl [[T4]],[[T4]],0x8
4770 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4771 ; MIPS32: andi [[T4]],a3,0xff
4772 ; MIPS32: andi [[T4]],[[T4]],0x1
4773 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4774 ; MIPS32: andi [[T7]],[[T7]],0x1
4775 ; MIPS32: sll [[T4]],[[T4]],0x1f
4776 ; MIPS32: sll [[T7]],[[T7]],0x1f
4777 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4778 ; MIPS32: sltu [[T4]],zero,[[T4]]
4779 ; MIPS32: andi [[T4]],[[T4]],0xff
4780 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4781 ; MIPS32: sll [[T11]],[[T11]],0x8
4782 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4783 ; MIPS32: srl [[T7]],a3,0x8
4784 ; MIPS32: andi [[T7]],[[T7]],0xff
4785 ; MIPS32: andi [[T7]],[[T7]],0x1
4786 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4787 ; MIPS32: andi [[T10]],[[T10]],0xff
4788 ; MIPS32: andi [[T10]],[[T10]],0x1
4789 ; MIPS32: sll [[T7]],[[T7]],0x1f
4790 ; MIPS32: sll [[T10]],[[T10]],0x1f
4791 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
4792 ; MIPS32: sltu [[T7]],zero,[[T7]]
4793 ; MIPS32: andi [[T7]],[[T7]],0xff
4794 ; MIPS32: sll [[T7]],[[T7]],0x8
4795 ; MIPS32: lui [[T10]],0xffff
4796 ; MIPS32: ori [[T10]],[[T10]],0xff
4797 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4798 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4799 ; MIPS32: srl [[T4]],a3,0x10
4800 ; MIPS32: andi [[T4]],[[T4]],0xff
4801 ; MIPS32: andi [[T4]],[[T4]],0x1
4802 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4803 ; MIPS32: andi [[T10]],[[T10]],0xff
4804 ; MIPS32: andi [[T10]],[[T10]],0x1
4805 ; MIPS32: sll [[T4]],[[T4]],0x1f
4806 ; MIPS32: sll [[T10]],[[T10]],0x1f
4807 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
4808 ; MIPS32: sltu [[T4]],zero,[[T4]]
4809 ; MIPS32: andi [[T4]],[[T4]],0xff
4810 ; MIPS32: sll [[T4]],[[T4]],0x10
4811 ; MIPS32: lui [[T10]],0xff00
4812 ; MIPS32: ori [[T10]],[[T10]],0xffff
4813 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4814 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4815 ; MIPS32: srl [[T12:.*]],a3,0x18
4816 ; MIPS32: andi [[T12]],[[T12]],0x1
4817 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4818 ; MIPS32: andi [[T13]],[[T13]],0x1 5297 ; MIPS32: andi [[T13]],[[T13]],0x1
4819 ; MIPS32: sll [[T12]],[[T12]],0x1f 5298 ; MIPS32: srl [[T3]],[[T3]],0x18
5299 ; MIPS32: andi [[T3]],[[T3]],0x1
4820 ; MIPS32: sll [[T13]],[[T13]],0x1f 5300 ; MIPS32: sll [[T13]],[[T13]],0x1f
4821 ; MIPS32: xor [[T12]],[[T12]],[[T13]] 5301 ; MIPS32: sll [[T3]],[[T3]],0x1f
4822 ; MIPS32: sltu [[T12]],zero,[[T12]] 5302 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
4823 ; MIPS32: srl [[T12]],[[T12]],0x18 5303 ; MIPS32: sltu [[T13]],zero,[[T13]]
4824 ; MIPS32: sll [[T4]],[[T4]],0x8 5304 ; MIPS32: srl [[T13]],[[T13]],0x18
4825 ; MIPS32: srl [[T4]],[[T4]],0x8 5305 ; MIPS32: sll [[T0]],[[T0]],0x8
4826 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] 5306 ; MIPS32: srl [[T0]],[[T0]],0x8
5307 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5308 ; MIPS32: move v0,[[T10]]
5309 ; MIPS32: move v1,[[T11]]
5310 ; MIPS32: move a0,[[T12]]
5311 ; MIPS32: move a1,[[T13]]
4827 } 5312 }
4828 5313
4829 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) { 5314 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) {
4830 entry: 5315 entry:
4831 %res = icmp sgt <16 x i1> %a, %b 5316 %res = icmp sgt <16 x i1> %a, %b
4832 ret <16 x i1> %res 5317 ret <16 x i1> %res
4833 ; CHECK-LABEL: test_icmp_v16i1_sgt 5318 ; CHECK-LABEL: test_icmp_v16i1_sgt
4834 ; CHECK: pcmpgtb 5319 ; CHECK: pcmpgtb
4835 5320
4836 ; MIPS32-LABEL: test_icmp_v16i1_sgt 5321 ; MIPS32-LABEL: test_icmp_v16i1_sgt
4837 ; MIPS32: lw [[BV_E0:.*]], 5322 ; MIPS32: lw [[T0:.*]],
4838 ; MIPS32: lw [[BV_E1:.*]], 5323 ; MIPS32: lw [[T1:.*]],
4839 ; MIPS32: lw [[BV_E2:.*]], 5324 ; MIPS32: lw [[T2:.*]],
4840 ; MIPS32: lw [[BV_E3:.*]], 5325 ; MIPS32: lw [[T3:.*]],
4841 ; MIPS32: move [[TV_E0:.*]],zero 5326 ; MIPS32: move [[T4:.*]],zero
4842 ; MIPS32: move [[TV_E1:.*]],zero 5327 ; MIPS32: move [[T5:.*]],zero
4843 ; MIPS32: move [[TV_E2:.*]],zero 5328 ; MIPS32: move [[T6:.*]],zero
4844 ; MIPS32: move [[TV_E3:.*]],zero 5329 ; MIPS32: move [[T7:.*]],zero
4845 ; MIPS32: andi [[T0:.*]],a0,0xff 5330 ; MIPS32: move [[T8:.*]],a0
5331 ; MIPS32: andi [[T8]],[[T8]],0xff
5332 ; MIPS32: andi [[T8]],[[T8]],0x1
5333 ; MIPS32: move [[T9:.*]],[[T0]]
5334 ; MIPS32: andi [[T9]],[[T9]],0xff
5335 ; MIPS32: andi [[T9]],[[T9]],0x1
5336 ; MIPS32: sll [[T8]],[[T8]],0x1f
5337 ; MIPS32: sll [[T9]],[[T9]],0x1f
5338 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
5339 ; MIPS32: andi [[T9]],[[T9]],0xff
5340 ; MIPS32: srl [[T4]],[[T4]],0x8
5341 ; MIPS32: sll [[T4]],[[T4]],0x8
5342 ; MIPS32: or [[T9]],[[T9]],[[T4]]
5343 ; MIPS32: move [[T4]],a0
5344 ; MIPS32: srl [[T4]],[[T4]],0x8
5345 ; MIPS32: andi [[T4]],[[T4]],0xff
5346 ; MIPS32: andi [[T4]],[[T4]],0x1
5347 ; MIPS32: move [[T8]],[[T0]]
5348 ; MIPS32: srl [[T8]],[[T8]],0x8
5349 ; MIPS32: andi [[T8]],[[T8]],0xff
5350 ; MIPS32: andi [[T8]],[[T8]],0x1
5351 ; MIPS32: sll [[T4]],[[T4]],0x1f
5352 ; MIPS32: sll [[T8]],[[T8]],0x1f
5353 ; MIPS32: slt [[T8]],[[T8]],[[T4]]
5354 ; MIPS32: andi [[T8]],[[T8]],0xff
5355 ; MIPS32: sll [[T8]],[[T8]],0x8
5356 ; MIPS32: lui [[T4]],0xffff
5357 ; MIPS32: ori [[T4]],[[T4]],0xff
5358 ; MIPS32: and [[T9]],[[T9]],[[T4]]
5359 ; MIPS32: or [[T8]],[[T8]],[[T9]]
5360 ; MIPS32: move [[T4]],a0
5361 ; MIPS32: srl [[T4]],[[T4]],0x10
5362 ; MIPS32: andi [[T4]],[[T4]],0xff
5363 ; MIPS32: andi [[T4]],[[T4]],0x1
5364 ; MIPS32: move [[T9]],[[T0]]
5365 ; MIPS32: srl [[T9]],[[T9]],0x10
5366 ; MIPS32: andi [[T9]],[[T9]],0xff
5367 ; MIPS32: andi [[T9]],[[T9]],0x1
5368 ; MIPS32: sll [[T4]],[[T4]],0x1f
5369 ; MIPS32: sll [[T9]],[[T9]],0x1f
5370 ; MIPS32: slt [[T9]],[[T9]],[[T4]]
5371 ; MIPS32: andi [[T9]],[[T9]],0xff
5372 ; MIPS32: sll [[T9]],[[T9]],0x10
5373 ; MIPS32: lui [[T4]],0xff00
5374 ; MIPS32: ori [[T4]],[[T4]],0xffff
5375 ; MIPS32: and [[T8]],[[T8]],[[T4]]
5376 ; MIPS32: or [[T9]],[[T9]],[[T8]]
5377 ; MIPS32: srl [[T10:.*]],a0,0x18
5378 ; MIPS32: andi [[T10]],[[T10]],0x1
5379 ; MIPS32: srl [[T0]],[[T0]],0x18
4846 ; MIPS32: andi [[T0]],[[T0]],0x1 5380 ; MIPS32: andi [[T0]],[[T0]],0x1
4847 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 5381 ; MIPS32: sll [[T10]],[[T10]],0x1f
4848 ; MIPS32: andi [[T1]],[[T1]],0x1
4849 ; MIPS32: sll [[T0]],[[T0]],0x1f 5382 ; MIPS32: sll [[T0]],[[T0]],0x1f
4850 ; MIPS32: sll [[T1]],[[T1]],0x1f 5383 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
4851 ; MIPS32: slt [[T1]],[[T1]],[[T0]] 5384 ; MIPS32: srl [[T0]],[[T0]],0x18
4852 ; MIPS32: andi [[T1]],[[T1]],0xff 5385 ; MIPS32: sll [[T9]],[[T9]],0x8
4853 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 5386 ; MIPS32: srl [[T9]],[[T9]],0x8
4854 ; MIPS32: sll [[T2]],[[T2]],0x8 5387 ; MIPS32: or v0,[[T0]],[[T9]]
4855 ; MIPS32: or [[T1]],[[T1]],[[T2]] 5388 ; MIPS32: move [[T10]],a1
4856 ; MIPS32: srl [[T2]],a0,0x8 5389 ; MIPS32: andi [[T10]],[[T10]],0xff
4857 ; MIPS32: andi [[T2]],[[T2]],0xff 5390 ; MIPS32: andi [[T10]],[[T10]],0x1
4858 ; MIPS32: andi [[T2]],[[T2]],0x1 5391 ; MIPS32: move [[T4]],[[T1]]
4859 ; MIPS32: srl [[T0]],[[BV_E0]],0x8 5392 ; MIPS32: andi [[T4]],[[T4]],0xff
4860 ; MIPS32: andi [[T0]],[[T0]],0xff 5393 ; MIPS32: andi [[T4]],[[T4]],0x1
4861 ; MIPS32: andi [[T0]],[[T0]],0x1 5394 ; MIPS32: sll [[T10]],[[T10]],0x1f
4862 ; MIPS32: sll [[T2]],[[T2]],0x1f 5395 ; MIPS32: sll [[T4]],[[T4]],0x1f
4863 ; MIPS32: sll [[T0]],[[T0]],0x1f 5396 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
4864 ; MIPS32: slt [[T0]],[[T0]],[[T2]] 5397 ; MIPS32: andi [[T4]],[[T4]],0xff
4865 ; MIPS32: andi [[T0]],[[T0]],0xff 5398 ; MIPS32: srl [[T5]],[[T5]],0x8
4866 ; MIPS32: sll [[T0]],[[T0]],0x8
4867 ; MIPS32: lui [[T2]],0xffff
4868 ; MIPS32: ori [[T2]],[[T2]],0xff
4869 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4870 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4871 ; MIPS32: srl [[T2]],a0,0x10
4872 ; MIPS32: andi [[T2]],[[T2]],0xff
4873 ; MIPS32: andi [[T2]],[[T2]],0x1
4874 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4875 ; MIPS32: andi [[T1]],[[T1]],0xff
4876 ; MIPS32: andi [[T1]],[[T1]],0x1
4877 ; MIPS32: sll [[T2]],[[T2]],0x1f
4878 ; MIPS32: sll [[T1]],[[T1]],0x1f
4879 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
4880 ; MIPS32: andi [[T1]],[[T1]],0xff
4881 ; MIPS32: sll [[T1]],[[T1]],0x10
4882 ; MIPS32: lui [[T2]],0xff00
4883 ; MIPS32: ori [[T2]],[[T2]],0xffff
4884 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4885 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4886 ; MIPS32: srl [[T3:.*]],a0,0x18
4887 ; MIPS32: andi [[T3]],[[T3]],0x1
4888 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4889 ; MIPS32: andi [[T4]],[[T4]],0x1
4890 ; MIPS32: sll [[T3]],[[T3]],0x1f
4891 ; MIPS32: sll [[T4]],[[T4]],0x1f
4892 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
4893 ; MIPS32: srl [[T4]],[[T4]],0x18
4894 ; MIPS32: sll [[T1]],[[T1]],0x8
4895 ; MIPS32: srl [[T1]],[[T1]],0x8
4896 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
4897 ; MIPS32: andi [[T3]],a1,0xff
4898 ; MIPS32: andi [[T3]],[[T3]],0x1
4899 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4900 ; MIPS32: andi [[T2]],[[T2]],0x1
4901 ; MIPS32: sll [[T3]],[[T3]],0x1f
4902 ; MIPS32: sll [[T2]],[[T2]],0x1f
4903 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
4904 ; MIPS32: andi [[T2]],[[T2]],0xff
4905 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4906 ; MIPS32: sll [[T5]],[[T5]],0x8 5399 ; MIPS32: sll [[T5]],[[T5]],0x8
4907 ; MIPS32: or [[T2]],[[T2]],[[T5]] 5400 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4908 ; MIPS32: srl [[T3]],a1,0x8 5401 ; MIPS32: move [[T10]],a1
4909 ; MIPS32: andi [[T3]],[[T3]],0xff 5402 ; MIPS32: srl [[T10]],[[T10]],0x8
4910 ; MIPS32: andi [[T3]],[[T3]],0x1 5403 ; MIPS32: andi [[T10]],[[T10]],0xff
4911 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 5404 ; MIPS32: andi [[T10]],[[T10]],0x1
5405 ; MIPS32: move [[T5]],[[T1]]
5406 ; MIPS32: srl [[T5]],[[T5]],0x8
4912 ; MIPS32: andi [[T5]],[[T5]],0xff 5407 ; MIPS32: andi [[T5]],[[T5]],0xff
4913 ; MIPS32: andi [[T5]],[[T5]],0x1 5408 ; MIPS32: andi [[T5]],[[T5]],0x1
4914 ; MIPS32: sll [[T3]],[[T3]],0x1f 5409 ; MIPS32: sll [[T10]],[[T10]],0x1f
4915 ; MIPS32: sll [[T5]],[[T5]],0x1f 5410 ; MIPS32: sll [[T5]],[[T5]],0x1f
4916 ; MIPS32: slt [[T5]],[[T5]],[[T3]] 5411 ; MIPS32: slt [[T5]],[[T5]],[[T10]]
4917 ; MIPS32: andi [[T5]],[[T5]],0xff 5412 ; MIPS32: andi [[T5]],[[T5]],0xff
4918 ; MIPS32: sll [[T5]],[[T5]],0x8 5413 ; MIPS32: sll [[T5]],[[T5]],0x8
4919 ; MIPS32: lui [[T3]],0xffff 5414 ; MIPS32: lui [[T10]],0xffff
4920 ; MIPS32: ori [[T3]],[[T3]],0xff 5415 ; MIPS32: ori [[T10]],[[T10]],0xff
4921 ; MIPS32: and [[T2]],[[T2]],[[T3]] 5416 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4922 ; MIPS32: or [[T5]],[[T5]],[[T2]] 5417 ; MIPS32: or [[T5]],[[T5]],[[T4]]
4923 ; MIPS32: srl [[T3]],a1,0x10 5418 ; MIPS32: move [[T10]],a1
4924 ; MIPS32: andi [[T3]],[[T3]],0xff 5419 ; MIPS32: srl [[T10]],[[T10]],0x10
5420 ; MIPS32: andi [[T10]],[[T10]],0xff
5421 ; MIPS32: andi [[T10]],[[T10]],0x1
5422 ; MIPS32: move [[T4]],[[T1]]
5423 ; MIPS32: srl [[T4]],[[T4]],0x10
5424 ; MIPS32: andi [[T4]],[[T4]],0xff
5425 ; MIPS32: andi [[T4]],[[T4]],0x1
5426 ; MIPS32: sll [[T10]],[[T10]],0x1f
5427 ; MIPS32: sll [[T4]],[[T4]],0x1f
5428 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5429 ; MIPS32: andi [[T4]],[[T4]],0xff
5430 ; MIPS32: sll [[T4]],[[T4]],0x10
5431 ; MIPS32: lui [[T10]],0xff00
5432 ; MIPS32: ori [[T10]],[[T10]],0xffff
5433 ; MIPS32: and [[T5]],[[T5]],[[T10]]
5434 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5435 ; MIPS32: srl [[T11:.*]],a1,0x18
5436 ; MIPS32: andi [[T11]],[[T11]],0x1
5437 ; MIPS32: srl [[T1]],[[T1]],0x18
5438 ; MIPS32: andi [[T1]],[[T1]],0x1
5439 ; MIPS32: sll [[T11]],[[T11]],0x1f
5440 ; MIPS32: sll [[T1]],[[T1]],0x1f
5441 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
5442 ; MIPS32: srl [[T1]],[[T1]],0x18
5443 ; MIPS32: sll [[T4]],[[T4]],0x8
5444 ; MIPS32: srl [[T4]],[[T4]],0x8
5445 ; MIPS32: or v1,[[T1]],[[T4]]
5446 ; MIPS32: move [[T10]],a2
5447 ; MIPS32: andi [[T10]],[[T10]],0xff
5448 ; MIPS32: andi [[T10]],[[T10]],0x1
5449 ; MIPS32: move [[T11]],[[T2]]
5450 ; MIPS32: andi [[T11]],[[T11]],0xff
5451 ; MIPS32: andi [[T11]],[[T11]],0x1
5452 ; MIPS32: sll [[T10]],[[T10]],0x1f
5453 ; MIPS32: sll [[T11]],[[T11]],0x1f
5454 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5455 ; MIPS32: andi [[T11]],[[T11]],0xff
5456 ; MIPS32: srl [[T6]],[[T6]],0x8
5457 ; MIPS32: sll [[T6]],[[T6]],0x8
5458 ; MIPS32: or [[T11]],[[T11]],[[T6]]
5459 ; MIPS32: move [[T10]],a2
5460 ; MIPS32: srl [[T10]],[[T10]],0x8
5461 ; MIPS32: andi [[T10]],[[T10]],0xff
5462 ; MIPS32: andi [[T10]],[[T10]],0x1
5463 ; MIPS32: move [[T4]],[[T2]]
5464 ; MIPS32: srl [[T4]],[[T4]],0x8
5465 ; MIPS32: andi [[T4]],[[T4]],0xff
5466 ; MIPS32: andi [[T4]],[[T4]],0x1
5467 ; MIPS32: sll [[T10]],[[T10]],0x1f
5468 ; MIPS32: sll [[T4]],[[T4]],0x1f
5469 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5470 ; MIPS32: andi [[T4]],[[T4]],0xff
5471 ; MIPS32: sll [[T4]],[[T4]],0x8
5472 ; MIPS32: lui [[T10]],0xffff
5473 ; MIPS32: ori [[T10]],[[T10]],0xff
5474 ; MIPS32: and [[T11]],[[T11]],[[T10]]
5475 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5476 ; MIPS32: move [[T10]],a2
5477 ; MIPS32: srl [[T10]],[[T10]],0x10
5478 ; MIPS32: andi [[T10]],[[T10]],0xff
5479 ; MIPS32: andi [[T10]],[[T10]],0x1
5480 ; MIPS32: move [[T11]],[[T2]]
5481 ; MIPS32: srl [[T11]],[[T11]],0x10
5482 ; MIPS32: andi [[T11]],[[T11]],0xff
5483 ; MIPS32: andi [[T11]],[[T11]],0x1
5484 ; MIPS32: sll [[T10]],[[T10]],0x1f
5485 ; MIPS32: sll [[T11]],[[T11]],0x1f
5486 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5487 ; MIPS32: andi [[T11]],[[T11]],0xff
5488 ; MIPS32: sll [[T11]],[[T11]],0x10
5489 ; MIPS32: lui [[T10]],0xff00
5490 ; MIPS32: ori [[T10]],[[T10]],0xffff
5491 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5492 ; MIPS32: or [[T11]],[[T11]],[[T4]]
5493 ; MIPS32: srl [[T12:.*]],a2,0x18
5494 ; MIPS32: andi [[T12]],[[T12]],0x1
5495 ; MIPS32: srl [[T2]],[[T2]],0x18
5496 ; MIPS32: andi [[T2]],[[T2]],0x1
5497 ; MIPS32: sll [[T12]],[[T12]],0x1f
5498 ; MIPS32: sll [[T2]],[[T2]],0x1f
5499 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
5500 ; MIPS32: srl [[T2]],[[T2]],0x18
5501 ; MIPS32: sll [[T11]],[[T11]],0x8
5502 ; MIPS32: srl [[T11]],[[T11]],0x8
5503 ; MIPS32: or [[T2]],[[T2]],[[T11]]
5504 ; MIPS32: move [[T10]],a3
5505 ; MIPS32: andi [[T10]],[[T10]],0xff
5506 ; MIPS32: andi [[T10]],[[T10]],0x1
5507 ; MIPS32: move [[T11]],[[T3]]
5508 ; MIPS32: andi [[T11]],[[T11]],0xff
5509 ; MIPS32: andi [[T11]],[[T11]],0x1
5510 ; MIPS32: sll [[T10]],[[T10]],0x1f
5511 ; MIPS32: sll [[T11]],[[T11]],0x1f
5512 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5513 ; MIPS32: andi [[T11]],[[T11]],0xff
5514 ; MIPS32: srl [[T7]],[[T7]],0x8
5515 ; MIPS32: sll [[T7]],[[T7]],0x8
5516 ; MIPS32: or [[T11]],[[T11]],[[T7]]
5517 ; MIPS32: move [[T10]],a3
5518 ; MIPS32: srl [[T10]],[[T10]],0x8
5519 ; MIPS32: andi [[T10]],[[T10]],0xff
5520 ; MIPS32: andi [[T10]],[[T10]],0x1
5521 ; MIPS32: move [[T12]],[[T3]]
5522 ; MIPS32: srl [[T12]],[[T12]],0x8
5523 ; MIPS32: andi [[T12]],[[T12]],0xff
5524 ; MIPS32: andi [[T12]],[[T12]],0x1
5525 ; MIPS32: sll [[T10]],[[T10]],0x1f
5526 ; MIPS32: sll [[T12]],[[T12]],0x1f
5527 ; MIPS32: slt [[T12]],[[T12]],[[T10]]
5528 ; MIPS32: andi [[T12]],[[T12]],0xff
5529 ; MIPS32: sll [[T12]],[[T12]],0x8
5530 ; MIPS32: lui [[T10]],0xffff
5531 ; MIPS32: ori [[T10]],[[T10]],0xff
5532 ; MIPS32: and [[T11]],[[T11]],[[T10]]
5533 ; MIPS32: or [[T12]],[[T12]],[[T11]]
5534 ; MIPS32: move [[T10]],a3
5535 ; MIPS32: srl [[T10]],[[T10]],0x10
5536 ; MIPS32: andi [[T10]],[[T10]],0xff
5537 ; MIPS32: andi [[T10]],[[T10]],0x1
5538 ; MIPS32: move [[T11]],[[T3]]
5539 ; MIPS32: srl [[T11]],[[T11]],0x10
5540 ; MIPS32: andi [[T11]],[[T11]],0xff
5541 ; MIPS32: andi [[T11]],[[T11]],0x1
5542 ; MIPS32: sll [[T10]],[[T10]],0x1f
5543 ; MIPS32: sll [[T11]],[[T11]],0x1f
5544 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5545 ; MIPS32: andi [[T11]],[[T11]],0xff
5546 ; MIPS32: sll [[T11]],[[T11]],0x10
5547 ; MIPS32: lui [[T10]],0xff00
5548 ; MIPS32: ori [[T10]],[[T10]],0xffff
5549 ; MIPS32: and [[T12]],[[T12]],[[T10]]
5550 ; MIPS32: or [[T11]],[[T11]],[[T12]]
5551 ; MIPS32: srl [[T13:.*]],a3,0x18
5552 ; MIPS32: andi [[T13]],[[T13]],0x1
5553 ; MIPS32: srl [[T3]],[[T3]],0x18
4925 ; MIPS32: andi [[T3]],[[T3]],0x1 5554 ; MIPS32: andi [[T3]],[[T3]],0x1
4926 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 5555 ; MIPS32: sll [[T13]],[[T13]],0x1f
4927 ; MIPS32: andi [[T2]],[[T2]],0xff
4928 ; MIPS32: andi [[T2]],[[T2]],0x1
4929 ; MIPS32: sll [[T3]],[[T3]],0x1f 5556 ; MIPS32: sll [[T3]],[[T3]],0x1f
4930 ; MIPS32: sll [[T2]],[[T2]],0x1f 5557 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
4931 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 5558 ; MIPS32: srl [[T3]],[[T3]],0x18
4932 ; MIPS32: andi [[T2]],[[T2]],0xff
4933 ; MIPS32: sll [[T2]],[[T2]],0x10
4934 ; MIPS32: lui [[T3]],0xff00
4935 ; MIPS32: ori [[T3]],[[T3]],0xffff
4936 ; MIPS32: and [[T5]],[[T5]],[[T3]]
4937 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4938 ; MIPS32: srl [[T6:.*]],a1,0x18
4939 ; MIPS32: andi [[T6]],[[T6]],0x1
4940 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4941 ; MIPS32: andi [[T7]],[[T7]],0x1
4942 ; MIPS32: sll [[T6]],[[T6]],0x1f
4943 ; MIPS32: sll [[T7]],[[T7]],0x1f
4944 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
4945 ; MIPS32: srl [[T7]],[[T7]],0x18
4946 ; MIPS32: sll [[T2]],[[T2]],0x8
4947 ; MIPS32: srl [[T2]],[[T2]],0x8
4948 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
4949 ; MIPS32: andi [[T3]],a2,0xff
4950 ; MIPS32: andi [[T3]],[[T3]],0x1
4951 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
4952 ; MIPS32: andi [[T6]],[[T6]],0x1
4953 ; MIPS32: sll [[T3]],[[T3]],0x1f
4954 ; MIPS32: sll [[T6]],[[T6]],0x1f
4955 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
4956 ; MIPS32: andi [[T6]],[[T6]],0xff
4957 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4958 ; MIPS32: sll [[T8]],[[T8]],0x8
4959 ; MIPS32: or [[T6]],[[T6]],[[T8]]
4960 ; MIPS32: srl [[T3]],a2,0x8
4961 ; MIPS32: andi [[T3]],[[T3]],0xff
4962 ; MIPS32: andi [[T3]],[[T3]],0x1
4963 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4964 ; MIPS32: andi [[T2]],[[T2]],0xff
4965 ; MIPS32: andi [[T2]],[[T2]],0x1
4966 ; MIPS32: sll [[T3]],[[T3]],0x1f
4967 ; MIPS32: sll [[T2]],[[T2]],0x1f
4968 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
4969 ; MIPS32: andi [[T2]],[[T2]],0xff
4970 ; MIPS32: sll [[T2]],[[T2]],0x8
4971 ; MIPS32: lui [[T3]],0xffff
4972 ; MIPS32: ori [[T3]],[[T3]],0xff
4973 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4974 ; MIPS32: or [[T2]],[[T2]],[[T6]]
4975 ; MIPS32: srl [[T3]],a2,0x10
4976 ; MIPS32: andi [[T3]],[[T3]],0xff
4977 ; MIPS32: andi [[T3]],[[T3]],0x1
4978 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
4979 ; MIPS32: andi [[T6]],[[T6]],0xff
4980 ; MIPS32: andi [[T6]],[[T6]],0x1
4981 ; MIPS32: sll [[T3]],[[T3]],0x1f
4982 ; MIPS32: sll [[T6]],[[T6]],0x1f
4983 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
4984 ; MIPS32: andi [[T6]],[[T6]],0xff
4985 ; MIPS32: sll [[T6]],[[T6]],0x10
4986 ; MIPS32: lui [[T3]],0xff00
4987 ; MIPS32: ori [[T3]],[[T3]],0xffff
4988 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4989 ; MIPS32: or [[T6]],[[T6]],[[T2]]
4990 ; MIPS32: srl [[T9:.*]],a2,0x18
4991 ; MIPS32: andi [[T9]],[[T9]],0x1
4992 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4993 ; MIPS32: andi [[T10]],[[T10]],0x1
4994 ; MIPS32: sll [[T9]],[[T9]],0x1f
4995 ; MIPS32: sll [[T10]],[[T10]],0x1f
4996 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
4997 ; MIPS32: srl [[T10]],[[T10]],0x18
4998 ; MIPS32: sll [[T6]],[[T6]],0x8
4999 ; MIPS32: srl [[T6]],[[T6]],0x8
5000 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5001 ; MIPS32: andi [[T3]],a3,0xff
5002 ; MIPS32: andi [[T3]],[[T3]],0x1
5003 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5004 ; MIPS32: andi [[T6]],[[T6]],0x1
5005 ; MIPS32: sll [[T3]],[[T3]],0x1f
5006 ; MIPS32: sll [[T6]],[[T6]],0x1f
5007 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5008 ; MIPS32: andi [[T6]],[[T6]],0xff
5009 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5010 ; MIPS32: sll [[T11]],[[T11]],0x8 5559 ; MIPS32: sll [[T11]],[[T11]],0x8
5011 ; MIPS32: or [[T6]],[[T6]],[[T11]] 5560 ; MIPS32: srl [[T11]],[[T11]],0x8
5012 ; MIPS32: srl [[T3]],a3,0x8 5561 ; MIPS32: or [[T3]],[[T3]],[[T11]]
5013 ; MIPS32: andi [[T3]],[[T3]],0xff 5562 ; MIPS32: move a0,[[T2]]
5014 ; MIPS32: andi [[T3]],[[T3]],0x1 5563 ; MIPS32: move a1,[[T3]]
5015 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5016 ; MIPS32: andi [[T9]],[[T9]],0xff
5017 ; MIPS32: andi [[T9]],[[T9]],0x1
5018 ; MIPS32: sll [[T3]],[[T3]],0x1f
5019 ; MIPS32: sll [[T9]],[[T9]],0x1f
5020 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
5021 ; MIPS32: andi [[T9]],[[T9]],0xff
5022 ; MIPS32: sll [[T9]],[[T9]],0x8
5023 ; MIPS32: lui [[T3]],0xffff
5024 ; MIPS32: ori [[T3]],[[T3]],0xff
5025 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5026 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5027 ; MIPS32: srl [[T3]],a3,0x10
5028 ; MIPS32: andi [[T3]],[[T3]],0xff
5029 ; MIPS32: andi [[T3]],[[T3]],0x1
5030 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5031 ; MIPS32: andi [[T6]],[[T6]],0xff
5032 ; MIPS32: andi [[T6]],[[T6]],0x1
5033 ; MIPS32: sll [[T3]],[[T3]],0x1f
5034 ; MIPS32: sll [[T6]],[[T6]],0x1f
5035 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5036 ; MIPS32: andi [[T6]],[[T6]],0xff
5037 ; MIPS32: sll [[T6]],[[T6]],0x10
5038 ; MIPS32: lui [[T3]],0xff00
5039 ; MIPS32: ori [[T3]],[[T3]],0xffff
5040 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5041 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5042 ; MIPS32: srl [[T12:.*]],a3,0x18
5043 ; MIPS32: andi [[T12]],[[T12]],0x1
5044 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5045 ; MIPS32: andi [[T13]],[[T13]],0x1
5046 ; MIPS32: sll [[T12]],[[T12]],0x1f
5047 ; MIPS32: sll [[T13]],[[T13]],0x1f
5048 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
5049 ; MIPS32: srl [[T13]],[[T13]],0x18
5050 ; MIPS32: sll [[T6]],[[T6]],0x8
5051 ; MIPS32: srl [[T6]],[[T6]],0x8
5052 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
5053 } 5564 }
5054 5565
5055 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) { 5566 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) {
5056 entry: 5567 entry:
5057 %res = icmp sle <16 x i1> %a, %b 5568 %res = icmp sle <16 x i1> %a, %b
5058 ret <16 x i1> %res 5569 ret <16 x i1> %res
5059 ; CHECK-LABEL: test_icmp_v16i1_sle 5570 ; CHECK-LABEL: test_icmp_v16i1_sle
5060 ; CHECK: pcmpgtb 5571 ; CHECK: pcmpgtb
5061 ; CHECK: pxor 5572 ; CHECK: pxor
5062 5573
5063 ; MIPS32-LABEL: test_icmp_v16i1_sle 5574 ; MIPS32-LABEL: test_icmp_v16i1_sle
5064 ; MIPS32: lw [[BV_E0:.*]], 5575 ; MIPS32: lw [[T0:.*]],
5065 ; MIPS32: lw [[BV_E1:.*]], 5576 ; MIPS32: lw [[T1:.*]],
5066 ; MIPS32: lw [[BV_E2:.*]], 5577 ; MIPS32: lw [[T2:.*]],
5067 ; MIPS32: lw [[BV_E3:.*]], 5578 ; MIPS32: lw [[T3:.*]],
5068 ; MIPS32: move [[TV_E0:.*]],zero 5579 ; MIPS32: move [[T4:.*]],zero
5069 ; MIPS32: move [[TV_E1:.*]],zero 5580 ; MIPS32: move [[T5:.*]],zero
5070 ; MIPS32: move [[TV_E2:.*]],zero 5581 ; MIPS32: move [[T6:.*]],zero
5071 ; MIPS32: move [[TV_E3:.*]],zero 5582 ; MIPS32: move [[T7:.*]],zero
5072 ; MIPS32: andi [[T0:.*]],a0,0xff 5583 ; MIPS32: move [[T8:.*]],a0
5584 ; MIPS32: andi [[T8]],[[T8]],0xff
5585 ; MIPS32: andi [[T8]],[[T8]],0x1
5586 ; MIPS32: move [[T9:.*]],[[T0]]
5587 ; MIPS32: andi [[T9]],[[T9]],0xff
5588 ; MIPS32: andi [[T9]],[[T9]],0x1
5589 ; MIPS32: sll [[T8]],[[T8]],0x1f
5590 ; MIPS32: sll [[T9]],[[T9]],0x1f
5591 ; MIPS32: slt [[T9]],[[T9]],[[T8]]
5592 ; MIPS32: xori [[T9]],[[T9]],0x1
5593 ; MIPS32: andi [[T9]],[[T9]],0xff
5594 ; MIPS32: srl [[T4]],[[T4]],0x8
5595 ; MIPS32: sll [[T4]],[[T4]],0x8
5596 ; MIPS32: or [[T9]],[[T9]],[[T4]]
5597 ; MIPS32: move [[T4]],a0
5598 ; MIPS32: srl [[T4]],[[T4]],0x8
5599 ; MIPS32: andi [[T4]],[[T4]],0xff
5600 ; MIPS32: andi [[T4]],[[T4]],0x1
5601 ; MIPS32: move [[T8]],[[T0]]
5602 ; MIPS32: srl [[T8]],[[T8]],0x8
5603 ; MIPS32: andi [[T8]],[[T8]],0xff
5604 ; MIPS32: andi [[T8]],[[T8]],0x1
5605 ; MIPS32: sll [[T4]],[[T4]],0x1f
5606 ; MIPS32: sll [[T8]],[[T8]],0x1f
5607 ; MIPS32: slt [[T8]],[[T8]],[[T4]]
5608 ; MIPS32: xori [[T8]],[[T8]],0x1
5609 ; MIPS32: andi [[T8]],[[T8]],0xff
5610 ; MIPS32: sll [[T8]],[[T8]],0x8
5611 ; MIPS32: lui [[T4]],0xffff
5612 ; MIPS32: ori [[T4]],[[T4]],0xff
5613 ; MIPS32: and [[T9]],[[T9]],[[T4]]
5614 ; MIPS32: or [[T8]],[[T8]],[[T9]]
5615 ; MIPS32: move [[T4]],a0
5616 ; MIPS32: srl [[T4]],[[T4]],0x10
5617 ; MIPS32: andi [[T4]],[[T4]],0xff
5618 ; MIPS32: andi [[T4]],[[T4]],0x1
5619 ; MIPS32: move [[T9]],[[T0]]
5620 ; MIPS32: srl [[T9]],[[T9]],0x10
5621 ; MIPS32: andi [[T9]],[[T9]],0xff
5622 ; MIPS32: andi [[T9]],[[T9]],0x1
5623 ; MIPS32: sll [[T4]],[[T4]],0x1f
5624 ; MIPS32: sll [[T9]],[[T9]],0x1f
5625 ; MIPS32: slt [[T9]],[[T9]],[[T4]]
5626 ; MIPS32: xori [[T9]],[[T9]],0x1
5627 ; MIPS32: andi [[T9]],[[T9]],0xff
5628 ; MIPS32: sll [[T9]],[[T9]],0x10
5629 ; MIPS32: lui [[T4]],0xff00
5630 ; MIPS32: ori [[T4]],[[T4]],0xffff
5631 ; MIPS32: and [[T8]],[[T8]],[[T4]]
5632 ; MIPS32: or [[T9]],[[T9]],[[T8]]
5633 ; MIPS32: srl [[T10:.*]],a0,0x18
5634 ; MIPS32: andi [[T10]],[[T10]],0x1
5635 ; MIPS32: srl [[T0]],[[T0]],0x18
5073 ; MIPS32: andi [[T0]],[[T0]],0x1 5636 ; MIPS32: andi [[T0]],[[T0]],0x1
5074 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 5637 ; MIPS32: sll [[T10]],[[T10]],0x1f
5075 ; MIPS32: andi [[T1]],[[T1]],0x1
5076 ; MIPS32: sll [[T0]],[[T0]],0x1f 5638 ; MIPS32: sll [[T0]],[[T0]],0x1f
5077 ; MIPS32: sll [[T1]],[[T1]],0x1f 5639 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
5078 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
5079 ; MIPS32: xori [[T1]],[[T1]],0x1
5080 ; MIPS32: andi [[T1]],[[T1]],0xff
5081 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
5082 ; MIPS32: sll [[T2]],[[T2]],0x8
5083 ; MIPS32: or [[T1]],[[T1]],[[T2]]
5084 ; MIPS32: srl [[T2]],a0,0x8
5085 ; MIPS32: andi [[T2]],[[T2]],0xff
5086 ; MIPS32: andi [[T2]],[[T2]],0x1
5087 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
5088 ; MIPS32: andi [[T0]],[[T0]],0xff
5089 ; MIPS32: andi [[T0]],[[T0]],0x1
5090 ; MIPS32: sll [[T2]],[[T2]],0x1f
5091 ; MIPS32: sll [[T0]],[[T0]],0x1f
5092 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
5093 ; MIPS32: xori [[T0]],[[T0]],0x1 5640 ; MIPS32: xori [[T0]],[[T0]],0x1
5094 ; MIPS32: andi [[T0]],[[T0]],0xff 5641 ; MIPS32: srl [[T0]],[[T0]],0x18
5095 ; MIPS32: sll [[T0]],[[T0]],0x8 5642 ; MIPS32: sll [[T9]],[[T9]],0x8
5096 ; MIPS32: lui [[T2]],0xffff 5643 ; MIPS32: srl [[T9]],[[T9]],0x8
5097 ; MIPS32: ori [[T2]],[[T2]],0xff 5644 ; MIPS32: or v0,[[T0]],[[T9]]
5098 ; MIPS32: and [[T1]],[[T1]],[[T2]] 5645 ; MIPS32: move [[T10]],a1
5099 ; MIPS32: or [[T0]],[[T0]],[[T1]] 5646 ; MIPS32: andi [[T10]],[[T10]],0xff
5100 ; MIPS32: srl [[T2]],a0,0x10 5647 ; MIPS32: andi [[T10]],[[T10]],0x1
5101 ; MIPS32: andi [[T2]],[[T2]],0xff 5648 ; MIPS32: move [[T4]],[[T1]]
5102 ; MIPS32: andi [[T2]],[[T2]],0x1 5649 ; MIPS32: andi [[T4]],[[T4]],0xff
5103 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 5650 ; MIPS32: andi [[T4]],[[T4]],0x1
5104 ; MIPS32: andi [[T1]],[[T1]],0xff 5651 ; MIPS32: sll [[T10]],[[T10]],0x1f
5105 ; MIPS32: andi [[T1]],[[T1]],0x1 5652 ; MIPS32: sll [[T4]],[[T4]],0x1f
5106 ; MIPS32: sll [[T2]],[[T2]],0x1f 5653 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5107 ; MIPS32: sll [[T1]],[[T1]],0x1f
5108 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
5109 ; MIPS32: xori [[T1]],[[T1]],0x1
5110 ; MIPS32: andi [[T1]],[[T1]],0xff
5111 ; MIPS32: sll [[T1]],[[T1]],0x10
5112 ; MIPS32: lui [[T2]],0xff00
5113 ; MIPS32: ori [[T2]],[[T2]],0xffff
5114 ; MIPS32: and [[T0]],[[T0]],[[T2]]
5115 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5116 ; MIPS32: srl [[T3:.*]],a0,0x18
5117 ; MIPS32: andi [[T3]],[[T3]],0x1
5118 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5119 ; MIPS32: andi [[T4]],[[T4]],0x1
5120 ; MIPS32: sll [[T3]],[[T3]],0x1f
5121 ; MIPS32: sll [[T4]],[[T4]],0x1f
5122 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
5123 ; MIPS32: xori [[T4]],[[T4]],0x1 5654 ; MIPS32: xori [[T4]],[[T4]],0x1
5124 ; MIPS32: srl [[T4]],[[T4]],0x18 5655 ; MIPS32: andi [[T4]],[[T4]],0xff
5125 ; MIPS32: sll [[T1]],[[T1]],0x8 5656 ; MIPS32: srl [[T5]],[[T5]],0x8
5126 ; MIPS32: srl [[T1]],[[T1]],0x8
5127 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
5128 ; MIPS32: andi [[T3]],a1,0xff
5129 ; MIPS32: andi [[T3]],[[T3]],0x1
5130 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5131 ; MIPS32: andi [[T2]],[[T2]],0x1
5132 ; MIPS32: sll [[T3]],[[T3]],0x1f
5133 ; MIPS32: sll [[T2]],[[T2]],0x1f
5134 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
5135 ; MIPS32: xori [[T2]],[[T2]],0x1
5136 ; MIPS32: andi [[T2]],[[T2]],0xff
5137 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5138 ; MIPS32: sll [[T5]],[[T5]],0x8 5657 ; MIPS32: sll [[T5]],[[T5]],0x8
5139 ; MIPS32: or [[T2]],[[T2]],[[T5]] 5658 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5140 ; MIPS32: srl [[T3]],a1,0x8 5659 ; MIPS32: move [[T10]],a1
5141 ; MIPS32: andi [[T3]],[[T3]],0xff 5660 ; MIPS32: srl [[T10]],[[T10]],0x8
5142 ; MIPS32: andi [[T3]],[[T3]],0x1 5661 ; MIPS32: andi [[T10]],[[T10]],0xff
5143 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 5662 ; MIPS32: andi [[T10]],[[T10]],0x1
5663 ; MIPS32: move [[T5]],[[T1]]
5664 ; MIPS32: srl [[T5]],[[T5]],0x8
5144 ; MIPS32: andi [[T5]],[[T5]],0xff 5665 ; MIPS32: andi [[T5]],[[T5]],0xff
5145 ; MIPS32: andi [[T5]],[[T5]],0x1 5666 ; MIPS32: andi [[T5]],[[T5]],0x1
5146 ; MIPS32: sll [[T3]],[[T3]],0x1f 5667 ; MIPS32: sll [[T10]],[[T10]],0x1f
5147 ; MIPS32: sll [[T5]],[[T5]],0x1f 5668 ; MIPS32: sll [[T5]],[[T5]],0x1f
5148 ; MIPS32: slt [[T5]],[[T5]],[[T3]] 5669 ; MIPS32: slt [[T5]],[[T5]],[[T10]]
5149 ; MIPS32: xori [[T5]],[[T5]],0x1 5670 ; MIPS32: xori [[T5]],[[T5]],0x1
5150 ; MIPS32: andi [[T5]],[[T5]],0xff 5671 ; MIPS32: andi [[T5]],[[T5]],0xff
5151 ; MIPS32: sll [[T5]],[[T5]],0x8 5672 ; MIPS32: sll [[T5]],[[T5]],0x8
5152 ; MIPS32: lui [[T3]],0xffff 5673 ; MIPS32: lui [[T10]],0xffff
5153 ; MIPS32: ori [[T3]],[[T3]],0xff 5674 ; MIPS32: ori [[T10]],[[T10]],0xff
5154 ; MIPS32: and [[T2]],[[T2]],[[T3]] 5675 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5155 ; MIPS32: or [[T5]],[[T5]],[[T2]] 5676 ; MIPS32: or [[T5]],[[T5]],[[T4]]
5156 ; MIPS32: srl [[T3]],a1,0x10 5677 ; MIPS32: move [[T10]],a1
5157 ; MIPS32: andi [[T3]],[[T3]],0xff 5678 ; MIPS32: srl [[T10]],[[T10]],0x10
5679 ; MIPS32: andi [[T10]],[[T10]],0xff
5680 ; MIPS32: andi [[T10]],[[T10]],0x1
5681 ; MIPS32: move [[T4]],[[T1]]
5682 ; MIPS32: srl [[T4]],[[T4]],0x10
5683 ; MIPS32: andi [[T4]],[[T4]],0xff
5684 ; MIPS32: andi [[T4]],[[T4]],0x1
5685 ; MIPS32: sll [[T10]],[[T10]],0x1f
5686 ; MIPS32: sll [[T4]],[[T4]],0x1f
5687 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5688 ; MIPS32: xori [[T4]],[[T4]],0x1
5689 ; MIPS32: andi [[T4]],[[T4]],0xff
5690 ; MIPS32: sll [[T4]],[[T4]],0x10
5691 ; MIPS32: lui [[T10]],0xff00
5692 ; MIPS32: ori [[T10]],[[T10]],0xffff
5693 ; MIPS32: and [[T5]],[[T5]],[[T10]]
5694 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5695 ; MIPS32: srl [[T11:.*]],a1,0x18
5696 ; MIPS32: andi [[T11]],[[T11]],0x1
5697 ; MIPS32: srl [[T1]],[[T1]],0x18
5698 ; MIPS32: andi [[T1]],[[T1]],0x1
5699 ; MIPS32: sll [[T11]],[[T11]],0x1f
5700 ; MIPS32: sll [[T1]],[[T1]],0x1f
5701 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
5702 ; MIPS32: xori [[T1]],[[T1]],0x1
5703 ; MIPS32: srl [[T1]],[[T1]],0x18
5704 ; MIPS32: sll [[T4]],[[T4]],0x8
5705 ; MIPS32: srl [[T4]],[[T4]],0x8
5706 ; MIPS32: or v1,[[T1]],[[T4]]
5707 ; MIPS32: move [[T10]],a2
5708 ; MIPS32: andi [[T10]],[[T10]],0xff
5709 ; MIPS32: andi [[T10]],[[T10]],0x1
5710 ; MIPS32: move [[T11]],[[T2]]
5711 ; MIPS32: andi [[T11]],[[T11]],0xff
5712 ; MIPS32: andi [[T11]],[[T11]],0x1
5713 ; MIPS32: sll [[T10]],[[T10]],0x1f
5714 ; MIPS32: sll [[T11]],[[T11]],0x1f
5715 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5716 ; MIPS32: xori [[T11]],[[T11]],0x1
5717 ; MIPS32: andi [[T11]],[[T11]],0xff
5718 ; MIPS32: srl [[T6]],[[T6]],0x8
5719 ; MIPS32: sll [[T6]],[[T6]],0x8
5720 ; MIPS32: or [[T11]],[[T11]],[[T6]]
5721 ; MIPS32: move [[T10]],a2
5722 ; MIPS32: srl [[T10]],[[T10]],0x8
5723 ; MIPS32: andi [[T10]],[[T10]],0xff
5724 ; MIPS32: andi [[T10]],[[T10]],0x1
5725 ; MIPS32: move [[T4]],[[T2]]
5726 ; MIPS32: srl [[T4]],[[T4]],0x8
5727 ; MIPS32: andi [[T4]],[[T4]],0xff
5728 ; MIPS32: andi [[T4]],[[T4]],0x1
5729 ; MIPS32: sll [[T10]],[[T10]],0x1f
5730 ; MIPS32: sll [[T4]],[[T4]],0x1f
5731 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5732 ; MIPS32: xori [[T4]],[[T4]],0x1
5733 ; MIPS32: andi [[T4]],[[T4]],0xff
5734 ; MIPS32: sll [[T4]],[[T4]],0x8
5735 ; MIPS32: lui [[T10]],0xffff
5736 ; MIPS32: ori [[T10]],[[T10]],0xff
5737 ; MIPS32: and [[T11]],[[T11]],[[T10]]
5738 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5739 ; MIPS32: move [[T10]],a2
5740 ; MIPS32: srl [[T10]],[[T10]],0x10
5741 ; MIPS32: andi [[T10]],[[T10]],0xff
5742 ; MIPS32: andi [[T10]],[[T10]],0x1
5743 ; MIPS32: move [[T11]],[[T2]]
5744 ; MIPS32: srl [[T11]],[[T11]],0x10
5745 ; MIPS32: andi [[T11]],[[T11]],0xff
5746 ; MIPS32: andi [[T11]],[[T11]],0x1
5747 ; MIPS32: sll [[T10]],[[T10]],0x1f
5748 ; MIPS32: sll [[T11]],[[T11]],0x1f
5749 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5750 ; MIPS32: xori [[T11]],[[T11]],0x1
5751 ; MIPS32: andi [[T11]],[[T11]],0xff
5752 ; MIPS32: sll [[T11]],[[T11]],0x10
5753 ; MIPS32: lui [[T10]],0xff00
5754 ; MIPS32: ori [[T10]],[[T10]],0xffff
5755 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5756 ; MIPS32: or [[T11]],[[T11]],[[T4]]
5757 ; MIPS32: srl [[T12:.*]],a2,0x18
5758 ; MIPS32: andi [[T12]],[[T12]],0x1
5759 ; MIPS32: srl [[T2]],[[T2]],0x18
5760 ; MIPS32: andi [[T2]],[[T2]],0x1
5761 ; MIPS32: sll [[T12]],[[T12]],0x1f
5762 ; MIPS32: sll [[T2]],[[T2]],0x1f
5763 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
5764 ; MIPS32: xori [[T2]],[[T2]],0x1
5765 ; MIPS32: srl [[T2]],[[T2]],0x18
5766 ; MIPS32: sll [[T11]],[[T11]],0x8
5767 ; MIPS32: srl [[T11]],[[T11]],0x8
5768 ; MIPS32: or [[T2]],[[T2]],[[T11]]
5769 ; MIPS32: move [[T10]],a3
5770 ; MIPS32: andi [[T10]],[[T10]],0xff
5771 ; MIPS32: andi [[T10]],[[T10]],0x1
5772 ; MIPS32: move [[T11]],[[T3]]
5773 ; MIPS32: andi [[T11]],[[T11]],0xff
5774 ; MIPS32: andi [[T11]],[[T11]],0x1
5775 ; MIPS32: sll [[T10]],[[T10]],0x1f
5776 ; MIPS32: sll [[T11]],[[T11]],0x1f
5777 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5778 ; MIPS32: xori [[T11]],[[T11]],0x1
5779 ; MIPS32: andi [[T11]],[[T11]],0xff
5780 ; MIPS32: srl [[T7]],[[T7]],0x8
5781 ; MIPS32: sll [[T7]],[[T7]],0x8
5782 ; MIPS32: or [[T11]],[[T11]],[[T7]]
5783 ; MIPS32: move [[T10]],a3
5784 ; MIPS32: srl [[T10]],[[T10]],0x8
5785 ; MIPS32: andi [[T10]],[[T10]],0xff
5786 ; MIPS32: andi [[T10]],[[T10]],0x1
5787 ; MIPS32: move [[T12]],[[T3]]
5788 ; MIPS32: srl [[T12]],[[T12]],0x8
5789 ; MIPS32: andi [[T12]],[[T12]],0xff
5790 ; MIPS32: andi [[T12]],[[T12]],0x1
5791 ; MIPS32: sll [[T10]],[[T10]],0x1f
5792 ; MIPS32: sll [[T12]],[[T12]],0x1f
5793 ; MIPS32: slt [[T12]],[[T12]],[[T10]]
5794 ; MIPS32: xori [[T12]],[[T12]],0x1
5795 ; MIPS32: andi [[T12]],[[T12]],0xff
5796 ; MIPS32: sll [[T12]],[[T12]],0x8
5797 ; MIPS32: lui [[T10]],0xffff
5798 ; MIPS32: ori [[T10]],[[T10]],0xff
5799 ; MIPS32: and [[T11]],[[T11]],[[T10]]
5800 ; MIPS32: or [[T12]],[[T12]],[[T11]]
5801 ; MIPS32: move [[T10]],a3
5802 ; MIPS32: srl [[T10]],[[T10]],0x10
5803 ; MIPS32: andi [[T10]],[[T10]],0xff
5804 ; MIPS32: andi [[T10]],[[T10]],0x1
5805 ; MIPS32: move [[T11]],[[T3]]
5806 ; MIPS32: srl [[T11]],[[T11]],0x10
5807 ; MIPS32: andi [[T11]],[[T11]],0xff
5808 ; MIPS32: andi [[T11]],[[T11]],0x1
5809 ; MIPS32: sll [[T10]],[[T10]],0x1f
5810 ; MIPS32: sll [[T11]],[[T11]],0x1f
5811 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
5812 ; MIPS32: xori [[T11]],[[T11]],0x1
5813 ; MIPS32: andi [[T11]],[[T11]],0xff
5814 ; MIPS32: sll [[T11]],[[T11]],0x10
5815 ; MIPS32: lui [[T10]],0xff00
5816 ; MIPS32: ori [[T10]],[[T10]],0xffff
5817 ; MIPS32: and [[T12]],[[T12]],[[T10]]
5818 ; MIPS32: or [[T11]],[[T11]],[[T12]]
5819 ; MIPS32: srl [[T13:.*]],a3,0x18
5820 ; MIPS32: andi [[T13]],[[T13]],0x1
5821 ; MIPS32: srl [[T3]],[[T3]],0x18
5158 ; MIPS32: andi [[T3]],[[T3]],0x1 5822 ; MIPS32: andi [[T3]],[[T3]],0x1
5159 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 5823 ; MIPS32: sll [[T13]],[[T13]],0x1f
5160 ; MIPS32: andi [[T2]],[[T2]],0xff
5161 ; MIPS32: andi [[T2]],[[T2]],0x1
5162 ; MIPS32: sll [[T3]],[[T3]],0x1f 5824 ; MIPS32: sll [[T3]],[[T3]],0x1f
5163 ; MIPS32: sll [[T2]],[[T2]],0x1f 5825 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
5164 ; MIPS32: slt [[T2]],[[T2]],[[T3]] 5826 ; MIPS32: xori [[T3]],[[T3]],0x1
5165 ; MIPS32: xori [[T2]],[[T2]],0x1 5827 ; MIPS32: srl [[T3]],[[T3]],0x18
5166 ; MIPS32: andi [[T2]],[[T2]],0xff
5167 ; MIPS32: sll [[T2]],[[T2]],0x10
5168 ; MIPS32: lui [[T3]],0xff00
5169 ; MIPS32: ori [[T3]],[[T3]],0xffff
5170 ; MIPS32: and [[T5]],[[T5]],[[T3]]
5171 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5172 ; MIPS32: srl [[T6:.*]],a1,0x18
5173 ; MIPS32: andi [[T6]],[[T6]],0x1
5174 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5175 ; MIPS32: andi [[T7]],[[T7]],0x1
5176 ; MIPS32: sll [[T6]],[[T6]],0x1f
5177 ; MIPS32: sll [[T7]],[[T7]],0x1f
5178 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
5179 ; MIPS32: xori [[T7]],[[T7]],0x1
5180 ; MIPS32: srl [[T7]],[[T7]],0x18
5181 ; MIPS32: sll [[T2]],[[T2]],0x8
5182 ; MIPS32: srl [[T2]],[[T2]],0x8
5183 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
5184 ; MIPS32: andi [[T3]],a2,0xff
5185 ; MIPS32: andi [[T3]],[[T3]],0x1
5186 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
5187 ; MIPS32: andi [[T6]],[[T6]],0x1
5188 ; MIPS32: sll [[T3]],[[T3]],0x1f
5189 ; MIPS32: sll [[T6]],[[T6]],0x1f
5190 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5191 ; MIPS32: xori [[T6]],[[T6]],0x1
5192 ; MIPS32: andi [[T6]],[[T6]],0xff
5193 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5194 ; MIPS32: sll [[T8]],[[T8]],0x8
5195 ; MIPS32: or [[T6]],[[T6]],[[T8]]
5196 ; MIPS32: srl [[T3]],a2,0x8
5197 ; MIPS32: andi [[T3]],[[T3]],0xff
5198 ; MIPS32: andi [[T3]],[[T3]],0x1
5199 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5200 ; MIPS32: andi [[T2]],[[T2]],0xff
5201 ; MIPS32: andi [[T2]],[[T2]],0x1
5202 ; MIPS32: sll [[T3]],[[T3]],0x1f
5203 ; MIPS32: sll [[T2]],[[T2]],0x1f
5204 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
5205 ; MIPS32: xori [[T2]],[[T2]],0x1
5206 ; MIPS32: andi [[T2]],[[T2]],0xff
5207 ; MIPS32: sll [[T2]],[[T2]],0x8
5208 ; MIPS32: lui [[T3]],0xffff
5209 ; MIPS32: ori [[T3]],[[T3]],0xff
5210 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5211 ; MIPS32: or [[T2]],[[T2]],[[T6]]
5212 ; MIPS32: srl [[T3]],a2,0x10
5213 ; MIPS32: andi [[T3]],[[T3]],0xff
5214 ; MIPS32: andi [[T3]],[[T3]],0x1
5215 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
5216 ; MIPS32: andi [[T6]],[[T6]],0xff
5217 ; MIPS32: andi [[T6]],[[T6]],0x1
5218 ; MIPS32: sll [[T3]],[[T3]],0x1f
5219 ; MIPS32: sll [[T6]],[[T6]],0x1f
5220 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5221 ; MIPS32: xori [[T6]],[[T6]],0x1
5222 ; MIPS32: andi [[T6]],[[T6]],0xff
5223 ; MIPS32: sll [[T6]],[[T6]],0x10
5224 ; MIPS32: lui [[T3]],0xff00
5225 ; MIPS32: ori [[T3]],[[T3]],0xffff
5226 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5227 ; MIPS32: or [[T6]],[[T6]],[[T2]]
5228 ; MIPS32: srl [[T9:.*]],a2,0x18
5229 ; MIPS32: andi [[T9]],[[T9]],0x1
5230 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5231 ; MIPS32: andi [[T10]],[[T10]],0x1
5232 ; MIPS32: sll [[T9]],[[T9]],0x1f
5233 ; MIPS32: sll [[T10]],[[T10]],0x1f
5234 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
5235 ; MIPS32: xori [[T10]],[[T10]],0x1
5236 ; MIPS32: srl [[T10]],[[T10]],0x18
5237 ; MIPS32: sll [[T6]],[[T6]],0x8
5238 ; MIPS32: srl [[T6]],[[T6]],0x8
5239 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5240 ; MIPS32: andi [[T3]],a3,0xff
5241 ; MIPS32: andi [[T3]],[[T3]],0x1
5242 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5243 ; MIPS32: andi [[T6]],[[T6]],0x1
5244 ; MIPS32: sll [[T3]],[[T3]],0x1f
5245 ; MIPS32: sll [[T6]],[[T6]],0x1f
5246 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5247 ; MIPS32: xori [[T6]],[[T6]],0x1
5248 ; MIPS32: andi [[T6]],[[T6]],0xff
5249 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5250 ; MIPS32: sll [[T11]],[[T11]],0x8 5828 ; MIPS32: sll [[T11]],[[T11]],0x8
5251 ; MIPS32: or [[T6]],[[T6]],[[T11]] 5829 ; MIPS32: srl [[T11]],[[T11]],0x8
5252 ; MIPS32: srl [[T3]],a3,0x8 5830 ; MIPS32: or [[T3]],[[T3]],[[T11]]
5253 ; MIPS32: andi [[T3]],[[T3]],0xff 5831 ; MIPS32: move a0,[[T2]]
5254 ; MIPS32: andi [[T3]],[[T3]],0x1 5832 ; MIPS32: move a1,[[T3]]
5255 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5256 ; MIPS32: andi [[T9]],[[T9]],0xff
5257 ; MIPS32: andi [[T9]],[[T9]],0x1
5258 ; MIPS32: sll [[T3]],[[T3]],0x1f
5259 ; MIPS32: sll [[T9]],[[T9]],0x1f
5260 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
5261 ; MIPS32: xori [[T9]],[[T9]],0x1
5262 ; MIPS32: andi [[T9]],[[T9]],0xff
5263 ; MIPS32: sll [[T9]],[[T9]],0x8
5264 ; MIPS32: lui [[T3]],0xffff
5265 ; MIPS32: ori [[T3]],[[T3]],0xff
5266 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5267 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5268 ; MIPS32: srl [[T3]],a3,0x10
5269 ; MIPS32: andi [[T3]],[[T3]],0xff
5270 ; MIPS32: andi [[T3]],[[T3]],0x1
5271 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5272 ; MIPS32: andi [[T6]],[[T6]],0xff
5273 ; MIPS32: andi [[T6]],[[T6]],0x1
5274 ; MIPS32: sll [[T3]],[[T3]],0x1f
5275 ; MIPS32: sll [[T6]],[[T6]],0x1f
5276 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5277 ; MIPS32: xori [[T6]],[[T6]],0x1
5278 ; MIPS32: andi [[T6]],[[T6]],0xff
5279 ; MIPS32: sll [[T6]],[[T6]],0x10
5280 ; MIPS32: lui [[T3]],0xff00
5281 ; MIPS32: ori [[T3]],[[T3]],0xffff
5282 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5283 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5284 ; MIPS32: srl [[T12:.*]],a3,0x18
5285 ; MIPS32: andi [[T12]],[[T12]],0x1
5286 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5287 ; MIPS32: andi [[T13]],[[T13]],0x1
5288 ; MIPS32: sll [[T12]],[[T12]],0x1f
5289 ; MIPS32: sll [[T13]],[[T13]],0x1f
5290 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
5291 ; MIPS32: xori [[T13]],[[T13]],0x1
5292 ; MIPS32: srl [[T13]],[[T13]],0x18
5293 ; MIPS32: sll [[T6]],[[T6]],0x8
5294 ; MIPS32: srl [[T6]],[[T6]],0x8
5295 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
5296 } 5833 }
5297 5834
5298 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) { 5835 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) {
5299 entry: 5836 entry:
5300 %res = icmp slt <16 x i1> %a, %b 5837 %res = icmp slt <16 x i1> %a, %b
5301 ret <16 x i1> %res 5838 ret <16 x i1> %res
5302 ; CHECK-LABEL: test_icmp_v16i1_slt 5839 ; CHECK-LABEL: test_icmp_v16i1_slt
5303 ; CHECK: pcmpgtb 5840 ; CHECK: pcmpgtb
5304 5841
5305 ; MIPS32-LABEL: test_icmp_v16i1_slt 5842 ; MIPS32-LABEL: test_icmp_v16i1_slt
5306 ; MIPS32: lw [[BV_E0:.*]], 5843 ; MIPS32: lw [[T0:.*]],
5307 ; MIPS32: lw [[BV_E1:.*]], 5844 ; MIPS32: lw [[T1:.*]],
5308 ; MIPS32: lw [[BV_E2:.*]], 5845 ; MIPS32: lw [[T2:.*]],
5309 ; MIPS32: lw [[BV_E3:.*]], 5846 ; MIPS32: lw [[T3:.*]],
5310 ; MIPS32: move [[TV_E0:.*]],zero 5847 ; MIPS32: move [[T4:.*]],zero
5311 ; MIPS32: move [[TV_E1:.*]],zero 5848 ; MIPS32: move [[T5:.*]],zero
5312 ; MIPS32: move [[TV_E2:.*]],zero 5849 ; MIPS32: move [[T6:.*]],zero
5313 ; MIPS32: move [[TV_E3:.*]],zero 5850 ; MIPS32: move [[T7:.*]],zero
5314 ; MIPS32: andi [[T0:.*]],a0,0xff 5851 ; MIPS32: move [[T8:.*]],a0
5315 ; MIPS32: andi [[T0]],[[T0]],0x1 5852 ; MIPS32: andi [[T8]],[[T8]],0xff
5316 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 5853 ; MIPS32: andi [[T8]],[[T8]],0x1
5854 ; MIPS32: move [[T9:.*]],[[T0]]
5855 ; MIPS32: andi [[T9]],[[T9]],0xff
5856 ; MIPS32: andi [[T9]],[[T9]],0x1
5857 ; MIPS32: sll [[T8]],[[T8]],0x1f
5858 ; MIPS32: sll [[T9]],[[T9]],0x1f
5859 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
5860 ; MIPS32: andi [[T8]],[[T8]],0xff
5861 ; MIPS32: srl [[T4]],[[T4]],0x8
5862 ; MIPS32: sll [[T4]],[[T4]],0x8
5863 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5864 ; MIPS32: move [[T4]],a0
5865 ; MIPS32: srl [[T4]],[[T4]],0x8
5866 ; MIPS32: andi [[T4]],[[T4]],0xff
5867 ; MIPS32: andi [[T4]],[[T4]],0x1
5868 ; MIPS32: move [[T9]],[[T0]]
5869 ; MIPS32: srl [[T9]],[[T9]],0x8
5870 ; MIPS32: andi [[T9]],[[T9]],0xff
5871 ; MIPS32: andi [[T9]],[[T9]],0x1
5872 ; MIPS32: sll [[T4]],[[T4]],0x1f
5873 ; MIPS32: sll [[T9]],[[T9]],0x1f
5874 ; MIPS32: slt [[T4]],[[T4]],[[T9]]
5875 ; MIPS32: andi [[T4]],[[T4]],0xff
5876 ; MIPS32: sll [[T4]],[[T4]],0x8
5877 ; MIPS32: lui [[T9]],0xffff
5878 ; MIPS32: ori [[T9]],[[T9]],0xff
5879 ; MIPS32: and [[T8]],[[T8]],[[T9]]
5880 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5881 ; MIPS32: move [[T8]],a0
5882 ; MIPS32: srl [[T8]],[[T8]],0x10
5883 ; MIPS32: andi [[T8]],[[T8]],0xff
5884 ; MIPS32: andi [[T8]],[[T8]],0x1
5885 ; MIPS32: move [[T9]],[[T0]]
5886 ; MIPS32: srl [[T9]],[[T9]],0x10
5887 ; MIPS32: andi [[T9]],[[T9]],0xff
5888 ; MIPS32: andi [[T9]],[[T9]],0x1
5889 ; MIPS32: sll [[T8]],[[T8]],0x1f
5890 ; MIPS32: sll [[T9]],[[T9]],0x1f
5891 ; MIPS32: slt [[T8]],[[T8]],[[T9]]
5892 ; MIPS32: andi [[T8]],[[T8]],0xff
5893 ; MIPS32: sll [[T8]],[[T8]],0x10
5894 ; MIPS32: lui [[T9]],0xff00
5895 ; MIPS32: ori [[T9]],[[T9]],0xffff
5896 ; MIPS32: and [[T4]],[[T4]],[[T9]]
5897 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5898 ; MIPS32: srl [[T10:.*]],a0,0x18
5899 ; MIPS32: andi [[T10]],[[T10]],0x1
5900 ; MIPS32: srl [[T0]],[[T0]],0x18
5901 ; MIPS32: andi [[T0]],[[T0]],0x1
5902 ; MIPS32: sll [[T10]],[[T10]],0x1f
5903 ; MIPS32: sll [[T0]],[[T0]],0x1f
5904 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
5905 ; MIPS32: srl [[T10]],[[T10]],0x18
5906 ; MIPS32: sll [[T8]],[[T8]],0x8
5907 ; MIPS32: srl [[T8]],[[T8]],0x8
5908 ; MIPS32: or [[T10]],[[T10]],[[T8]]
5909 ; MIPS32: move [[T0]],a1
5910 ; MIPS32: andi [[T0]],[[T0]],0xff
5911 ; MIPS32: andi [[T0]],[[T0]],0x1
5912 ; MIPS32: move [[T4]],[[T1]]
5913 ; MIPS32: andi [[T4]],[[T4]],0xff
5914 ; MIPS32: andi [[T4]],[[T4]],0x1
5915 ; MIPS32: sll [[T0]],[[T0]],0x1f
5916 ; MIPS32: sll [[T4]],[[T4]],0x1f
5917 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
5918 ; MIPS32: andi [[T0]],[[T0]],0xff
5919 ; MIPS32: srl [[T5]],[[T5]],0x8
5920 ; MIPS32: sll [[T5]],[[T5]],0x8
5921 ; MIPS32: or [[T0]],[[T0]],[[T5]]
5922 ; MIPS32: move [[T4]],a1
5923 ; MIPS32: srl [[T4]],[[T4]],0x8
5924 ; MIPS32: andi [[T4]],[[T4]],0xff
5925 ; MIPS32: andi [[T4]],[[T4]],0x1
5926 ; MIPS32: move [[T5]],[[T1]]
5927 ; MIPS32: srl [[T5]],[[T5]],0x8
5928 ; MIPS32: andi [[T5]],[[T5]],0xff
5929 ; MIPS32: andi [[T5]],[[T5]],0x1
5930 ; MIPS32: sll [[T4]],[[T4]],0x1f
5931 ; MIPS32: sll [[T5]],[[T5]],0x1f
5932 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
5933 ; MIPS32: andi [[T4]],[[T4]],0xff
5934 ; MIPS32: sll [[T4]],[[T4]],0x8
5935 ; MIPS32: lui [[T5]],0xffff
5936 ; MIPS32: ori [[T5]],[[T5]],0xff
5937 ; MIPS32: and [[T0]],[[T0]],[[T5]]
5938 ; MIPS32: or [[T4]],[[T4]],[[T0]]
5939 ; MIPS32: move [[T0]],a1
5940 ; MIPS32: srl [[T0]],[[T0]],0x10
5941 ; MIPS32: andi [[T0]],[[T0]],0xff
5942 ; MIPS32: andi [[T0]],[[T0]],0x1
5943 ; MIPS32: move [[T5]],[[T1]]
5944 ; MIPS32: srl [[T5]],[[T5]],0x10
5945 ; MIPS32: andi [[T5]],[[T5]],0xff
5946 ; MIPS32: andi [[T5]],[[T5]],0x1
5947 ; MIPS32: sll [[T0]],[[T0]],0x1f
5948 ; MIPS32: sll [[T5]],[[T5]],0x1f
5949 ; MIPS32: slt [[T0]],[[T0]],[[T5]]
5950 ; MIPS32: andi [[T0]],[[T0]],0xff
5951 ; MIPS32: sll [[T0]],[[T0]],0x10
5952 ; MIPS32: lui [[T5]],0xff00
5953 ; MIPS32: ori [[T5]],[[T5]],0xffff
5954 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5955 ; MIPS32: or [[T0]],[[T0]],[[T4]]
5956 ; MIPS32: srl [[T11:.*]],a1,0x18
5957 ; MIPS32: andi [[T11]],[[T11]],0x1
5958 ; MIPS32: srl [[T1]],[[T1]],0x18
5959 ; MIPS32: andi [[T1]],[[T1]],0x1
5960 ; MIPS32: sll [[T11]],[[T11]],0x1f
5961 ; MIPS32: sll [[T1]],[[T1]],0x1f
5962 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
5963 ; MIPS32: srl [[T11]],[[T11]],0x18
5964 ; MIPS32: sll [[T0]],[[T0]],0x8
5965 ; MIPS32: srl [[T0]],[[T0]],0x8
5966 ; MIPS32: or [[T11]],[[T11]],[[T0]]
5967 ; MIPS32: move [[T0]],a2
5968 ; MIPS32: andi [[T0]],[[T0]],0xff
5969 ; MIPS32: andi [[T0]],[[T0]],0x1
5970 ; MIPS32: move [[T1]],[[T2]]
5971 ; MIPS32: andi [[T1]],[[T1]],0xff
5317 ; MIPS32: andi [[T1]],[[T1]],0x1 5972 ; MIPS32: andi [[T1]],[[T1]],0x1
5318 ; MIPS32: sll [[T0]],[[T0]],0x1f 5973 ; MIPS32: sll [[T0]],[[T0]],0x1f
5319 ; MIPS32: sll [[T1]],[[T1]],0x1f 5974 ; MIPS32: sll [[T1]],[[T1]],0x1f
5320 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 5975 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
5321 ; MIPS32: andi [[T0]],[[T0]],0xff 5976 ; MIPS32: andi [[T0]],[[T0]],0xff
5322 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 5977 ; MIPS32: srl [[T6]],[[T6]],0x8
5323 ; MIPS32: sll [[T2]],[[T2]],0x8 5978 ; MIPS32: sll [[T6]],[[T6]],0x8
5324 ; MIPS32: or [[T0]],[[T0]],[[T2]] 5979 ; MIPS32: or [[T0]],[[T0]],[[T6]]
5325 ; MIPS32: srl [[T2]],a0,0x8 5980 ; MIPS32: move [[T1]],a2
5981 ; MIPS32: srl [[T1]],[[T1]],0x8
5982 ; MIPS32: andi [[T1]],[[T1]],0xff
5983 ; MIPS32: andi [[T1]],[[T1]],0x1
5984 ; MIPS32: move [[T4]],[[T2]]
5985 ; MIPS32: srl [[T4]],[[T4]],0x8
5986 ; MIPS32: andi [[T4]],[[T4]],0xff
5987 ; MIPS32: andi [[T4]],[[T4]],0x1
5988 ; MIPS32: sll [[T1]],[[T1]],0x1f
5989 ; MIPS32: sll [[T4]],[[T4]],0x1f
5990 ; MIPS32: slt [[T1]],[[T1]],[[T4]]
5991 ; MIPS32: andi [[T1]],[[T1]],0xff
5992 ; MIPS32: sll [[T1]],[[T1]],0x8
5993 ; MIPS32: lui [[T4]],0xffff
5994 ; MIPS32: ori [[T4]],[[T4]],0xff
5995 ; MIPS32: and [[T0]],[[T0]],[[T4]]
5996 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5997 ; MIPS32: move [[T0]],a2
5998 ; MIPS32: srl [[T0]],[[T0]],0x10
5999 ; MIPS32: andi [[T0]],[[T0]],0xff
6000 ; MIPS32: andi [[T0]],[[T0]],0x1
6001 ; MIPS32: move [[T4]],[[T2]]
6002 ; MIPS32: srl [[T4]],[[T4]],0x10
6003 ; MIPS32: andi [[T4]],[[T4]],0xff
6004 ; MIPS32: andi [[T4]],[[T4]],0x1
6005 ; MIPS32: sll [[T0]],[[T0]],0x1f
6006 ; MIPS32: sll [[T4]],[[T4]],0x1f
6007 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
6008 ; MIPS32: andi [[T0]],[[T0]],0xff
6009 ; MIPS32: sll [[T0]],[[T0]],0x10
6010 ; MIPS32: lui [[T4]],0xff00
6011 ; MIPS32: ori [[T4]],[[T4]],0xffff
6012 ; MIPS32: and [[T1]],[[T1]],[[T4]]
6013 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6014 ; MIPS32: srl [[T12:.*]],a2,0x18
6015 ; MIPS32: andi [[T12]],[[T12]],0x1
6016 ; MIPS32: srl [[T2]],[[T2]],0x18
6017 ; MIPS32: andi [[T2]],[[T2]],0x1
6018 ; MIPS32: sll [[T12]],[[T12]],0x1f
6019 ; MIPS32: sll [[T2]],[[T2]],0x1f
6020 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
6021 ; MIPS32: srl [[T12]],[[T12]],0x18
6022 ; MIPS32: sll [[T0]],[[T0]],0x8
6023 ; MIPS32: srl [[T0]],[[T0]],0x8
6024 ; MIPS32: or [[T12]],[[T12]],[[T0]]
6025 ; MIPS32: move [[T0]],a3
6026 ; MIPS32: andi [[T0]],[[T0]],0xff
6027 ; MIPS32: andi [[T0]],[[T0]],0x1
6028 ; MIPS32: move [[T1]],[[T3]]
6029 ; MIPS32: andi [[T1]],[[T1]],0xff
6030 ; MIPS32: andi [[T1]],[[T1]],0x1
6031 ; MIPS32: sll [[T0]],[[T0]],0x1f
6032 ; MIPS32: sll [[T1]],[[T1]],0x1f
6033 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
6034 ; MIPS32: andi [[T0]],[[T0]],0xff
6035 ; MIPS32: srl [[T7]],[[T7]],0x8
6036 ; MIPS32: sll [[T7]],[[T7]],0x8
6037 ; MIPS32: or [[T0]],[[T0]],[[T7]]
6038 ; MIPS32: move [[T1]],a3
6039 ; MIPS32: srl [[T1]],[[T1]],0x8
6040 ; MIPS32: andi [[T1]],[[T1]],0xff
6041 ; MIPS32: andi [[T1]],[[T1]],0x1
6042 ; MIPS32: move [[T2]],[[T3]]
6043 ; MIPS32: srl [[T2]],[[T2]],0x8
5326 ; MIPS32: andi [[T2]],[[T2]],0xff 6044 ; MIPS32: andi [[T2]],[[T2]],0xff
5327 ; MIPS32: andi [[T2]],[[T2]],0x1 6045 ; MIPS32: andi [[T2]],[[T2]],0x1
5328 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 6046 ; MIPS32: sll [[T1]],[[T1]],0x1f
5329 ; MIPS32: andi [[T1]],[[T1]],0xff
5330 ; MIPS32: andi [[T1]],[[T1]],0x1
5331 ; MIPS32: sll [[T2]],[[T2]],0x1f 6047 ; MIPS32: sll [[T2]],[[T2]],0x1f
5332 ; MIPS32: sll [[T1]],[[T1]],0x1f 6048 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
5333 ; MIPS32: slt [[T2]],[[T2]],[[T1]] 6049 ; MIPS32: andi [[T1]],[[T1]],0xff
6050 ; MIPS32: sll [[T1]],[[T1]],0x8
6051 ; MIPS32: lui [[T2]],0xffff
6052 ; MIPS32: ori [[T2]],[[T2]],0xff
6053 ; MIPS32: and [[T0]],[[T0]],[[T2]]
6054 ; MIPS32: or [[T1]],[[T1]],[[T0]]
6055 ; MIPS32: move [[T0]],a3
6056 ; MIPS32: srl [[T0]],[[T0]],0x10
6057 ; MIPS32: andi [[T0]],[[T0]],0xff
6058 ; MIPS32: andi [[T0]],[[T0]],0x1
6059 ; MIPS32: move [[T2]],[[T3]]
6060 ; MIPS32: srl [[T2]],[[T2]],0x10
5334 ; MIPS32: andi [[T2]],[[T2]],0xff 6061 ; MIPS32: andi [[T2]],[[T2]],0xff
5335 ; MIPS32: sll [[T2]],[[T2]],0x8 6062 ; MIPS32: andi [[T2]],[[T2]],0x1
5336 ; MIPS32: lui [[T1]],0xffff 6063 ; MIPS32: sll [[T0]],[[T0]],0x1f
5337 ; MIPS32: ori [[T1]],[[T1]],0xff 6064 ; MIPS32: sll [[T2]],[[T2]],0x1f
5338 ; MIPS32: and [[T0]],[[T0]],[[T1]] 6065 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
5339 ; MIPS32: or [[T2]],[[T2]],[[T0]]
5340 ; MIPS32: srl [[T0]],a0,0x10
5341 ; MIPS32: andi [[T0]],[[T0]],0xff
5342 ; MIPS32: andi [[T0]],[[T0]],0x1
5343 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5344 ; MIPS32: andi [[T1]],[[T1]],0xff
5345 ; MIPS32: andi [[T1]],[[T1]],0x1
5346 ; MIPS32: sll [[T0]],[[T0]],0x1f
5347 ; MIPS32: sll [[T1]],[[T1]],0x1f
5348 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
5349 ; MIPS32: andi [[T0]],[[T0]],0xff 6066 ; MIPS32: andi [[T0]],[[T0]],0xff
5350 ; MIPS32: sll [[T0]],[[T0]],0x10 6067 ; MIPS32: sll [[T0]],[[T0]],0x10
5351 ; MIPS32: lui [[T1]],0xff00 6068 ; MIPS32: lui [[T2]],0xff00
5352 ; MIPS32: ori [[T1]],[[T1]],0xffff 6069 ; MIPS32: ori [[T2]],[[T2]],0xffff
5353 ; MIPS32: and [[T2]],[[T2]],[[T1]] 6070 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5354 ; MIPS32: or [[T0]],[[T0]],[[T2]] 6071 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5355 ; MIPS32: srl [[T3:.*]],a0,0x18 6072 ; MIPS32: srl [[T13:.*]],a3,0x18
6073 ; MIPS32: andi [[T13]],[[T13]],0x1
6074 ; MIPS32: srl [[T3]],[[T3]],0x18
5356 ; MIPS32: andi [[T3]],[[T3]],0x1 6075 ; MIPS32: andi [[T3]],[[T3]],0x1
5357 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 6076 ; MIPS32: sll [[T13]],[[T13]],0x1f
5358 ; MIPS32: andi [[T4]],[[T4]],0x1
5359 ; MIPS32: sll [[T3]],[[T3]],0x1f 6077 ; MIPS32: sll [[T3]],[[T3]],0x1f
5360 ; MIPS32: sll [[T4]],[[T4]],0x1f 6078 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
5361 ; MIPS32: slt [[T3]],[[T3]],[[T4]] 6079 ; MIPS32: srl [[T13]],[[T13]],0x18
5362 ; MIPS32: srl [[T3]],[[T3]],0x18
5363 ; MIPS32: sll [[T0]],[[T0]],0x8 6080 ; MIPS32: sll [[T0]],[[T0]],0x8
5364 ; MIPS32: srl [[T0]],[[T0]],0x8 6081 ; MIPS32: srl [[T0]],[[T0]],0x8
5365 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 6082 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5366 ; MIPS32: andi [[T4]],a1,0xff 6083 ; MIPS32: move v0,[[T10]]
5367 ; MIPS32: andi [[T4]],[[T4]],0x1 6084 ; MIPS32: move v1,[[T11]]
5368 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 6085 ; MIPS32: move a0,[[T12]]
5369 ; MIPS32: andi [[T2]],[[T2]],0x1 6086 ; MIPS32: move a1,[[T13]]
5370 ; MIPS32: sll [[T4]],[[T4]],0x1f
5371 ; MIPS32: sll [[T2]],[[T2]],0x1f
5372 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
5373 ; MIPS32: andi [[T4]],[[T4]],0xff
5374 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5375 ; MIPS32: sll [[T5]],[[T5]],0x8
5376 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5377 ; MIPS32: srl [[T2]],a1,0x8
5378 ; MIPS32: andi [[T2]],[[T2]],0xff
5379 ; MIPS32: andi [[T2]],[[T2]],0x1
5380 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5381 ; MIPS32: andi [[T5]],[[T5]],0xff
5382 ; MIPS32: andi [[T5]],[[T5]],0x1
5383 ; MIPS32: sll [[T2]],[[T2]],0x1f
5384 ; MIPS32: sll [[T5]],[[T5]],0x1f
5385 ; MIPS32: slt [[T2]],[[T2]],[[T5]]
5386 ; MIPS32: andi [[T2]],[[T2]],0xff
5387 ; MIPS32: sll [[T2]],[[T2]],0x8
5388 ; MIPS32: lui [[T5]],0xffff
5389 ; MIPS32: ori [[T5]],[[T5]],0xff
5390 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5391 ; MIPS32: or [[T2]],[[T2]],[[T4]]
5392 ; MIPS32: srl [[T4]],a1,0x10
5393 ; MIPS32: andi [[T4]],[[T4]],0xff
5394 ; MIPS32: andi [[T4]],[[T4]],0x1
5395 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
5396 ; MIPS32: andi [[T5]],[[T5]],0xff
5397 ; MIPS32: andi [[T5]],[[T5]],0x1
5398 ; MIPS32: sll [[T4]],[[T4]],0x1f
5399 ; MIPS32: sll [[T5]],[[T5]],0x1f
5400 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
5401 ; MIPS32: andi [[T4]],[[T4]],0xff
5402 ; MIPS32: sll [[T4]],[[T4]],0x10
5403 ; MIPS32: lui [[T5]],0xff00
5404 ; MIPS32: ori [[T5]],[[T5]],0xffff
5405 ; MIPS32: and [[T2]],[[T2]],[[T5]]
5406 ; MIPS32: or [[T4]],[[T4]],[[T2]]
5407 ; MIPS32: srl [[T6:.*]],a1,0x18
5408 ; MIPS32: andi [[T6]],[[T6]],0x1
5409 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5410 ; MIPS32: andi [[T7]],[[T7]],0x1
5411 ; MIPS32: sll [[T6]],[[T6]],0x1f
5412 ; MIPS32: sll [[T7]],[[T7]],0x1f
5413 ; MIPS32: slt [[T6]],[[T6]],[[T7]]
5414 ; MIPS32: srl [[T6]],[[T6]],0x18
5415 ; MIPS32: sll [[T4]],[[T4]],0x8
5416 ; MIPS32: srl [[T4]],[[T4]],0x8
5417 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
5418 ; MIPS32: andi [[T4]],a2,0xff
5419 ; MIPS32: andi [[T4]],[[T4]],0x1
5420 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
5421 ; MIPS32: andi [[T7]],[[T7]],0x1
5422 ; MIPS32: sll [[T4]],[[T4]],0x1f
5423 ; MIPS32: sll [[T7]],[[T7]],0x1f
5424 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
5425 ; MIPS32: andi [[T4]],[[T4]],0xff
5426 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5427 ; MIPS32: sll [[T8]],[[T8]],0x8
5428 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5429 ; MIPS32: srl [[T7]],a2,0x8
5430 ; MIPS32: andi [[T7]],[[T7]],0xff
5431 ; MIPS32: andi [[T7]],[[T7]],0x1
5432 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5433 ; MIPS32: andi [[T2]],[[T2]],0xff
5434 ; MIPS32: andi [[T2]],[[T2]],0x1
5435 ; MIPS32: sll [[T7]],[[T7]],0x1f
5436 ; MIPS32: sll [[T2]],[[T2]],0x1f
5437 ; MIPS32: slt [[T7]],[[T7]],[[T2]]
5438 ; MIPS32: andi [[T7]],[[T7]],0xff
5439 ; MIPS32: sll [[T7]],[[T7]],0x8
5440 ; MIPS32: lui [[T2]],0xffff
5441 ; MIPS32: ori [[T2]],[[T2]],0xff
5442 ; MIPS32: and [[T4]],[[T4]],[[T2]]
5443 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5444 ; MIPS32: srl [[T4]],a2,0x10
5445 ; MIPS32: andi [[T4]],[[T4]],0xff
5446 ; MIPS32: andi [[T4]],[[T4]],0x1
5447 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
5448 ; MIPS32: andi [[T2]],[[T2]],0xff
5449 ; MIPS32: andi [[T2]],[[T2]],0x1
5450 ; MIPS32: sll [[T4]],[[T4]],0x1f
5451 ; MIPS32: sll [[T2]],[[T2]],0x1f
5452 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
5453 ; MIPS32: andi [[T4]],[[T4]],0xff
5454 ; MIPS32: sll [[T4]],[[T4]],0x10
5455 ; MIPS32: lui [[T2]],0xff00
5456 ; MIPS32: ori [[T2]],[[T2]],0xffff
5457 ; MIPS32: and [[T7]],[[T7]],[[T2]]
5458 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5459 ; MIPS32: srl [[T9:.*]],a2,0x18
5460 ; MIPS32: andi [[T9]],[[T9]],0x1
5461 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5462 ; MIPS32: andi [[T10]],[[T10]],0x1
5463 ; MIPS32: sll [[T9]],[[T9]],0x1f
5464 ; MIPS32: sll [[T10]],[[T10]],0x1f
5465 ; MIPS32: slt [[T9]],[[T9]],[[T10]]
5466 ; MIPS32: srl [[T9]],[[T9]],0x18
5467 ; MIPS32: sll [[T4]],[[T4]],0x8
5468 ; MIPS32: srl [[T4]],[[T4]],0x8
5469 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
5470 ; MIPS32: andi [[T4]],a3,0xff
5471 ; MIPS32: andi [[T4]],[[T4]],0x1
5472 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
5473 ; MIPS32: andi [[T7]],[[T7]],0x1
5474 ; MIPS32: sll [[T4]],[[T4]],0x1f
5475 ; MIPS32: sll [[T7]],[[T7]],0x1f
5476 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
5477 ; MIPS32: andi [[T4]],[[T4]],0xff
5478 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5479 ; MIPS32: sll [[T11]],[[T11]],0x8
5480 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5481 ; MIPS32: srl [[T7]],a3,0x8
5482 ; MIPS32: andi [[T7]],[[T7]],0xff
5483 ; MIPS32: andi [[T7]],[[T7]],0x1
5484 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
5485 ; MIPS32: andi [[T10]],[[T10]],0xff
5486 ; MIPS32: andi [[T10]],[[T10]],0x1
5487 ; MIPS32: sll [[T7]],[[T7]],0x1f
5488 ; MIPS32: sll [[T10]],[[T10]],0x1f
5489 ; MIPS32: slt [[T7]],[[T7]],[[T10]]
5490 ; MIPS32: andi [[T7]],[[T7]],0xff
5491 ; MIPS32: sll [[T7]],[[T7]],0x8
5492 ; MIPS32: lui [[T10]],0xffff
5493 ; MIPS32: ori [[T10]],[[T10]],0xff
5494 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5495 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5496 ; MIPS32: srl [[T4]],a3,0x10
5497 ; MIPS32: andi [[T4]],[[T4]],0xff
5498 ; MIPS32: andi [[T4]],[[T4]],0x1
5499 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
5500 ; MIPS32: andi [[T10]],[[T10]],0xff
5501 ; MIPS32: andi [[T10]],[[T10]],0x1
5502 ; MIPS32: sll [[T4]],[[T4]],0x1f
5503 ; MIPS32: sll [[T10]],[[T10]],0x1f
5504 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5505 ; MIPS32: andi [[T4]],[[T4]],0xff
5506 ; MIPS32: sll [[T4]],[[T4]],0x10
5507 ; MIPS32: lui [[T10]],0xff00
5508 ; MIPS32: ori [[T10]],[[T10]],0xffff
5509 ; MIPS32: and [[T7]],[[T7]],[[T10]]
5510 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5511 ; MIPS32: srl [[T12:.*]],a3,0x18
5512 ; MIPS32: andi [[T12]],[[T12]],0x1
5513 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5514 ; MIPS32: andi [[T13]],[[T13]],0x1
5515 ; MIPS32: sll [[T12]],[[T12]],0x1f
5516 ; MIPS32: sll [[T13]],[[T13]],0x1f
5517 ; MIPS32: slt [[T12]],[[T12]],[[T13]]
5518 ; MIPS32: srl [[T12]],[[T12]],0x18
5519 ; MIPS32: sll [[T4]],[[T4]],0x8
5520 ; MIPS32: srl [[T4]],[[T4]],0x8
5521 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
5522 } 6087 }
5523 6088
5524 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) { 6089 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) {
5525 entry: 6090 entry:
5526 %res = icmp uge <16 x i1> %a, %b 6091 %res = icmp uge <16 x i1> %a, %b
5527 ret <16 x i1> %res 6092 ret <16 x i1> %res
5528 ; CHECK-LABEL: test_icmp_v16i1_uge 6093 ; CHECK-LABEL: test_icmp_v16i1_uge
5529 ; CHECK: pxor 6094 ; CHECK: pxor
5530 ; CHECK: pcmpgtb 6095 ; CHECK: pcmpgtb
5531 ; CHECK: pxor 6096 ; CHECK: pxor
5532 6097
5533 ; MIPS32-LABEL: test_icmp_v16i1_uge 6098 ; MIPS32-LABEL: test_icmp_v16i1_uge
5534 ; MIPS32: lw [[BV_E0:.*]], 6099 ; MIPS32: lw [[T0:.*]],
5535 ; MIPS32: lw [[BV_E1:.*]], 6100 ; MIPS32: lw [[T1:.*]],
5536 ; MIPS32: lw [[BV_E2:.*]], 6101 ; MIPS32: lw [[T2:.*]],
5537 ; MIPS32: lw [[BV_E3:.*]], 6102 ; MIPS32: lw [[T3:.*]],
5538 ; MIPS32: move [[TV_E0:.*]],zero 6103 ; MIPS32: move [[T4:.*]],zero
5539 ; MIPS32: move [[TV_E1:.*]],zero 6104 ; MIPS32: move [[T5:.*]],zero
5540 ; MIPS32: move [[TV_E2:.*]],zero 6105 ; MIPS32: move [[T6:.*]],zero
5541 ; MIPS32: move [[TV_E3:.*]],zero 6106 ; MIPS32: move [[T7:.*]],zero
5542 ; MIPS32: andi [[T0:.*]],a0,0xff 6107 ; MIPS32: move [[T8:.*]],a0
5543 ; MIPS32: andi [[T0]],[[T0]],0x1 6108 ; MIPS32: andi [[T8]],[[T8]],0xff
5544 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 6109 ; MIPS32: andi [[T8]],[[T8]],0x1
6110 ; MIPS32: move [[T9:.*]],[[T0]]
6111 ; MIPS32: andi [[T9]],[[T9]],0xff
6112 ; MIPS32: andi [[T9]],[[T9]],0x1
6113 ; MIPS32: sll [[T8]],[[T8]],0x1f
6114 ; MIPS32: sll [[T9]],[[T9]],0x1f
6115 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
6116 ; MIPS32: xori [[T8]],[[T8]],0x1
6117 ; MIPS32: andi [[T8]],[[T8]],0xff
6118 ; MIPS32: srl [[T4]],[[T4]],0x8
6119 ; MIPS32: sll [[T4]],[[T4]],0x8
6120 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6121 ; MIPS32: move [[T4]],a0
6122 ; MIPS32: srl [[T4]],[[T4]],0x8
6123 ; MIPS32: andi [[T4]],[[T4]],0xff
6124 ; MIPS32: andi [[T4]],[[T4]],0x1
6125 ; MIPS32: move [[T9]],[[T0]]
6126 ; MIPS32: srl [[T9]],[[T9]],0x8
6127 ; MIPS32: andi [[T9]],[[T9]],0xff
6128 ; MIPS32: andi [[T9]],[[T9]],0x1
6129 ; MIPS32: sll [[T4]],[[T4]],0x1f
6130 ; MIPS32: sll [[T9]],[[T9]],0x1f
6131 ; MIPS32: sltu [[T4]],[[T4]],[[T9]]
6132 ; MIPS32: xori [[T4]],[[T4]],0x1
6133 ; MIPS32: andi [[T4]],[[T4]],0xff
6134 ; MIPS32: sll [[T4]],[[T4]],0x8
6135 ; MIPS32: lui [[T9]],0xffff
6136 ; MIPS32: ori [[T9]],[[T9]],0xff
6137 ; MIPS32: and [[T8]],[[T8]],[[T9]]
6138 ; MIPS32: or [[T4]],[[T4]],[[T8]]
6139 ; MIPS32: move [[T8]],a0
6140 ; MIPS32: srl [[T8]],[[T8]],0x10
6141 ; MIPS32: andi [[T8]],[[T8]],0xff
6142 ; MIPS32: andi [[T8]],[[T8]],0x1
6143 ; MIPS32: move [[T9]],[[T0]]
6144 ; MIPS32: srl [[T9]],[[T9]],0x10
6145 ; MIPS32: andi [[T9]],[[T9]],0xff
6146 ; MIPS32: andi [[T9]],[[T9]],0x1
6147 ; MIPS32: sll [[T8]],[[T8]],0x1f
6148 ; MIPS32: sll [[T9]],[[T9]],0x1f
6149 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
6150 ; MIPS32: xori [[T8]],[[T8]],0x1
6151 ; MIPS32: andi [[T8]],[[T8]],0xff
6152 ; MIPS32: sll [[T8]],[[T8]],0x10
6153 ; MIPS32: lui [[T9]],0xff00
6154 ; MIPS32: ori [[T9]],[[T9]],0xffff
6155 ; MIPS32: and [[T4]],[[T4]],[[T9]]
6156 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6157 ; MIPS32: srl [[T10:.*]],a0,0x18
6158 ; MIPS32: andi [[T10]],[[T10]],0x1
6159 ; MIPS32: srl [[T0]],[[T0]],0x18
6160 ; MIPS32: andi [[T0]],[[T0]],0x1
6161 ; MIPS32: sll [[T10]],[[T10]],0x1f
6162 ; MIPS32: sll [[T0]],[[T0]],0x1f
6163 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
6164 ; MIPS32: xori [[T10]],[[T10]],0x1
6165 ; MIPS32: srl [[T10]],[[T10]],0x18
6166 ; MIPS32: sll [[T8]],[[T8]],0x8
6167 ; MIPS32: srl [[T8]],[[T8]],0x8
6168 ; MIPS32: or [[T10]],[[T10]],[[T8]]
6169 ; MIPS32: move [[T0]],a1
6170 ; MIPS32: andi [[T0]],[[T0]],0xff
6171 ; MIPS32: andi [[T0]],[[T0]],0x1
6172 ; MIPS32: move [[T4]],[[T1]]
6173 ; MIPS32: andi [[T4]],[[T4]],0xff
6174 ; MIPS32: andi [[T4]],[[T4]],0x1
6175 ; MIPS32: sll [[T0]],[[T0]],0x1f
6176 ; MIPS32: sll [[T4]],[[T4]],0x1f
6177 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
6178 ; MIPS32: xori [[T0]],[[T0]],0x1
6179 ; MIPS32: andi [[T0]],[[T0]],0xff
6180 ; MIPS32: srl [[T5]],[[T5]],0x8
6181 ; MIPS32: sll [[T5]],[[T5]],0x8
6182 ; MIPS32: or [[T0]],[[T0]],[[T5]]
6183 ; MIPS32: move [[T4]],a1
6184 ; MIPS32: srl [[T4]],[[T4]],0x8
6185 ; MIPS32: andi [[T4]],[[T4]],0xff
6186 ; MIPS32: andi [[T4]],[[T4]],0x1
6187 ; MIPS32: move [[T5]],[[T1]]
6188 ; MIPS32: srl [[T5]],[[T5]],0x8
6189 ; MIPS32: andi [[T5]],[[T5]],0xff
6190 ; MIPS32: andi [[T5]],[[T5]],0x1
6191 ; MIPS32: sll [[T4]],[[T4]],0x1f
6192 ; MIPS32: sll [[T5]],[[T5]],0x1f
6193 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
6194 ; MIPS32: xori [[T4]],[[T4]],0x1
6195 ; MIPS32: andi [[T4]],[[T4]],0xff
6196 ; MIPS32: sll [[T4]],[[T4]],0x8
6197 ; MIPS32: lui [[T5]],0xffff
6198 ; MIPS32: ori [[T5]],[[T5]],0xff
6199 ; MIPS32: and [[T0]],[[T0]],[[T5]]
6200 ; MIPS32: or [[T4]],[[T4]],[[T0]]
6201 ; MIPS32: move [[T0]],a1
6202 ; MIPS32: srl [[T0]],[[T0]],0x10
6203 ; MIPS32: andi [[T0]],[[T0]],0xff
6204 ; MIPS32: andi [[T0]],[[T0]],0x1
6205 ; MIPS32: move [[T5]],[[T1]]
6206 ; MIPS32: srl [[T5]],[[T5]],0x10
6207 ; MIPS32: andi [[T5]],[[T5]],0xff
6208 ; MIPS32: andi [[T5]],[[T5]],0x1
6209 ; MIPS32: sll [[T0]],[[T0]],0x1f
6210 ; MIPS32: sll [[T5]],[[T5]],0x1f
6211 ; MIPS32: sltu [[T0]],[[T0]],[[T5]]
6212 ; MIPS32: xori [[T0]],[[T0]],0x1
6213 ; MIPS32: andi [[T0]],[[T0]],0xff
6214 ; MIPS32: sll [[T0]],[[T0]],0x10
6215 ; MIPS32: lui [[T5]],0xff00
6216 ; MIPS32: ori [[T5]],[[T5]],0xffff
6217 ; MIPS32: and [[T4]],[[T4]],[[T5]]
6218 ; MIPS32: or [[T0]],[[T0]],[[T4]]
6219 ; MIPS32: srl [[T11:.*]],a1,0x18
6220 ; MIPS32: andi [[T11]],[[T11]],0x1
6221 ; MIPS32: srl [[T1]],[[T1]],0x18
6222 ; MIPS32: andi [[T1]],[[T1]],0x1
6223 ; MIPS32: sll [[T11]],[[T11]],0x1f
6224 ; MIPS32: sll [[T1]],[[T1]],0x1f
6225 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
6226 ; MIPS32: xori [[T11]],[[T11]],0x1
6227 ; MIPS32: srl [[T11]],[[T11]],0x18
6228 ; MIPS32: sll [[T0]],[[T0]],0x8
6229 ; MIPS32: srl [[T0]],[[T0]],0x8
6230 ; MIPS32: or [[T11]],[[T11]],[[T0]]
6231 ; MIPS32: move [[T0]],a2
6232 ; MIPS32: andi [[T0]],[[T0]],0xff
6233 ; MIPS32: andi [[T0]],[[T0]],0x1
6234 ; MIPS32: move [[T1]],[[T2]]
6235 ; MIPS32: andi [[T1]],[[T1]],0xff
5545 ; MIPS32: andi [[T1]],[[T1]],0x1 6236 ; MIPS32: andi [[T1]],[[T1]],0x1
5546 ; MIPS32: sll [[T0]],[[T0]],0x1f 6237 ; MIPS32: sll [[T0]],[[T0]],0x1f
5547 ; MIPS32: sll [[T1]],[[T1]],0x1f 6238 ; MIPS32: sll [[T1]],[[T1]],0x1f
5548 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 6239 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
5549 ; MIPS32: xori [[T0]],[[T0]],0x1 6240 ; MIPS32: xori [[T0]],[[T0]],0x1
5550 ; MIPS32: andi [[T0]],[[T0]],0xff 6241 ; MIPS32: andi [[T0]],[[T0]],0xff
5551 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 6242 ; MIPS32: srl [[T6]],[[T6]],0x8
5552 ; MIPS32: sll [[T2]],[[T2]],0x8 6243 ; MIPS32: sll [[T6]],[[T6]],0x8
5553 ; MIPS32: or [[T0]],[[T0]],[[T2]] 6244 ; MIPS32: or [[T0]],[[T0]],[[T6]]
5554 ; MIPS32: srl [[T2]],a0,0x8 6245 ; MIPS32: move [[T1]],a2
5555 ; MIPS32: andi [[T2]],[[T2]],0xff 6246 ; MIPS32: srl [[T1]],[[T1]],0x8
6247 ; MIPS32: andi [[T1]],[[T1]],0xff
6248 ; MIPS32: andi [[T1]],[[T1]],0x1
6249 ; MIPS32: move [[T4]],[[T2]]
6250 ; MIPS32: srl [[T4]],[[T4]],0x8
6251 ; MIPS32: andi [[T4]],[[T4]],0xff
6252 ; MIPS32: andi [[T4]],[[T4]],0x1
6253 ; MIPS32: sll [[T1]],[[T1]],0x1f
6254 ; MIPS32: sll [[T4]],[[T4]],0x1f
6255 ; MIPS32: sltu [[T1]],[[T1]],[[T4]]
6256 ; MIPS32: xori [[T1]],[[T1]],0x1
6257 ; MIPS32: andi [[T1]],[[T1]],0xff
6258 ; MIPS32: sll [[T1]],[[T1]],0x8
6259 ; MIPS32: lui [[T4]],0xffff
6260 ; MIPS32: ori [[T4]],[[T4]],0xff
6261 ; MIPS32: and [[T0]],[[T0]],[[T4]]
6262 ; MIPS32: or [[T1]],[[T1]],[[T0]]
6263 ; MIPS32: move [[T0]],a2
6264 ; MIPS32: srl [[T0]],[[T0]],0x10
6265 ; MIPS32: andi [[T0]],[[T0]],0xff
6266 ; MIPS32: andi [[T0]],[[T0]],0x1
6267 ; MIPS32: move [[T4]],[[T2]]
6268 ; MIPS32: srl [[T4]],[[T4]],0x10
6269 ; MIPS32: andi [[T4]],[[T4]],0xff
6270 ; MIPS32: andi [[T4]],[[T4]],0x1
6271 ; MIPS32: sll [[T0]],[[T0]],0x1f
6272 ; MIPS32: sll [[T4]],[[T4]],0x1f
6273 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
6274 ; MIPS32: xori [[T0]],[[T0]],0x1
6275 ; MIPS32: andi [[T0]],[[T0]],0xff
6276 ; MIPS32: sll [[T0]],[[T0]],0x10
6277 ; MIPS32: lui [[T4]],0xff00
6278 ; MIPS32: ori [[T4]],[[T4]],0xffff
6279 ; MIPS32: and [[T1]],[[T1]],[[T4]]
6280 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6281 ; MIPS32: srl [[T12:.*]],a2,0x18
6282 ; MIPS32: andi [[T12]],[[T12]],0x1
6283 ; MIPS32: srl [[T2]],[[T2]],0x18
5556 ; MIPS32: andi [[T2]],[[T2]],0x1 6284 ; MIPS32: andi [[T2]],[[T2]],0x1
5557 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 6285 ; MIPS32: sll [[T12]],[[T12]],0x1f
5558 ; MIPS32: andi [[T1]],[[T1]],0xff
5559 ; MIPS32: andi [[T1]],[[T1]],0x1
5560 ; MIPS32: sll [[T2]],[[T2]],0x1f 6286 ; MIPS32: sll [[T2]],[[T2]],0x1f
5561 ; MIPS32: sll [[T1]],[[T1]],0x1f 6287 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
5562 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 6288 ; MIPS32: xori [[T12]],[[T12]],0x1
5563 ; MIPS32: xori [[T2]],[[T2]],0x1 6289 ; MIPS32: srl [[T12]],[[T12]],0x18
5564 ; MIPS32: andi [[T2]],[[T2]],0xff 6290 ; MIPS32: sll [[T0]],[[T0]],0x8
5565 ; MIPS32: sll [[T2]],[[T2]],0x8 6291 ; MIPS32: srl [[T0]],[[T0]],0x8
5566 ; MIPS32: lui [[T1]],0xffff 6292 ; MIPS32: or [[T12]],[[T12]],[[T0]]
5567 ; MIPS32: ori [[T1]],[[T1]],0xff 6293 ; MIPS32: move [[T0]],a3
5568 ; MIPS32: and [[T0]],[[T0]],[[T1]] 6294 ; MIPS32: andi [[T0]],[[T0]],0xff
5569 ; MIPS32: or [[T2]],[[T2]],[[T0]] 6295 ; MIPS32: andi [[T0]],[[T0]],0x1
5570 ; MIPS32: srl [[T0]],a0,0x10 6296 ; MIPS32: move [[T1]],[[T3]]
5571 ; MIPS32: andi [[T0]],[[T0]],0xff 6297 ; MIPS32: andi [[T1]],[[T1]],0xff
5572 ; MIPS32: andi [[T0]],[[T0]],0x1 6298 ; MIPS32: andi [[T1]],[[T1]],0x1
5573 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 6299 ; MIPS32: sll [[T0]],[[T0]],0x1f
5574 ; MIPS32: andi [[T1]],[[T1]],0xff
5575 ; MIPS32: andi [[T1]],[[T1]],0x1
5576 ; MIPS32: sll [[T0]],[[T0]],0x1f
5577 ; MIPS32: sll [[T1]],[[T1]],0x1f 6300 ; MIPS32: sll [[T1]],[[T1]],0x1f
5578 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 6301 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
5579 ; MIPS32: xori [[T0]],[[T0]],0x1 6302 ; MIPS32: xori [[T0]],[[T0]],0x1
5580 ; MIPS32: andi [[T0]],[[T0]],0xff 6303 ; MIPS32: andi [[T0]],[[T0]],0xff
6304 ; MIPS32: srl [[T7]],[[T7]],0x8
6305 ; MIPS32: sll [[T7]],[[T7]],0x8
6306 ; MIPS32: or [[T0]],[[T0]],[[T7]]
6307 ; MIPS32: move [[T1]],a3
6308 ; MIPS32: srl [[T1]],[[T1]],0x8
6309 ; MIPS32: andi [[T1]],[[T1]],0xff
6310 ; MIPS32: andi [[T1]],[[T1]],0x1
6311 ; MIPS32: move [[T2]],[[T3]]
6312 ; MIPS32: srl [[T2]],[[T2]],0x8
6313 ; MIPS32: andi [[T2]],[[T2]],0xff
6314 ; MIPS32: andi [[T2]],[[T2]],0x1
6315 ; MIPS32: sll [[T1]],[[T1]],0x1f
6316 ; MIPS32: sll [[T2]],[[T2]],0x1f
6317 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
6318 ; MIPS32: xori [[T1]],[[T1]],0x1
6319 ; MIPS32: andi [[T1]],[[T1]],0xff
6320 ; MIPS32: sll [[T1]],[[T1]],0x8
6321 ; MIPS32: lui [[T2]],0xffff
6322 ; MIPS32: ori [[T2]],[[T2]],0xff
6323 ; MIPS32: and [[T0]],[[T0]],[[T2]]
6324 ; MIPS32: or [[T1]],[[T1]],[[T0]]
6325 ; MIPS32: move [[T0]],a3
6326 ; MIPS32: srl [[T0]],[[T0]],0x10
6327 ; MIPS32: andi [[T0]],[[T0]],0xff
6328 ; MIPS32: andi [[T0]],[[T0]],0x1
6329 ; MIPS32: move [[T2]],[[T3]]
6330 ; MIPS32: srl [[T2]],[[T2]],0x10
6331 ; MIPS32: andi [[T2]],[[T2]],0xff
6332 ; MIPS32: andi [[T2]],[[T2]],0x1
6333 ; MIPS32: sll [[T0]],[[T0]],0x1f
6334 ; MIPS32: sll [[T2]],[[T2]],0x1f
6335 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
6336 ; MIPS32: xori [[T0]],[[T0]],0x1
6337 ; MIPS32: andi [[T0]],[[T0]],0xff
5581 ; MIPS32: sll [[T0]],[[T0]],0x10 6338 ; MIPS32: sll [[T0]],[[T0]],0x10
5582 ; MIPS32: lui [[T1]],0xff00 6339 ; MIPS32: lui [[T2]],0xff00
5583 ; MIPS32: ori [[T1]],[[T1]],0xffff 6340 ; MIPS32: ori [[T2]],[[T2]],0xffff
5584 ; MIPS32: and [[T2]],[[T2]],[[T1]] 6341 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5585 ; MIPS32: or [[T0]],[[T0]],[[T2]] 6342 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5586 ; MIPS32: srl [[T3:.*]],a0,0x18 6343 ; MIPS32: srl [[T13:.*]],a3,0x18
6344 ; MIPS32: andi [[T13]],[[T13]],0x1
6345 ; MIPS32: srl [[T3]],[[T3]],0x18
5587 ; MIPS32: andi [[T3]],[[T3]],0x1 6346 ; MIPS32: andi [[T3]],[[T3]],0x1
5588 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 6347 ; MIPS32: sll [[T13]],[[T13]],0x1f
5589 ; MIPS32: andi [[T4]],[[T4]],0x1
5590 ; MIPS32: sll [[T3]],[[T3]],0x1f 6348 ; MIPS32: sll [[T3]],[[T3]],0x1f
5591 ; MIPS32: sll [[T4]],[[T4]],0x1f 6349 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
5592 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 6350 ; MIPS32: xori [[T13]],[[T13]],0x1
5593 ; MIPS32: xori [[T3]],[[T3]],0x1 6351 ; MIPS32: srl [[T13]],[[T13]],0x18
5594 ; MIPS32: srl [[T3]],[[T3]],0x18
5595 ; MIPS32: sll [[T0]],[[T0]],0x8 6352 ; MIPS32: sll [[T0]],[[T0]],0x8
5596 ; MIPS32: srl [[T0]],[[T0]],0x8 6353 ; MIPS32: srl [[T0]],[[T0]],0x8
5597 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 6354 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5598 ; MIPS32: andi [[T4]],a1,0xff 6355 ; MIPS32: move v0,[[T10]]
5599 ; MIPS32: andi [[T4]],[[T4]],0x1 6356 ; MIPS32: move v1,[[T11]]
5600 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 6357 ; MIPS32: move a0,[[T12]]
5601 ; MIPS32: andi [[T2]],[[T2]],0x1 6358 ; MIPS32: move a1,[[T13]]
5602 ; MIPS32: sll [[T4]],[[T4]],0x1f
5603 ; MIPS32: sll [[T2]],[[T2]],0x1f
5604 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
5605 ; MIPS32: xori [[T4]],[[T4]],0x1
5606 ; MIPS32: andi [[T4]],[[T4]],0xff
5607 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5608 ; MIPS32: sll [[T5]],[[T5]],0x8
5609 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5610 ; MIPS32: srl [[T2]],a1,0x8
5611 ; MIPS32: andi [[T2]],[[T2]],0xff
5612 ; MIPS32: andi [[T2]],[[T2]],0x1
5613 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5614 ; MIPS32: andi [[T5]],[[T5]],0xff
5615 ; MIPS32: andi [[T5]],[[T5]],0x1
5616 ; MIPS32: sll [[T2]],[[T2]],0x1f
5617 ; MIPS32: sll [[T5]],[[T5]],0x1f
5618 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
5619 ; MIPS32: xori [[T2]],[[T2]],0x1
5620 ; MIPS32: andi [[T2]],[[T2]],0xff
5621 ; MIPS32: sll [[T2]],[[T2]],0x8
5622 ; MIPS32: lui [[T5]],0xffff
5623 ; MIPS32: ori [[T5]],[[T5]],0xff
5624 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5625 ; MIPS32: or [[T2]],[[T2]],[[T4]]
5626 ; MIPS32: srl [[T4]],a1,0x10
5627 ; MIPS32: andi [[T4]],[[T4]],0xff
5628 ; MIPS32: andi [[T4]],[[T4]],0x1
5629 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
5630 ; MIPS32: andi [[T5]],[[T5]],0xff
5631 ; MIPS32: andi [[T5]],[[T5]],0x1
5632 ; MIPS32: sll [[T4]],[[T4]],0x1f
5633 ; MIPS32: sll [[T5]],[[T5]],0x1f
5634 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
5635 ; MIPS32: xori [[T4]],[[T4]],0x1
5636 ; MIPS32: andi [[T4]],[[T4]],0xff
5637 ; MIPS32: sll [[T4]],[[T4]],0x10
5638 ; MIPS32: lui [[T5]],0xff00
5639 ; MIPS32: ori [[T5]],[[T5]],0xffff
5640 ; MIPS32: and [[T2]],[[T2]],[[T5]]
5641 ; MIPS32: or [[T4]],[[T4]],[[T2]]
5642 ; MIPS32: srl [[T6:.*]],a1,0x18
5643 ; MIPS32: andi [[T6]],[[T6]],0x1
5644 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5645 ; MIPS32: andi [[T7]],[[T7]],0x1
5646 ; MIPS32: sll [[T6]],[[T6]],0x1f
5647 ; MIPS32: sll [[T7]],[[T7]],0x1f
5648 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
5649 ; MIPS32: xori [[T6]],[[T6]],0x1
5650 ; MIPS32: srl [[T6]],[[T6]],0x18
5651 ; MIPS32: sll [[T4]],[[T4]],0x8
5652 ; MIPS32: srl [[T4]],[[T4]],0x8
5653 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
5654 ; MIPS32: andi [[T4]],a2,0xff
5655 ; MIPS32: andi [[T4]],[[T4]],0x1
5656 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
5657 ; MIPS32: andi [[T7]],[[T7]],0x1
5658 ; MIPS32: sll [[T4]],[[T4]],0x1f
5659 ; MIPS32: sll [[T7]],[[T7]],0x1f
5660 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
5661 ; MIPS32: xori [[T4]],[[T4]],0x1
5662 ; MIPS32: andi [[T4]],[[T4]],0xff
5663 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5664 ; MIPS32: sll [[T8]],[[T8]],0x8
5665 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5666 ; MIPS32: srl [[T7]],a2,0x8
5667 ; MIPS32: andi [[T7]],[[T7]],0xff
5668 ; MIPS32: andi [[T7]],[[T7]],0x1
5669 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5670 ; MIPS32: andi [[T2]],[[T2]],0xff
5671 ; MIPS32: andi [[T2]],[[T2]],0x1
5672 ; MIPS32: sll [[T7]],[[T7]],0x1f
5673 ; MIPS32: sll [[T2]],[[T2]],0x1f
5674 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
5675 ; MIPS32: xori [[T7]],[[T7]],0x1
5676 ; MIPS32: andi [[T7]],[[T7]],0xff
5677 ; MIPS32: sll [[T7]],[[T7]],0x8
5678 ; MIPS32: lui [[T2]],0xffff
5679 ; MIPS32: ori [[T2]],[[T2]],0xff
5680 ; MIPS32: and [[T4]],[[T4]],[[T2]]
5681 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5682 ; MIPS32: srl [[T4]],a2,0x10
5683 ; MIPS32: andi [[T4]],[[T4]],0xff
5684 ; MIPS32: andi [[T4]],[[T4]],0x1
5685 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
5686 ; MIPS32: andi [[T2]],[[T2]],0xff
5687 ; MIPS32: andi [[T2]],[[T2]],0x1
5688 ; MIPS32: sll [[T4]],[[T4]],0x1f
5689 ; MIPS32: sll [[T2]],[[T2]],0x1f
5690 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
5691 ; MIPS32: xori [[T4]],[[T4]],0x1
5692 ; MIPS32: andi [[T4]],[[T4]],0xff
5693 ; MIPS32: sll [[T4]],[[T4]],0x10
5694 ; MIPS32: lui [[T2]],0xff00
5695 ; MIPS32: ori [[T2]],[[T2]],0xffff
5696 ; MIPS32: and [[T7]],[[T7]],[[T2]]
5697 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5698 ; MIPS32: srl [[T9:.*]],a2,0x18
5699 ; MIPS32: andi [[T9]],[[T9]],0x1
5700 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5701 ; MIPS32: andi [[T10]],[[T10]],0x1
5702 ; MIPS32: sll [[T9]],[[T9]],0x1f
5703 ; MIPS32: sll [[T10]],[[T10]],0x1f
5704 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
5705 ; MIPS32: xori [[T9]],[[T9]],0x1
5706 ; MIPS32: srl [[T9]],[[T9]],0x18
5707 ; MIPS32: sll [[T4]],[[T4]],0x8
5708 ; MIPS32: srl [[T4]],[[T4]],0x8
5709 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
5710 ; MIPS32: andi [[T4]],a3,0xff
5711 ; MIPS32: andi [[T4]],[[T4]],0x1
5712 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
5713 ; MIPS32: andi [[T7]],[[T7]],0x1
5714 ; MIPS32: sll [[T4]],[[T4]],0x1f
5715 ; MIPS32: sll [[T7]],[[T7]],0x1f
5716 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
5717 ; MIPS32: xori [[T4]],[[T4]],0x1
5718 ; MIPS32: andi [[T4]],[[T4]],0xff
5719 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5720 ; MIPS32: sll [[T11]],[[T11]],0x8
5721 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5722 ; MIPS32: srl [[T7]],a3,0x8
5723 ; MIPS32: andi [[T7]],[[T7]],0xff
5724 ; MIPS32: andi [[T7]],[[T7]],0x1
5725 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
5726 ; MIPS32: andi [[T10]],[[T10]],0xff
5727 ; MIPS32: andi [[T10]],[[T10]],0x1
5728 ; MIPS32: sll [[T7]],[[T7]],0x1f
5729 ; MIPS32: sll [[T10]],[[T10]],0x1f
5730 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
5731 ; MIPS32: xori [[T7]],[[T7]],0x1
5732 ; MIPS32: andi [[T7]],[[T7]],0xff
5733 ; MIPS32: sll [[T7]],[[T7]],0x8
5734 ; MIPS32: lui [[T10]],0xffff
5735 ; MIPS32: ori [[T10]],[[T10]],0xff
5736 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5737 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5738 ; MIPS32: srl [[T4]],a3,0x10
5739 ; MIPS32: andi [[T4]],[[T4]],0xff
5740 ; MIPS32: andi [[T4]],[[T4]],0x1
5741 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
5742 ; MIPS32: andi [[T10]],[[T10]],0xff
5743 ; MIPS32: andi [[T10]],[[T10]],0x1
5744 ; MIPS32: sll [[T4]],[[T4]],0x1f
5745 ; MIPS32: sll [[T10]],[[T10]],0x1f
5746 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
5747 ; MIPS32: xori [[T4]],[[T4]],0x1
5748 ; MIPS32: andi [[T4]],[[T4]],0xff
5749 ; MIPS32: sll [[T4]],[[T4]],0x10
5750 ; MIPS32: lui [[T10]],0xff00
5751 ; MIPS32: ori [[T10]],[[T10]],0xffff
5752 ; MIPS32: and [[T7]],[[T7]],[[T10]]
5753 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5754 ; MIPS32: srl [[T12:.*]],a3,0x18
5755 ; MIPS32: andi [[T12]],[[T12]],0x1
5756 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5757 ; MIPS32: andi [[T13]],[[T13]],0x1
5758 ; MIPS32: sll [[T12]],[[T12]],0x1f
5759 ; MIPS32: sll [[T13]],[[T13]],0x1f
5760 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
5761 ; MIPS32: xori [[T12]],[[T12]],0x1
5762 ; MIPS32: srl [[T12]],[[T12]],0x18
5763 ; MIPS32: sll [[T4]],[[T4]],0x8
5764 ; MIPS32: srl [[T4]],[[T4]],0x8
5765 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
5766 } 6359 }
5767 6360
5768 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) { 6361 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) {
5769 entry: 6362 entry:
5770 %res = icmp ugt <16 x i1> %a, %b 6363 %res = icmp ugt <16 x i1> %a, %b
5771 ret <16 x i1> %res 6364 ret <16 x i1> %res
5772 ; CHECK-LABEL: test_icmp_v16i1_ugt 6365 ; CHECK-LABEL: test_icmp_v16i1_ugt
5773 ; CHECK: pxor 6366 ; CHECK: pxor
5774 ; CHECK: pcmpgtb 6367 ; CHECK: pcmpgtb
5775 6368
5776 ; MIPS32-LABEL: test_icmp_v16i1_ugt 6369 ; MIPS32-LABEL: test_icmp_v16i1_ugt
5777 ; MIPS32: lw [[BV_E0:.*]], 6370 ; MIPS32: lw [[T0:.*]],
5778 ; MIPS32: lw [[BV_E1:.*]], 6371 ; MIPS32: lw [[T1:.*]],
5779 ; MIPS32: lw [[BV_E2:.*]], 6372 ; MIPS32: lw [[T2:.*]],
5780 ; MIPS32: lw [[BV_E3:.*]], 6373 ; MIPS32: lw [[T3:.*]],
5781 ; MIPS32: move [[TV_E0:.*]],zero 6374 ; MIPS32: move [[T4:.*]],zero
5782 ; MIPS32: move [[TV_E1:.*]],zero 6375 ; MIPS32: move [[T5:.*]],zero
5783 ; MIPS32: move [[TV_E2:.*]],zero 6376 ; MIPS32: move [[T6:.*]],zero
5784 ; MIPS32: move [[TV_E3:.*]],zero 6377 ; MIPS32: move [[T7:.*]],zero
5785 ; MIPS32: andi [[T0:.*]],a0,0xff 6378 ; MIPS32: move [[T8:.*]],a0
6379 ; MIPS32: andi [[T8]],[[T8]],0xff
6380 ; MIPS32: andi [[T8]],[[T8]],0x1
6381 ; MIPS32: move [[T9:.*]],[[T0]]
6382 ; MIPS32: andi [[T9]],[[T9]],0xff
6383 ; MIPS32: andi [[T9]],[[T9]],0x1
6384 ; MIPS32: sll [[T8]],[[T8]],0x1f
6385 ; MIPS32: sll [[T9]],[[T9]],0x1f
6386 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
6387 ; MIPS32: andi [[T9]],[[T9]],0xff
6388 ; MIPS32: srl [[T4]],[[T4]],0x8
6389 ; MIPS32: sll [[T4]],[[T4]],0x8
6390 ; MIPS32: or [[T9]],[[T9]],[[T4]]
6391 ; MIPS32: move [[T4]],a0
6392 ; MIPS32: srl [[T4]],[[T4]],0x8
6393 ; MIPS32: andi [[T4]],[[T4]],0xff
6394 ; MIPS32: andi [[T4]],[[T4]],0x1
6395 ; MIPS32: move [[T8]],[[T0]]
6396 ; MIPS32: srl [[T8]],[[T8]],0x8
6397 ; MIPS32: andi [[T8]],[[T8]],0xff
6398 ; MIPS32: andi [[T8]],[[T8]],0x1
6399 ; MIPS32: sll [[T4]],[[T4]],0x1f
6400 ; MIPS32: sll [[T8]],[[T8]],0x1f
6401 ; MIPS32: sltu [[T8]],[[T8]],[[T4]]
6402 ; MIPS32: andi [[T8]],[[T8]],0xff
6403 ; MIPS32: sll [[T8]],[[T8]],0x8
6404 ; MIPS32: lui [[T4]],0xffff
6405 ; MIPS32: ori [[T4]],[[T4]],0xff
6406 ; MIPS32: and [[T9]],[[T9]],[[T4]]
6407 ; MIPS32: or [[T8]],[[T8]],[[T9]]
6408 ; MIPS32: move [[T4]],a0
6409 ; MIPS32: srl [[T4]],[[T4]],0x10
6410 ; MIPS32: andi [[T4]],[[T4]],0xff
6411 ; MIPS32: andi [[T4]],[[T4]],0x1
6412 ; MIPS32: move [[T9]],[[T0]]
6413 ; MIPS32: srl [[T9]],[[T9]],0x10
6414 ; MIPS32: andi [[T9]],[[T9]],0xff
6415 ; MIPS32: andi [[T9]],[[T9]],0x1
6416 ; MIPS32: sll [[T4]],[[T4]],0x1f
6417 ; MIPS32: sll [[T9]],[[T9]],0x1f
6418 ; MIPS32: sltu [[T9]],[[T9]],[[T4]]
6419 ; MIPS32: andi [[T9]],[[T9]],0xff
6420 ; MIPS32: sll [[T9]],[[T9]],0x10
6421 ; MIPS32: lui [[T4]],0xff00
6422 ; MIPS32: ori [[T4]],[[T4]],0xffff
6423 ; MIPS32: and [[T8]],[[T8]],[[T4]]
6424 ; MIPS32: or [[T9]],[[T9]],[[T8]]
6425 ; MIPS32: srl [[T10:.*]],a0,0x18
6426 ; MIPS32: andi [[T10]],[[T10]],0x1
6427 ; MIPS32: srl [[T0]],[[T0]],0x18
5786 ; MIPS32: andi [[T0]],[[T0]],0x1 6428 ; MIPS32: andi [[T0]],[[T0]],0x1
5787 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 6429 ; MIPS32: sll [[T10]],[[T10]],0x1f
5788 ; MIPS32: andi [[T1]],[[T1]],0x1
5789 ; MIPS32: sll [[T0]],[[T0]],0x1f 6430 ; MIPS32: sll [[T0]],[[T0]],0x1f
5790 ; MIPS32: sll [[T1]],[[T1]],0x1f 6431 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
5791 ; MIPS32: sltu [[T1]],[[T1]],[[T0]] 6432 ; MIPS32: srl [[T0]],[[T0]],0x18
5792 ; MIPS32: andi [[T1]],[[T1]],0xff 6433 ; MIPS32: sll [[T9]],[[T9]],0x8
5793 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 6434 ; MIPS32: srl [[T9]],[[T9]],0x8
5794 ; MIPS32: sll [[T2]],[[T2]],0x8 6435 ; MIPS32: or v0,[[T0]],[[T9]]
5795 ; MIPS32: or [[T1]],[[T1]],[[T2]] 6436 ; MIPS32: move [[T10]],a1
5796 ; MIPS32: srl [[T2]],a0,0x8 6437 ; MIPS32: andi [[T10]],[[T10]],0xff
5797 ; MIPS32: andi [[T2]],[[T2]],0xff 6438 ; MIPS32: andi [[T10]],[[T10]],0x1
5798 ; MIPS32: andi [[T2]],[[T2]],0x1 6439 ; MIPS32: move [[T4]],[[T1]]
5799 ; MIPS32: srl [[T0]],[[BV_E0]],0x8 6440 ; MIPS32: andi [[T4]],[[T4]],0xff
5800 ; MIPS32: andi [[T0]],[[T0]],0xff 6441 ; MIPS32: andi [[T4]],[[T4]],0x1
5801 ; MIPS32: andi [[T0]],[[T0]],0x1 6442 ; MIPS32: sll [[T10]],[[T10]],0x1f
5802 ; MIPS32: sll [[T2]],[[T2]],0x1f 6443 ; MIPS32: sll [[T4]],[[T4]],0x1f
5803 ; MIPS32: sll [[T0]],[[T0]],0x1f 6444 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
5804 ; MIPS32: sltu [[T0]],[[T0]],[[T2]] 6445 ; MIPS32: andi [[T4]],[[T4]],0xff
5805 ; MIPS32: andi [[T0]],[[T0]],0xff 6446 ; MIPS32: srl [[T5]],[[T5]],0x8
5806 ; MIPS32: sll [[T0]],[[T0]],0x8
5807 ; MIPS32: lui [[T2]],0xffff
5808 ; MIPS32: ori [[T2]],[[T2]],0xff
5809 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5810 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5811 ; MIPS32: srl [[T2]],a0,0x10
5812 ; MIPS32: andi [[T2]],[[T2]],0xff
5813 ; MIPS32: andi [[T2]],[[T2]],0x1
5814 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5815 ; MIPS32: andi [[T1]],[[T1]],0xff
5816 ; MIPS32: andi [[T1]],[[T1]],0x1
5817 ; MIPS32: sll [[T2]],[[T2]],0x1f
5818 ; MIPS32: sll [[T1]],[[T1]],0x1f
5819 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
5820 ; MIPS32: andi [[T1]],[[T1]],0xff
5821 ; MIPS32: sll [[T1]],[[T1]],0x10
5822 ; MIPS32: lui [[T2]],0xff00
5823 ; MIPS32: ori [[T2]],[[T2]],0xffff
5824 ; MIPS32: and [[T0]],[[T0]],[[T2]]
5825 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5826 ; MIPS32: srl [[T3:.*]],a0,0x18
5827 ; MIPS32: andi [[T3]],[[T3]],0x1
5828 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5829 ; MIPS32: andi [[T4]],[[T4]],0x1
5830 ; MIPS32: sll [[T3]],[[T3]],0x1f
5831 ; MIPS32: sll [[T4]],[[T4]],0x1f
5832 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
5833 ; MIPS32: srl [[T4]],[[T4]],0x18
5834 ; MIPS32: sll [[T1]],[[T1]],0x8
5835 ; MIPS32: srl [[T1]],[[T1]],0x8
5836 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
5837 ; MIPS32: andi [[T3]],a1,0xff
5838 ; MIPS32: andi [[T3]],[[T3]],0x1
5839 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5840 ; MIPS32: andi [[T2]],[[T2]],0x1
5841 ; MIPS32: sll [[T3]],[[T3]],0x1f
5842 ; MIPS32: sll [[T2]],[[T2]],0x1f
5843 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
5844 ; MIPS32: andi [[T2]],[[T2]],0xff
5845 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5846 ; MIPS32: sll [[T5]],[[T5]],0x8 6447 ; MIPS32: sll [[T5]],[[T5]],0x8
5847 ; MIPS32: or [[T2]],[[T2]],[[T5]] 6448 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5848 ; MIPS32: srl [[T3]],a1,0x8 6449 ; MIPS32: move [[T10]],a1
5849 ; MIPS32: andi [[T3]],[[T3]],0xff 6450 ; MIPS32: srl [[T10]],[[T10]],0x8
5850 ; MIPS32: andi [[T3]],[[T3]],0x1 6451 ; MIPS32: andi [[T10]],[[T10]],0xff
5851 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 6452 ; MIPS32: andi [[T10]],[[T10]],0x1
6453 ; MIPS32: move [[T5]],[[T1]]
6454 ; MIPS32: srl [[T5]],[[T5]],0x8
5852 ; MIPS32: andi [[T5]],[[T5]],0xff 6455 ; MIPS32: andi [[T5]],[[T5]],0xff
5853 ; MIPS32: andi [[T5]],[[T5]],0x1 6456 ; MIPS32: andi [[T5]],[[T5]],0x1
5854 ; MIPS32: sll [[T3]],[[T3]],0x1f 6457 ; MIPS32: sll [[T10]],[[T10]],0x1f
5855 ; MIPS32: sll [[T5]],[[T5]],0x1f 6458 ; MIPS32: sll [[T5]],[[T5]],0x1f
5856 ; MIPS32: sltu [[T5]],[[T5]],[[T3]] 6459 ; MIPS32: sltu [[T5]],[[T5]],[[T10]]
5857 ; MIPS32: andi [[T5]],[[T5]],0xff 6460 ; MIPS32: andi [[T5]],[[T5]],0xff
5858 ; MIPS32: sll [[T5]],[[T5]],0x8 6461 ; MIPS32: sll [[T5]],[[T5]],0x8
5859 ; MIPS32: lui [[T3]],0xffff 6462 ; MIPS32: lui [[T10]],0xffff
5860 ; MIPS32: ori [[T3]],[[T3]],0xff 6463 ; MIPS32: ori [[T10]],[[T10]],0xff
5861 ; MIPS32: and [[T2]],[[T2]],[[T3]] 6464 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5862 ; MIPS32: or [[T5]],[[T5]],[[T2]] 6465 ; MIPS32: or [[T5]],[[T5]],[[T4]]
5863 ; MIPS32: srl [[T3]],a1,0x10 6466 ; MIPS32: move [[T10]],a1
5864 ; MIPS32: andi [[T3]],[[T3]],0xff 6467 ; MIPS32: srl [[T10]],[[T10]],0x10
6468 ; MIPS32: andi [[T10]],[[T10]],0xff
6469 ; MIPS32: andi [[T10]],[[T10]],0x1
6470 ; MIPS32: move [[T4]],[[T1]]
6471 ; MIPS32: srl [[T4]],[[T4]],0x10
6472 ; MIPS32: andi [[T4]],[[T4]],0xff
6473 ; MIPS32: andi [[T4]],[[T4]],0x1
6474 ; MIPS32: sll [[T10]],[[T10]],0x1f
6475 ; MIPS32: sll [[T4]],[[T4]],0x1f
6476 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6477 ; MIPS32: andi [[T4]],[[T4]],0xff
6478 ; MIPS32: sll [[T4]],[[T4]],0x10
6479 ; MIPS32: lui [[T10]],0xff00
6480 ; MIPS32: ori [[T10]],[[T10]],0xffff
6481 ; MIPS32: and [[T5]],[[T5]],[[T10]]
6482 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6483 ; MIPS32: srl [[T11:.*]],a1,0x18
6484 ; MIPS32: andi [[T11]],[[T11]],0x1
6485 ; MIPS32: srl [[T1]],[[T1]],0x18
6486 ; MIPS32: andi [[T1]],[[T1]],0x1
6487 ; MIPS32: sll [[T11]],[[T11]],0x1f
6488 ; MIPS32: sll [[T1]],[[T1]],0x1f
6489 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
6490 ; MIPS32: srl [[T1]],[[T1]],0x18
6491 ; MIPS32: sll [[T4]],[[T4]],0x8
6492 ; MIPS32: srl [[T4]],[[T4]],0x8
6493 ; MIPS32: or v1,[[T1]],[[T4]]
6494 ; MIPS32: move [[T10]],a2
6495 ; MIPS32: andi [[T10]],[[T10]],0xff
6496 ; MIPS32: andi [[T10]],[[T10]],0x1
6497 ; MIPS32: move [[T11]],[[T2]]
6498 ; MIPS32: andi [[T11]],[[T11]],0xff
6499 ; MIPS32: andi [[T11]],[[T11]],0x1
6500 ; MIPS32: sll [[T10]],[[T10]],0x1f
6501 ; MIPS32: sll [[T11]],[[T11]],0x1f
6502 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6503 ; MIPS32: andi [[T11]],[[T11]],0xff
6504 ; MIPS32: srl [[T6]],[[T6]],0x8
6505 ; MIPS32: sll [[T6]],[[T6]],0x8
6506 ; MIPS32: or [[T11]],[[T11]],[[T6]]
6507 ; MIPS32: move [[T10]],a2
6508 ; MIPS32: srl [[T10]],[[T10]],0x8
6509 ; MIPS32: andi [[T10]],[[T10]],0xff
6510 ; MIPS32: andi [[T10]],[[T10]],0x1
6511 ; MIPS32: move [[T4]],[[T2]]
6512 ; MIPS32: srl [[T4]],[[T4]],0x8
6513 ; MIPS32: andi [[T4]],[[T4]],0xff
6514 ; MIPS32: andi [[T4]],[[T4]],0x1
6515 ; MIPS32: sll [[T10]],[[T10]],0x1f
6516 ; MIPS32: sll [[T4]],[[T4]],0x1f
6517 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6518 ; MIPS32: andi [[T4]],[[T4]],0xff
6519 ; MIPS32: sll [[T4]],[[T4]],0x8
6520 ; MIPS32: lui [[T10]],0xffff
6521 ; MIPS32: ori [[T10]],[[T10]],0xff
6522 ; MIPS32: and [[T11]],[[T11]],[[T10]]
6523 ; MIPS32: or [[T4]],[[T4]],[[T11]]
6524 ; MIPS32: move [[T10]],a2
6525 ; MIPS32: srl [[T10]],[[T10]],0x10
6526 ; MIPS32: andi [[T10]],[[T10]],0xff
6527 ; MIPS32: andi [[T10]],[[T10]],0x1
6528 ; MIPS32: move [[T11]],[[T2]]
6529 ; MIPS32: srl [[T11]],[[T11]],0x10
6530 ; MIPS32: andi [[T11]],[[T11]],0xff
6531 ; MIPS32: andi [[T11]],[[T11]],0x1
6532 ; MIPS32: sll [[T10]],[[T10]],0x1f
6533 ; MIPS32: sll [[T11]],[[T11]],0x1f
6534 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6535 ; MIPS32: andi [[T11]],[[T11]],0xff
6536 ; MIPS32: sll [[T11]],[[T11]],0x10
6537 ; MIPS32: lui [[T10]],0xff00
6538 ; MIPS32: ori [[T10]],[[T10]],0xffff
6539 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6540 ; MIPS32: or [[T11]],[[T11]],[[T4]]
6541 ; MIPS32: srl [[T12:.*]],a2,0x18
6542 ; MIPS32: andi [[T12]],[[T12]],0x1
6543 ; MIPS32: srl [[T2]],[[T2]],0x18
6544 ; MIPS32: andi [[T2]],[[T2]],0x1
6545 ; MIPS32: sll [[T12]],[[T12]],0x1f
6546 ; MIPS32: sll [[T2]],[[T2]],0x1f
6547 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
6548 ; MIPS32: srl [[T2]],[[T2]],0x18
6549 ; MIPS32: sll [[T11]],[[T11]],0x8
6550 ; MIPS32: srl [[T11]],[[T11]],0x8
6551 ; MIPS32: or [[T2]],[[T2]],[[T11]]
6552 ; MIPS32: move [[T10]],a3
6553 ; MIPS32: andi [[T10]],[[T10]],0xff
6554 ; MIPS32: andi [[T10]],[[T10]],0x1
6555 ; MIPS32: move [[T11]],[[T3]]
6556 ; MIPS32: andi [[T11]],[[T11]],0xff
6557 ; MIPS32: andi [[T11]],[[T11]],0x1
6558 ; MIPS32: sll [[T10]],[[T10]],0x1f
6559 ; MIPS32: sll [[T11]],[[T11]],0x1f
6560 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6561 ; MIPS32: andi [[T11]],[[T11]],0xff
6562 ; MIPS32: srl [[T7]],[[T7]],0x8
6563 ; MIPS32: sll [[T7]],[[T7]],0x8
6564 ; MIPS32: or [[T11]],[[T11]],[[T7]]
6565 ; MIPS32: move [[T10]],a3
6566 ; MIPS32: srl [[T10]],[[T10]],0x8
6567 ; MIPS32: andi [[T10]],[[T10]],0xff
6568 ; MIPS32: andi [[T10]],[[T10]],0x1
6569 ; MIPS32: move [[T12]],[[T3]]
6570 ; MIPS32: srl [[T12]],[[T12]],0x8
6571 ; MIPS32: andi [[T12]],[[T12]],0xff
6572 ; MIPS32: andi [[T12]],[[T12]],0x1
6573 ; MIPS32: sll [[T10]],[[T10]],0x1f
6574 ; MIPS32: sll [[T12]],[[T12]],0x1f
6575 ; MIPS32: sltu [[T12]],[[T12]],[[T10]]
6576 ; MIPS32: andi [[T12]],[[T12]],0xff
6577 ; MIPS32: sll [[T12]],[[T12]],0x8
6578 ; MIPS32: lui [[T10]],0xffff
6579 ; MIPS32: ori [[T10]],[[T10]],0xff
6580 ; MIPS32: and [[T11]],[[T11]],[[T10]]
6581 ; MIPS32: or [[T12]],[[T12]],[[T11]]
6582 ; MIPS32: move [[T10]],a3
6583 ; MIPS32: srl [[T10]],[[T10]],0x10
6584 ; MIPS32: andi [[T10]],[[T10]],0xff
6585 ; MIPS32: andi [[T10]],[[T10]],0x1
6586 ; MIPS32: move [[T11]],[[T3]]
6587 ; MIPS32: srl [[T11]],[[T11]],0x10
6588 ; MIPS32: andi [[T11]],[[T11]],0xff
6589 ; MIPS32: andi [[T11]],[[T11]],0x1
6590 ; MIPS32: sll [[T10]],[[T10]],0x1f
6591 ; MIPS32: sll [[T11]],[[T11]],0x1f
6592 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6593 ; MIPS32: andi [[T11]],[[T11]],0xff
6594 ; MIPS32: sll [[T11]],[[T11]],0x10
6595 ; MIPS32: lui [[T10]],0xff00
6596 ; MIPS32: ori [[T10]],[[T10]],0xffff
6597 ; MIPS32: and [[T12]],[[T12]],[[T10]]
6598 ; MIPS32: or [[T11]],[[T11]],[[T12]]
6599 ; MIPS32: srl [[T13:.*]],a3,0x18
6600 ; MIPS32: andi [[T13]],[[T13]],0x1
6601 ; MIPS32: srl [[T3]],[[T3]],0x18
5865 ; MIPS32: andi [[T3]],[[T3]],0x1 6602 ; MIPS32: andi [[T3]],[[T3]],0x1
5866 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 6603 ; MIPS32: sll [[T13]],[[T13]],0x1f
5867 ; MIPS32: andi [[T2]],[[T2]],0xff
5868 ; MIPS32: andi [[T2]],[[T2]],0x1
5869 ; MIPS32: sll [[T3]],[[T3]],0x1f 6604 ; MIPS32: sll [[T3]],[[T3]],0x1f
5870 ; MIPS32: sll [[T2]],[[T2]],0x1f 6605 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
5871 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 6606 ; MIPS32: srl [[T3]],[[T3]],0x18
5872 ; MIPS32: andi [[T2]],[[T2]],0xff
5873 ; MIPS32: sll [[T2]],[[T2]],0x10
5874 ; MIPS32: lui [[T3]],0xff00
5875 ; MIPS32: ori [[T3]],[[T3]],0xffff
5876 ; MIPS32: and [[T5]],[[T5]],[[T3]]
5877 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5878 ; MIPS32: srl [[T6:.*]],a1,0x18
5879 ; MIPS32: andi [[T6]],[[T6]],0x1
5880 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5881 ; MIPS32: andi [[T7]],[[T7]],0x1
5882 ; MIPS32: sll [[T6]],[[T6]],0x1f
5883 ; MIPS32: sll [[T7]],[[T7]],0x1f
5884 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
5885 ; MIPS32: srl [[T7]],[[T7]],0x18
5886 ; MIPS32: sll [[T2]],[[T2]],0x8
5887 ; MIPS32: srl [[T2]],[[T2]],0x8
5888 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
5889 ; MIPS32: andi [[T3]],a2,0xff
5890 ; MIPS32: andi [[T3]],[[T3]],0x1
5891 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
5892 ; MIPS32: andi [[T6]],[[T6]],0x1
5893 ; MIPS32: sll [[T3]],[[T3]],0x1f
5894 ; MIPS32: sll [[T6]],[[T6]],0x1f
5895 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5896 ; MIPS32: andi [[T6]],[[T6]],0xff
5897 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5898 ; MIPS32: sll [[T8]],[[T8]],0x8
5899 ; MIPS32: or [[T6]],[[T6]],[[T8]]
5900 ; MIPS32: srl [[T3]],a2,0x8
5901 ; MIPS32: andi [[T3]],[[T3]],0xff
5902 ; MIPS32: andi [[T3]],[[T3]],0x1
5903 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5904 ; MIPS32: andi [[T2]],[[T2]],0xff
5905 ; MIPS32: andi [[T2]],[[T2]],0x1
5906 ; MIPS32: sll [[T3]],[[T3]],0x1f
5907 ; MIPS32: sll [[T2]],[[T2]],0x1f
5908 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
5909 ; MIPS32: andi [[T2]],[[T2]],0xff
5910 ; MIPS32: sll [[T2]],[[T2]],0x8
5911 ; MIPS32: lui [[T3]],0xffff
5912 ; MIPS32: ori [[T3]],[[T3]],0xff
5913 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5914 ; MIPS32: or [[T2]],[[T2]],[[T6]]
5915 ; MIPS32: srl [[T3]],a2,0x10
5916 ; MIPS32: andi [[T3]],[[T3]],0xff
5917 ; MIPS32: andi [[T3]],[[T3]],0x1
5918 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
5919 ; MIPS32: andi [[T6]],[[T6]],0xff
5920 ; MIPS32: andi [[T6]],[[T6]],0x1
5921 ; MIPS32: sll [[T3]],[[T3]],0x1f
5922 ; MIPS32: sll [[T6]],[[T6]],0x1f
5923 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5924 ; MIPS32: andi [[T6]],[[T6]],0xff
5925 ; MIPS32: sll [[T6]],[[T6]],0x10
5926 ; MIPS32: lui [[T3]],0xff00
5927 ; MIPS32: ori [[T3]],[[T3]],0xffff
5928 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5929 ; MIPS32: or [[T6]],[[T6]],[[T2]]
5930 ; MIPS32: srl [[T9:.*]],a2,0x18
5931 ; MIPS32: andi [[T9]],[[T9]],0x1
5932 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5933 ; MIPS32: andi [[T10]],[[T10]],0x1
5934 ; MIPS32: sll [[T9]],[[T9]],0x1f
5935 ; MIPS32: sll [[T10]],[[T10]],0x1f
5936 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
5937 ; MIPS32: srl [[T10]],[[T10]],0x18
5938 ; MIPS32: sll [[T6]],[[T6]],0x8
5939 ; MIPS32: srl [[T6]],[[T6]],0x8
5940 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5941 ; MIPS32: andi [[T3]],a3,0xff
5942 ; MIPS32: andi [[T3]],[[T3]],0x1
5943 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5944 ; MIPS32: andi [[T6]],[[T6]],0x1
5945 ; MIPS32: sll [[T3]],[[T3]],0x1f
5946 ; MIPS32: sll [[T6]],[[T6]],0x1f
5947 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5948 ; MIPS32: andi [[T6]],[[T6]],0xff
5949 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5950 ; MIPS32: sll [[T11]],[[T11]],0x8 6607 ; MIPS32: sll [[T11]],[[T11]],0x8
5951 ; MIPS32: or [[T6]],[[T6]],[[T11]] 6608 ; MIPS32: srl [[T11]],[[T11]],0x8
5952 ; MIPS32: srl [[T3]],a3,0x8 6609 ; MIPS32: or [[T3]],[[T3]],[[T11]]
5953 ; MIPS32: andi [[T3]],[[T3]],0xff 6610 ; MIPS32: move a0,[[T2]]
5954 ; MIPS32: andi [[T3]],[[T3]],0x1 6611 ; MIPS32: move a1,[[T3]]
5955 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5956 ; MIPS32: andi [[T9]],[[T9]],0xff
5957 ; MIPS32: andi [[T9]],[[T9]],0x1
5958 ; MIPS32: sll [[T3]],[[T3]],0x1f
5959 ; MIPS32: sll [[T9]],[[T9]],0x1f
5960 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
5961 ; MIPS32: andi [[T9]],[[T9]],0xff
5962 ; MIPS32: sll [[T9]],[[T9]],0x8
5963 ; MIPS32: lui [[T3]],0xffff
5964 ; MIPS32: ori [[T3]],[[T3]],0xff
5965 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5966 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5967 ; MIPS32: srl [[T3]],a3,0x10
5968 ; MIPS32: andi [[T3]],[[T3]],0xff
5969 ; MIPS32: andi [[T3]],[[T3]],0x1
5970 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5971 ; MIPS32: andi [[T6]],[[T6]],0xff
5972 ; MIPS32: andi [[T6]],[[T6]],0x1
5973 ; MIPS32: sll [[T3]],[[T3]],0x1f
5974 ; MIPS32: sll [[T6]],[[T6]],0x1f
5975 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5976 ; MIPS32: andi [[T6]],[[T6]],0xff
5977 ; MIPS32: sll [[T6]],[[T6]],0x10
5978 ; MIPS32: lui [[T3]],0xff00
5979 ; MIPS32: ori [[T3]],[[T3]],0xffff
5980 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5981 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5982 ; MIPS32: srl [[T12:.*]],a3,0x18
5983 ; MIPS32: andi [[T12]],[[T12]],0x1
5984 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5985 ; MIPS32: andi [[T13]],[[T13]],0x1
5986 ; MIPS32: sll [[T12]],[[T12]],0x1f
5987 ; MIPS32: sll [[T13]],[[T13]],0x1f
5988 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
5989 ; MIPS32: srl [[T13]],[[T13]],0x18
5990 ; MIPS32: sll [[T6]],[[T6]],0x8
5991 ; MIPS32: srl [[T6]],[[T6]],0x8
5992 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
5993 } 6612 }
5994 6613
5995 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) { 6614 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) {
5996 entry: 6615 entry:
5997 %res = icmp ule <16 x i1> %a, %b 6616 %res = icmp ule <16 x i1> %a, %b
5998 ret <16 x i1> %res 6617 ret <16 x i1> %res
5999 ; CHECK-LABEL: test_icmp_v16i1_ule 6618 ; CHECK-LABEL: test_icmp_v16i1_ule
6000 ; CHECK: pxor 6619 ; CHECK: pxor
6001 ; CHECK: pcmpgtb 6620 ; CHECK: pcmpgtb
6002 ; CHECK: pxor 6621 ; CHECK: pxor
6003 6622
6004 ; MIPS32-LABEL: test_icmp_v16i1_ule 6623 ; MIPS32-LABEL: test_icmp_v16i1_ule
6005 ; MIPS32: lw [[BV_E0:.*]], 6624 ; MIPS32: lw [[T0:.*]],
6006 ; MIPS32: lw [[BV_E1:.*]], 6625 ; MIPS32: lw [[T1:.*]],
6007 ; MIPS32: lw [[BV_E2:.*]], 6626 ; MIPS32: lw [[T2:.*]],
6008 ; MIPS32: lw [[BV_E3:.*]], 6627 ; MIPS32: lw [[T3:.*]],
6009 ; MIPS32: move [[TV_E0:.*]],zero 6628 ; MIPS32: move [[T4:.*]],zero
6010 ; MIPS32: move [[TV_E1:.*]],zero 6629 ; MIPS32: move [[T5:.*]],zero
6011 ; MIPS32: move [[TV_E2:.*]],zero 6630 ; MIPS32: move [[T6:.*]],zero
6012 ; MIPS32: move [[TV_E3:.*]],zero 6631 ; MIPS32: move [[T7:.*]],zero
6013 ; MIPS32: andi [[T0:.*]],a0,0xff 6632 ; MIPS32: move [[T8:.*]],a0
6633 ; MIPS32: andi [[T8]],[[T8]],0xff
6634 ; MIPS32: andi [[T8]],[[T8]],0x1
6635 ; MIPS32: move [[T9:.*]],[[T0]]
6636 ; MIPS32: andi [[T9]],[[T9]],0xff
6637 ; MIPS32: andi [[T9]],[[T9]],0x1
6638 ; MIPS32: sll [[T8]],[[T8]],0x1f
6639 ; MIPS32: sll [[T9]],[[T9]],0x1f
6640 ; MIPS32: sltu [[T9]],[[T9]],[[T8]]
6641 ; MIPS32: xori [[T9]],[[T9]],0x1
6642 ; MIPS32: andi [[T9]],[[T9]],0xff
6643 ; MIPS32: srl [[T4]],[[T4]],0x8
6644 ; MIPS32: sll [[T4]],[[T4]],0x8
6645 ; MIPS32: or [[T9]],[[T9]],[[T4]]
6646 ; MIPS32: move [[T4]],a0
6647 ; MIPS32: srl [[T4]],[[T4]],0x8
6648 ; MIPS32: andi [[T4]],[[T4]],0xff
6649 ; MIPS32: andi [[T4]],[[T4]],0x1
6650 ; MIPS32: move [[T8]],[[T0]]
6651 ; MIPS32: srl [[T8]],[[T8]],0x8
6652 ; MIPS32: andi [[T8]],[[T8]],0xff
6653 ; MIPS32: andi [[T8]],[[T8]],0x1
6654 ; MIPS32: sll [[T4]],[[T4]],0x1f
6655 ; MIPS32: sll [[T8]],[[T8]],0x1f
6656 ; MIPS32: sltu [[T8]],[[T8]],[[T4]]
6657 ; MIPS32: xori [[T8]],[[T8]],0x1
6658 ; MIPS32: andi [[T8]],[[T8]],0xff
6659 ; MIPS32: sll [[T8]],[[T8]],0x8
6660 ; MIPS32: lui [[T4]],0xffff
6661 ; MIPS32: ori [[T4]],[[T4]],0xff
6662 ; MIPS32: and [[T9]],[[T9]],[[T4]]
6663 ; MIPS32: or [[T8]],[[T8]],[[T9]]
6664 ; MIPS32: move [[T4]],a0
6665 ; MIPS32: srl [[T4]],[[T4]],0x10
6666 ; MIPS32: andi [[T4]],[[T4]],0xff
6667 ; MIPS32: andi [[T4]],[[T4]],0x1
6668 ; MIPS32: move [[T9]],[[T0]]
6669 ; MIPS32: srl [[T9]],[[T9]],0x10
6670 ; MIPS32: andi [[T9]],[[T9]],0xff
6671 ; MIPS32: andi [[T9]],[[T9]],0x1
6672 ; MIPS32: sll [[T4]],[[T4]],0x1f
6673 ; MIPS32: sll [[T9]],[[T9]],0x1f
6674 ; MIPS32: sltu [[T9]],[[T9]],[[T4]]
6675 ; MIPS32: xori [[T9]],[[T9]],0x1
6676 ; MIPS32: andi [[T9]],[[T9]],0xff
6677 ; MIPS32: sll [[T9]],[[T9]],0x10
6678 ; MIPS32: lui [[T4]],0xff00
6679 ; MIPS32: ori [[T4]],[[T4]],0xffff
6680 ; MIPS32: and [[T8]],[[T8]],[[T4]]
6681 ; MIPS32: or [[T9]],[[T9]],[[T8]]
6682 ; MIPS32: srl [[T10:.*]],a0,0x18
6683 ; MIPS32: andi [[T10]],[[T10]],0x1
6684 ; MIPS32: srl [[T0]],[[T0]],0x18
6014 ; MIPS32: andi [[T0]],[[T0]],0x1 6685 ; MIPS32: andi [[T0]],[[T0]],0x1
6015 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 6686 ; MIPS32: sll [[T10]],[[T10]],0x1f
6016 ; MIPS32: andi [[T1]],[[T1]],0x1
6017 ; MIPS32: sll [[T0]],[[T0]],0x1f 6687 ; MIPS32: sll [[T0]],[[T0]],0x1f
6018 ; MIPS32: sll [[T1]],[[T1]],0x1f 6688 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
6019 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
6020 ; MIPS32: xori [[T1]],[[T1]],0x1
6021 ; MIPS32: andi [[T1]],[[T1]],0xff
6022 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
6023 ; MIPS32: sll [[T2]],[[T2]],0x8
6024 ; MIPS32: or [[T1]],[[T1]],[[T2]]
6025 ; MIPS32: srl [[T2]],a0,0x8
6026 ; MIPS32: andi [[T2]],[[T2]],0xff
6027 ; MIPS32: andi [[T2]],[[T2]],0x1
6028 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
6029 ; MIPS32: andi [[T0]],[[T0]],0xff
6030 ; MIPS32: andi [[T0]],[[T0]],0x1
6031 ; MIPS32: sll [[T2]],[[T2]],0x1f
6032 ; MIPS32: sll [[T0]],[[T0]],0x1f
6033 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
6034 ; MIPS32: xori [[T0]],[[T0]],0x1 6689 ; MIPS32: xori [[T0]],[[T0]],0x1
6035 ; MIPS32: andi [[T0]],[[T0]],0xff 6690 ; MIPS32: srl [[T0]],[[T0]],0x18
6036 ; MIPS32: sll [[T0]],[[T0]],0x8 6691 ; MIPS32: sll [[T9]],[[T9]],0x8
6037 ; MIPS32: lui [[T2]],0xffff 6692 ; MIPS32: srl [[T9]],[[T9]],0x8
6038 ; MIPS32: ori [[T2]],[[T2]],0xff 6693 ; MIPS32: or v0,[[T0]],[[T9]]
6039 ; MIPS32: and [[T1]],[[T1]],[[T2]] 6694 ; MIPS32: move [[T10]],a1
6040 ; MIPS32: or [[T0]],[[T0]],[[T1]] 6695 ; MIPS32: andi [[T10]],[[T10]],0xff
6041 ; MIPS32: srl [[T2]],a0,0x10 6696 ; MIPS32: andi [[T10]],[[T10]],0x1
6042 ; MIPS32: andi [[T2]],[[T2]],0xff 6697 ; MIPS32: move [[T4]],[[T1]]
6043 ; MIPS32: andi [[T2]],[[T2]],0x1 6698 ; MIPS32: andi [[T4]],[[T4]],0xff
6044 ; MIPS32: srl [[T1]],[[BV_E0]],0x10 6699 ; MIPS32: andi [[T4]],[[T4]],0x1
6045 ; MIPS32: andi [[T1]],[[T1]],0xff 6700 ; MIPS32: sll [[T10]],[[T10]],0x1f
6046 ; MIPS32: andi [[T1]],[[T1]],0x1 6701 ; MIPS32: sll [[T4]],[[T4]],0x1f
6047 ; MIPS32: sll [[T2]],[[T2]],0x1f 6702 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6048 ; MIPS32: sll [[T1]],[[T1]],0x1f
6049 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
6050 ; MIPS32: xori [[T1]],[[T1]],0x1
6051 ; MIPS32: andi [[T1]],[[T1]],0xff
6052 ; MIPS32: sll [[T1]],[[T1]],0x10
6053 ; MIPS32: lui [[T2]],0xff00
6054 ; MIPS32: ori [[T2]],[[T2]],0xffff
6055 ; MIPS32: and [[T0]],[[T0]],[[T2]]
6056 ; MIPS32: or [[T1]],[[T1]],[[T0]]
6057 ; MIPS32: srl [[T3:.*]],a0,0x18
6058 ; MIPS32: andi [[T3]],[[T3]],0x1
6059 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
6060 ; MIPS32: andi [[T4]],[[T4]],0x1
6061 ; MIPS32: sll [[T3]],[[T3]],0x1f
6062 ; MIPS32: sll [[T4]],[[T4]],0x1f
6063 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
6064 ; MIPS32: xori [[T4]],[[T4]],0x1 6703 ; MIPS32: xori [[T4]],[[T4]],0x1
6065 ; MIPS32: srl [[T4]],[[T4]],0x18 6704 ; MIPS32: andi [[T4]],[[T4]],0xff
6066 ; MIPS32: sll [[T1]],[[T1]],0x8 6705 ; MIPS32: srl [[T5]],[[T5]],0x8
6067 ; MIPS32: srl [[T1]],[[T1]],0x8
6068 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
6069 ; MIPS32: andi [[T3]],a1,0xff
6070 ; MIPS32: andi [[T3]],[[T3]],0x1
6071 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
6072 ; MIPS32: andi [[T2]],[[T2]],0x1
6073 ; MIPS32: sll [[T3]],[[T3]],0x1f
6074 ; MIPS32: sll [[T2]],[[T2]],0x1f
6075 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
6076 ; MIPS32: xori [[T2]],[[T2]],0x1
6077 ; MIPS32: andi [[T2]],[[T2]],0xff
6078 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
6079 ; MIPS32: sll [[T5]],[[T5]],0x8 6706 ; MIPS32: sll [[T5]],[[T5]],0x8
6080 ; MIPS32: or [[T2]],[[T2]],[[T5]] 6707 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6081 ; MIPS32: srl [[T3]],a1,0x8 6708 ; MIPS32: move [[T10]],a1
6082 ; MIPS32: andi [[T3]],[[T3]],0xff 6709 ; MIPS32: srl [[T10]],[[T10]],0x8
6083 ; MIPS32: andi [[T3]],[[T3]],0x1 6710 ; MIPS32: andi [[T10]],[[T10]],0xff
6084 ; MIPS32: srl [[T5]],[[BV_E1]],0x8 6711 ; MIPS32: andi [[T10]],[[T10]],0x1
6712 ; MIPS32: move [[T5]],[[T1]]
6713 ; MIPS32: srl [[T5]],[[T5]],0x8
6085 ; MIPS32: andi [[T5]],[[T5]],0xff 6714 ; MIPS32: andi [[T5]],[[T5]],0xff
6086 ; MIPS32: andi [[T5]],[[T5]],0x1 6715 ; MIPS32: andi [[T5]],[[T5]],0x1
6087 ; MIPS32: sll [[T3]],[[T3]],0x1f 6716 ; MIPS32: sll [[T10]],[[T10]],0x1f
6088 ; MIPS32: sll [[T5]],[[T5]],0x1f 6717 ; MIPS32: sll [[T5]],[[T5]],0x1f
6089 ; MIPS32: sltu [[T5]],[[T5]],[[T3]] 6718 ; MIPS32: sltu [[T5]],[[T5]],[[T10]]
6090 ; MIPS32: xori [[T5]],[[T5]],0x1 6719 ; MIPS32: xori [[T5]],[[T5]],0x1
6091 ; MIPS32: andi [[T5]],[[T5]],0xff 6720 ; MIPS32: andi [[T5]],[[T5]],0xff
6092 ; MIPS32: sll [[T5]],[[T5]],0x8 6721 ; MIPS32: sll [[T5]],[[T5]],0x8
6093 ; MIPS32: lui [[T3]],0xffff 6722 ; MIPS32: lui [[T10]],0xffff
6094 ; MIPS32: ori [[T3]],[[T3]],0xff 6723 ; MIPS32: ori [[T10]],[[T10]],0xff
6095 ; MIPS32: and [[T2]],[[T2]],[[T3]] 6724 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6096 ; MIPS32: or [[T5]],[[T5]],[[T2]] 6725 ; MIPS32: or [[T5]],[[T5]],[[T4]]
6097 ; MIPS32: srl [[T3]],a1,0x10 6726 ; MIPS32: move [[T10]],a1
6098 ; MIPS32: andi [[T3]],[[T3]],0xff 6727 ; MIPS32: srl [[T10]],[[T10]],0x10
6728 ; MIPS32: andi [[T10]],[[T10]],0xff
6729 ; MIPS32: andi [[T10]],[[T10]],0x1
6730 ; MIPS32: move [[T4]],[[T1]]
6731 ; MIPS32: srl [[T4]],[[T4]],0x10
6732 ; MIPS32: andi [[T4]],[[T4]],0xff
6733 ; MIPS32: andi [[T4]],[[T4]],0x1
6734 ; MIPS32: sll [[T10]],[[T10]],0x1f
6735 ; MIPS32: sll [[T4]],[[T4]],0x1f
6736 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6737 ; MIPS32: xori [[T4]],[[T4]],0x1
6738 ; MIPS32: andi [[T4]],[[T4]],0xff
6739 ; MIPS32: sll [[T4]],[[T4]],0x10
6740 ; MIPS32: lui [[T10]],0xff00
6741 ; MIPS32: ori [[T10]],[[T10]],0xffff
6742 ; MIPS32: and [[T5]],[[T5]],[[T10]]
6743 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6744 ; MIPS32: srl [[T11:.*]],a1,0x18
6745 ; MIPS32: andi [[T11]],[[T11]],0x1
6746 ; MIPS32: srl [[T1]],[[T1]],0x18
6747 ; MIPS32: andi [[T1]],[[T1]],0x1
6748 ; MIPS32: sll [[T11]],[[T11]],0x1f
6749 ; MIPS32: sll [[T1]],[[T1]],0x1f
6750 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
6751 ; MIPS32: xori [[T1]],[[T1]],0x1
6752 ; MIPS32: srl [[T1]],[[T1]],0x18
6753 ; MIPS32: sll [[T4]],[[T4]],0x8
6754 ; MIPS32: srl [[T4]],[[T4]],0x8
6755 ; MIPS32: or v1,[[T1]],[[T4]]
6756 ; MIPS32: move [[T10]],a2
6757 ; MIPS32: andi [[T10]],[[T10]],0xff
6758 ; MIPS32: andi [[T10]],[[T10]],0x1
6759 ; MIPS32: move [[T11]],[[T2]]
6760 ; MIPS32: andi [[T11]],[[T11]],0xff
6761 ; MIPS32: andi [[T11]],[[T11]],0x1
6762 ; MIPS32: sll [[T10]],[[T10]],0x1f
6763 ; MIPS32: sll [[T11]],[[T11]],0x1f
6764 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6765 ; MIPS32: xori [[T11]],[[T11]],0x1
6766 ; MIPS32: andi [[T11]],[[T11]],0xff
6767 ; MIPS32: srl [[T6]],[[T6]],0x8
6768 ; MIPS32: sll [[T6]],[[T6]],0x8
6769 ; MIPS32: or [[T11]],[[T11]],[[T6]]
6770 ; MIPS32: move [[T10]],a2
6771 ; MIPS32: srl [[T10]],[[T10]],0x8
6772 ; MIPS32: andi [[T10]],[[T10]],0xff
6773 ; MIPS32: andi [[T10]],[[T10]],0x1
6774 ; MIPS32: move [[T4]],[[T2]]
6775 ; MIPS32: srl [[T4]],[[T4]],0x8
6776 ; MIPS32: andi [[T4]],[[T4]],0xff
6777 ; MIPS32: andi [[T4]],[[T4]],0x1
6778 ; MIPS32: sll [[T10]],[[T10]],0x1f
6779 ; MIPS32: sll [[T4]],[[T4]],0x1f
6780 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6781 ; MIPS32: xori [[T4]],[[T4]],0x1
6782 ; MIPS32: andi [[T4]],[[T4]],0xff
6783 ; MIPS32: sll [[T4]],[[T4]],0x8
6784 ; MIPS32: lui [[T10]],0xffff
6785 ; MIPS32: ori [[T10]],[[T10]],0xff
6786 ; MIPS32: and [[T11]],[[T11]],[[T10]]
6787 ; MIPS32: or [[T4]],[[T4]],[[T11]]
6788 ; MIPS32: move [[T10]],a2
6789 ; MIPS32: srl [[T10]],[[T10]],0x10
6790 ; MIPS32: andi [[T10]],[[T10]],0xff
6791 ; MIPS32: andi [[T10]],[[T10]],0x1
6792 ; MIPS32: move [[T11]],[[T2]]
6793 ; MIPS32: srl [[T11]],[[T11]],0x10
6794 ; MIPS32: andi [[T11]],[[T11]],0xff
6795 ; MIPS32: andi [[T11]],[[T11]],0x1
6796 ; MIPS32: sll [[T10]],[[T10]],0x1f
6797 ; MIPS32: sll [[T11]],[[T11]],0x1f
6798 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6799 ; MIPS32: xori [[T11]],[[T11]],0x1
6800 ; MIPS32: andi [[T11]],[[T11]],0xff
6801 ; MIPS32: sll [[T11]],[[T11]],0x10
6802 ; MIPS32: lui [[T10]],0xff00
6803 ; MIPS32: ori [[T10]],[[T10]],0xffff
6804 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6805 ; MIPS32: or [[T11]],[[T11]],[[T4]]
6806 ; MIPS32: srl [[T12:.*]],a2,0x18
6807 ; MIPS32: andi [[T12]],[[T12]],0x1
6808 ; MIPS32: srl [[T2]],[[T2]],0x18
6809 ; MIPS32: andi [[T2]],[[T2]],0x1
6810 ; MIPS32: sll [[T12]],[[T12]],0x1f
6811 ; MIPS32: sll [[T2]],[[T2]],0x1f
6812 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
6813 ; MIPS32: xori [[T2]],[[T2]],0x1
6814 ; MIPS32: srl [[T2]],[[T2]],0x18
6815 ; MIPS32: sll [[T11]],[[T11]],0x8
6816 ; MIPS32: srl [[T11]],[[T11]],0x8
6817 ; MIPS32: or [[T2]],[[T2]],[[T11]]
6818 ; MIPS32: move [[T10]],a3
6819 ; MIPS32: andi [[T10]],[[T10]],0xff
6820 ; MIPS32: andi [[T10]],[[T10]],0x1
6821 ; MIPS32: move [[T11]],[[T3]]
6822 ; MIPS32: andi [[T11]],[[T11]],0xff
6823 ; MIPS32: andi [[T11]],[[T11]],0x1
6824 ; MIPS32: sll [[T10]],[[T10]],0x1f
6825 ; MIPS32: sll [[T11]],[[T11]],0x1f
6826 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6827 ; MIPS32: xori [[T11]],[[T11]],0x1
6828 ; MIPS32: andi [[T11]],[[T11]],0xff
6829 ; MIPS32: srl [[T7]],[[T7]],0x8
6830 ; MIPS32: sll [[T7]],[[T7]],0x8
6831 ; MIPS32: or [[T11]],[[T11]],[[T7]]
6832 ; MIPS32: move [[T10]],a3
6833 ; MIPS32: srl [[T10]],[[T10]],0x8
6834 ; MIPS32: andi [[T10]],[[T10]],0xff
6835 ; MIPS32: andi [[T10]],[[T10]],0x1
6836 ; MIPS32: move [[T12]],[[T3]]
6837 ; MIPS32: srl [[T12]],[[T12]],0x8
6838 ; MIPS32: andi [[T12]],[[T12]],0xff
6839 ; MIPS32: andi [[T12]],[[T12]],0x1
6840 ; MIPS32: sll [[T10]],[[T10]],0x1f
6841 ; MIPS32: sll [[T12]],[[T12]],0x1f
6842 ; MIPS32: sltu [[T12]],[[T12]],[[T10]]
6843 ; MIPS32: xori [[T12]],[[T12]],0x1
6844 ; MIPS32: andi [[T12]],[[T12]],0xff
6845 ; MIPS32: sll [[T12]],[[T12]],0x8
6846 ; MIPS32: lui [[T10]],0xffff
6847 ; MIPS32: ori [[T10]],[[T10]],0xff
6848 ; MIPS32: and [[T11]],[[T11]],[[T10]]
6849 ; MIPS32: or [[T12]],[[T12]],[[T11]]
6850 ; MIPS32: move [[T10]],a3
6851 ; MIPS32: srl [[T10]],[[T10]],0x10
6852 ; MIPS32: andi [[T10]],[[T10]],0xff
6853 ; MIPS32: andi [[T10]],[[T10]],0x1
6854 ; MIPS32: move [[T11]],[[T3]]
6855 ; MIPS32: srl [[T11]],[[T11]],0x10
6856 ; MIPS32: andi [[T11]],[[T11]],0xff
6857 ; MIPS32: andi [[T11]],[[T11]],0x1
6858 ; MIPS32: sll [[T10]],[[T10]],0x1f
6859 ; MIPS32: sll [[T11]],[[T11]],0x1f
6860 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
6861 ; MIPS32: xori [[T11]],[[T11]],0x1
6862 ; MIPS32: andi [[T11]],[[T11]],0xff
6863 ; MIPS32: sll [[T11]],[[T11]],0x10
6864 ; MIPS32: lui [[T10]],0xff00
6865 ; MIPS32: ori [[T10]],[[T10]],0xffff
6866 ; MIPS32: and [[T12]],[[T12]],[[T10]]
6867 ; MIPS32: or [[T11]],[[T11]],[[T12]]
6868 ; MIPS32: srl [[T13:.*]],a3,0x18
6869 ; MIPS32: andi [[T13]],[[T13]],0x1
6870 ; MIPS32: srl [[T3]],[[T3]],0x18
6099 ; MIPS32: andi [[T3]],[[T3]],0x1 6871 ; MIPS32: andi [[T3]],[[T3]],0x1
6100 ; MIPS32: srl [[T2]],[[BV_E1]],0x10 6872 ; MIPS32: sll [[T13]],[[T13]],0x1f
6101 ; MIPS32: andi [[T2]],[[T2]],0xff
6102 ; MIPS32: andi [[T2]],[[T2]],0x1
6103 ; MIPS32: sll [[T3]],[[T3]],0x1f 6873 ; MIPS32: sll [[T3]],[[T3]],0x1f
6104 ; MIPS32: sll [[T2]],[[T2]],0x1f 6874 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
6105 ; MIPS32: sltu [[T2]],[[T2]],[[T3]] 6875 ; MIPS32: xori [[T3]],[[T3]],0x1
6106 ; MIPS32: xori [[T2]],[[T2]],0x1 6876 ; MIPS32: srl [[T3]],[[T3]],0x18
6107 ; MIPS32: andi [[T2]],[[T2]],0xff
6108 ; MIPS32: sll [[T2]],[[T2]],0x10
6109 ; MIPS32: lui [[T3]],0xff00
6110 ; MIPS32: ori [[T3]],[[T3]],0xffff
6111 ; MIPS32: and [[T5]],[[T5]],[[T3]]
6112 ; MIPS32: or [[T2]],[[T2]],[[T5]]
6113 ; MIPS32: srl [[T6:.*]],a1,0x18
6114 ; MIPS32: andi [[T6]],[[T6]],0x1
6115 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
6116 ; MIPS32: andi [[T7]],[[T7]],0x1
6117 ; MIPS32: sll [[T6]],[[T6]],0x1f
6118 ; MIPS32: sll [[T7]],[[T7]],0x1f
6119 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
6120 ; MIPS32: xori [[T7]],[[T7]],0x1
6121 ; MIPS32: srl [[T7]],[[T7]],0x18
6122 ; MIPS32: sll [[T2]],[[T2]],0x8
6123 ; MIPS32: srl [[T2]],[[T2]],0x8
6124 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
6125 ; MIPS32: andi [[T3]],a2,0xff
6126 ; MIPS32: andi [[T3]],[[T3]],0x1
6127 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
6128 ; MIPS32: andi [[T6]],[[T6]],0x1
6129 ; MIPS32: sll [[T3]],[[T3]],0x1f
6130 ; MIPS32: sll [[T6]],[[T6]],0x1f
6131 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6132 ; MIPS32: xori [[T6]],[[T6]],0x1
6133 ; MIPS32: andi [[T6]],[[T6]],0xff
6134 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
6135 ; MIPS32: sll [[T8]],[[T8]],0x8
6136 ; MIPS32: or [[T6]],[[T6]],[[T8]]
6137 ; MIPS32: srl [[T3]],a2,0x8
6138 ; MIPS32: andi [[T3]],[[T3]],0xff
6139 ; MIPS32: andi [[T3]],[[T3]],0x1
6140 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
6141 ; MIPS32: andi [[T2]],[[T2]],0xff
6142 ; MIPS32: andi [[T2]],[[T2]],0x1
6143 ; MIPS32: sll [[T3]],[[T3]],0x1f
6144 ; MIPS32: sll [[T2]],[[T2]],0x1f
6145 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
6146 ; MIPS32: xori [[T2]],[[T2]],0x1
6147 ; MIPS32: andi [[T2]],[[T2]],0xff
6148 ; MIPS32: sll [[T2]],[[T2]],0x8
6149 ; MIPS32: lui [[T3]],0xffff
6150 ; MIPS32: ori [[T3]],[[T3]],0xff
6151 ; MIPS32: and [[T6]],[[T6]],[[T3]]
6152 ; MIPS32: or [[T2]],[[T2]],[[T6]]
6153 ; MIPS32: srl [[T3]],a2,0x10
6154 ; MIPS32: andi [[T3]],[[T3]],0xff
6155 ; MIPS32: andi [[T3]],[[T3]],0x1
6156 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
6157 ; MIPS32: andi [[T6]],[[T6]],0xff
6158 ; MIPS32: andi [[T6]],[[T6]],0x1
6159 ; MIPS32: sll [[T3]],[[T3]],0x1f
6160 ; MIPS32: sll [[T6]],[[T6]],0x1f
6161 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6162 ; MIPS32: xori [[T6]],[[T6]],0x1
6163 ; MIPS32: andi [[T6]],[[T6]],0xff
6164 ; MIPS32: sll [[T6]],[[T6]],0x10
6165 ; MIPS32: lui [[T3]],0xff00
6166 ; MIPS32: ori [[T3]],[[T3]],0xffff
6167 ; MIPS32: and [[T2]],[[T2]],[[T3]]
6168 ; MIPS32: or [[T6]],[[T6]],[[T2]]
6169 ; MIPS32: srl [[T9:.*]],a2,0x18
6170 ; MIPS32: andi [[T9]],[[T9]],0x1
6171 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
6172 ; MIPS32: andi [[T10]],[[T10]],0x1
6173 ; MIPS32: sll [[T9]],[[T9]],0x1f
6174 ; MIPS32: sll [[T10]],[[T10]],0x1f
6175 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
6176 ; MIPS32: xori [[T10]],[[T10]],0x1
6177 ; MIPS32: srl [[T10]],[[T10]],0x18
6178 ; MIPS32: sll [[T6]],[[T6]],0x8
6179 ; MIPS32: srl [[T6]],[[T6]],0x8
6180 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
6181 ; MIPS32: andi [[T3]],a3,0xff
6182 ; MIPS32: andi [[T3]],[[T3]],0x1
6183 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
6184 ; MIPS32: andi [[T6]],[[T6]],0x1
6185 ; MIPS32: sll [[T3]],[[T3]],0x1f
6186 ; MIPS32: sll [[T6]],[[T6]],0x1f
6187 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6188 ; MIPS32: xori [[T6]],[[T6]],0x1
6189 ; MIPS32: andi [[T6]],[[T6]],0xff
6190 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
6191 ; MIPS32: sll [[T11]],[[T11]],0x8 6877 ; MIPS32: sll [[T11]],[[T11]],0x8
6192 ; MIPS32: or [[T6]],[[T6]],[[T11]] 6878 ; MIPS32: srl [[T11]],[[T11]],0x8
6193 ; MIPS32: srl [[T3]],a3,0x8 6879 ; MIPS32: or [[T3]],[[T3]],[[T11]]
6194 ; MIPS32: andi [[T3]],[[T3]],0xff 6880 ; MIPS32: move a0,[[T2]]
6195 ; MIPS32: andi [[T3]],[[T3]],0x1 6881 ; MIPS32: move a1,[[T3]]
6196 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
6197 ; MIPS32: andi [[T9]],[[T9]],0xff
6198 ; MIPS32: andi [[T9]],[[T9]],0x1
6199 ; MIPS32: sll [[T3]],[[T3]],0x1f
6200 ; MIPS32: sll [[T9]],[[T9]],0x1f
6201 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
6202 ; MIPS32: xori [[T9]],[[T9]],0x1
6203 ; MIPS32: andi [[T9]],[[T9]],0xff
6204 ; MIPS32: sll [[T9]],[[T9]],0x8
6205 ; MIPS32: lui [[T3]],0xffff
6206 ; MIPS32: ori [[T3]],[[T3]],0xff
6207 ; MIPS32: and [[T6]],[[T6]],[[T3]]
6208 ; MIPS32: or [[T9]],[[T9]],[[T6]]
6209 ; MIPS32: srl [[T3]],a3,0x10
6210 ; MIPS32: andi [[T3]],[[T3]],0xff
6211 ; MIPS32: andi [[T3]],[[T3]],0x1
6212 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
6213 ; MIPS32: andi [[T6]],[[T6]],0xff
6214 ; MIPS32: andi [[T6]],[[T6]],0x1
6215 ; MIPS32: sll [[T3]],[[T3]],0x1f
6216 ; MIPS32: sll [[T6]],[[T6]],0x1f
6217 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6218 ; MIPS32: xori [[T6]],[[T6]],0x1
6219 ; MIPS32: andi [[T6]],[[T6]],0xff
6220 ; MIPS32: sll [[T6]],[[T6]],0x10
6221 ; MIPS32: lui [[T3]],0xff00
6222 ; MIPS32: ori [[T3]],[[T3]],0xffff
6223 ; MIPS32: and [[T9]],[[T9]],[[T3]]
6224 ; MIPS32: or [[T6]],[[T6]],[[T9]]
6225 ; MIPS32: srl [[T12:.*]],a3,0x18
6226 ; MIPS32: andi [[T12]],[[T12]],0x1
6227 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
6228 ; MIPS32: andi [[T13]],[[T13]],0x1
6229 ; MIPS32: sll [[T12]],[[T12]],0x1f
6230 ; MIPS32: sll [[T13]],[[T13]],0x1f
6231 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
6232 ; MIPS32: xori [[T13]],[[T13]],0x1
6233 ; MIPS32: srl [[T13]],[[T13]],0x18
6234 ; MIPS32: sll [[T6]],[[T6]],0x8
6235 ; MIPS32: srl [[T6]],[[T6]],0x8
6236 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
6237 } 6882 }
6238 6883
6239 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) { 6884 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) {
6240 entry: 6885 entry:
6241 %res = icmp ult <16 x i1> %a, %b 6886 %res = icmp ult <16 x i1> %a, %b
6242 ret <16 x i1> %res 6887 ret <16 x i1> %res
6243 ; CHECK-LABEL: test_icmp_v16i1_ult 6888 ; CHECK-LABEL: test_icmp_v16i1_ult
6244 ; CHECK: pxor 6889 ; CHECK: pxor
6245 ; CHECK: pcmpgtb 6890 ; CHECK: pcmpgtb
6246 6891
6247 ; MIPS32-LABEL: test_icmp_v16i1_ult 6892 ; MIPS32-LABEL: test_icmp_v16i1_ult
6248 ; MIPS32: lw [[BV_E0:.*]], 6893 ; MIPS32: lw [[T0:.*]],
6249 ; MIPS32: lw [[BV_E1:.*]], 6894 ; MIPS32: lw [[T1:.*]],
6250 ; MIPS32: lw [[BV_E2:.*]], 6895 ; MIPS32: lw [[T2:.*]],
6251 ; MIPS32: lw [[BV_E3:.*]], 6896 ; MIPS32: lw [[T3:.*]],
6252 ; MIPS32: move [[TV_E0:.*]],zero 6897 ; MIPS32: move [[T4:.*]],zero
6253 ; MIPS32: move [[TV_E1:.*]],zero 6898 ; MIPS32: move [[T5:.*]],zero
6254 ; MIPS32: move [[TV_E2:.*]],zero 6899 ; MIPS32: move [[T6:.*]],zero
6255 ; MIPS32: move [[TV_E3:.*]],zero 6900 ; MIPS32: move [[T7:.*]],zero
6256 ; MIPS32: andi [[T0:.*]],a0,0xff 6901 ; MIPS32: move [[T8:.*]],a0
6257 ; MIPS32: andi [[T0]],[[T0]],0x1 6902 ; MIPS32: andi [[T8]],[[T8]],0xff
6258 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff 6903 ; MIPS32: andi [[T8]],[[T8]],0x1
6904 ; MIPS32: move [[T9:.*]],[[T0]]
6905 ; MIPS32: andi [[T9]],[[T9]],0xff
6906 ; MIPS32: andi [[T9]],[[T9]],0x1
6907 ; MIPS32: sll [[T8]],[[T8]],0x1f
6908 ; MIPS32: sll [[T9]],[[T9]],0x1f
6909 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
6910 ; MIPS32: andi [[T8]],[[T8]],0xff
6911 ; MIPS32: srl [[T4]],[[T4]],0x8
6912 ; MIPS32: sll [[T4]],[[T4]],0x8
6913 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6914 ; MIPS32: move [[T4]],a0
6915 ; MIPS32: srl [[T4]],[[T4]],0x8
6916 ; MIPS32: andi [[T4]],[[T4]],0xff
6917 ; MIPS32: andi [[T4]],[[T4]],0x1
6918 ; MIPS32: move [[T9]],[[T0]]
6919 ; MIPS32: srl [[T9]],[[T9]],0x8
6920 ; MIPS32: andi [[T9]],[[T9]],0xff
6921 ; MIPS32: andi [[T9]],[[T9]],0x1
6922 ; MIPS32: sll [[T4]],[[T4]],0x1f
6923 ; MIPS32: sll [[T9]],[[T9]],0x1f
6924 ; MIPS32: sltu [[T4]],[[T4]],[[T9]]
6925 ; MIPS32: andi [[T4]],[[T4]],0xff
6926 ; MIPS32: sll [[T4]],[[T4]],0x8
6927 ; MIPS32: lui [[T9]],0xffff
6928 ; MIPS32: ori [[T9]],[[T9]],0xff
6929 ; MIPS32: and [[T8]],[[T8]],[[T9]]
6930 ; MIPS32: or [[T4]],[[T4]],[[T8]]
6931 ; MIPS32: move [[T8]],a0
6932 ; MIPS32: srl [[T8]],[[T8]],0x10
6933 ; MIPS32: andi [[T8]],[[T8]],0xff
6934 ; MIPS32: andi [[T8]],[[T8]],0x1
6935 ; MIPS32: move [[T9]],[[T0]]
6936 ; MIPS32: srl [[T9]],[[T9]],0x10
6937 ; MIPS32: andi [[T9]],[[T9]],0xff
6938 ; MIPS32: andi [[T9]],[[T9]],0x1
6939 ; MIPS32: sll [[T8]],[[T8]],0x1f
6940 ; MIPS32: sll [[T9]],[[T9]],0x1f
6941 ; MIPS32: sltu [[T8]],[[T8]],[[T9]]
6942 ; MIPS32: andi [[T8]],[[T8]],0xff
6943 ; MIPS32: sll [[T8]],[[T8]],0x10
6944 ; MIPS32: lui [[T9]],0xff00
6945 ; MIPS32: ori [[T9]],[[T9]],0xffff
6946 ; MIPS32: and [[T4]],[[T4]],[[T9]]
6947 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6948 ; MIPS32: srl [[T10:.*]],a0,0x18
6949 ; MIPS32: andi [[T10]],[[T10]],0x1
6950 ; MIPS32: srl [[T0]],[[T0]],0x18
6951 ; MIPS32: andi [[T0]],[[T0]],0x1
6952 ; MIPS32: sll [[T10]],[[T10]],0x1f
6953 ; MIPS32: sll [[T0]],[[T0]],0x1f
6954 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
6955 ; MIPS32: srl [[T10]],[[T10]],0x18
6956 ; MIPS32: sll [[T8]],[[T8]],0x8
6957 ; MIPS32: srl [[T8]],[[T8]],0x8
6958 ; MIPS32: or [[T10]],[[T10]],[[T8]]
6959 ; MIPS32: move [[T0]],a1
6960 ; MIPS32: andi [[T0]],[[T0]],0xff
6961 ; MIPS32: andi [[T0]],[[T0]],0x1
6962 ; MIPS32: move [[T4]],[[T1]]
6963 ; MIPS32: andi [[T4]],[[T4]],0xff
6964 ; MIPS32: andi [[T4]],[[T4]],0x1
6965 ; MIPS32: sll [[T0]],[[T0]],0x1f
6966 ; MIPS32: sll [[T4]],[[T4]],0x1f
6967 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
6968 ; MIPS32: andi [[T0]],[[T0]],0xff
6969 ; MIPS32: srl [[T5]],[[T5]],0x8
6970 ; MIPS32: sll [[T5]],[[T5]],0x8
6971 ; MIPS32: or [[T0]],[[T0]],[[T5]]
6972 ; MIPS32: move [[T4]],a1
6973 ; MIPS32: srl [[T4]],[[T4]],0x8
6974 ; MIPS32: andi [[T4]],[[T4]],0xff
6975 ; MIPS32: andi [[T4]],[[T4]],0x1
6976 ; MIPS32: move [[T5]],[[T1]]
6977 ; MIPS32: srl [[T5]],[[T5]],0x8
6978 ; MIPS32: andi [[T5]],[[T5]],0xff
6979 ; MIPS32: andi [[T5]],[[T5]],0x1
6980 ; MIPS32: sll [[T4]],[[T4]],0x1f
6981 ; MIPS32: sll [[T5]],[[T5]],0x1f
6982 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
6983 ; MIPS32: andi [[T4]],[[T4]],0xff
6984 ; MIPS32: sll [[T4]],[[T4]],0x8
6985 ; MIPS32: lui [[T5]],0xffff
6986 ; MIPS32: ori [[T5]],[[T5]],0xff
6987 ; MIPS32: and [[T0]],[[T0]],[[T5]]
6988 ; MIPS32: or [[T4]],[[T4]],[[T0]]
6989 ; MIPS32: move [[T0]],a1
6990 ; MIPS32: srl [[T0]],[[T0]],0x10
6991 ; MIPS32: andi [[T0]],[[T0]],0xff
6992 ; MIPS32: andi [[T0]],[[T0]],0x1
6993 ; MIPS32: move [[T5]],[[T1]]
6994 ; MIPS32: srl [[T5]],[[T5]],0x10
6995 ; MIPS32: andi [[T5]],[[T5]],0xff
6996 ; MIPS32: andi [[T5]],[[T5]],0x1
6997 ; MIPS32: sll [[T0]],[[T0]],0x1f
6998 ; MIPS32: sll [[T5]],[[T5]],0x1f
6999 ; MIPS32: sltu [[T0]],[[T0]],[[T5]]
7000 ; MIPS32: andi [[T0]],[[T0]],0xff
7001 ; MIPS32: sll [[T0]],[[T0]],0x10
7002 ; MIPS32: lui [[T5]],0xff00
7003 ; MIPS32: ori [[T5]],[[T5]],0xffff
7004 ; MIPS32: and [[T4]],[[T4]],[[T5]]
7005 ; MIPS32: or [[T0]],[[T0]],[[T4]]
7006 ; MIPS32: srl [[T11:.*]],a1,0x18
7007 ; MIPS32: andi [[T11]],[[T11]],0x1
7008 ; MIPS32: srl [[T1]],[[T1]],0x18
7009 ; MIPS32: andi [[T1]],[[T1]],0x1
7010 ; MIPS32: sll [[T11]],[[T11]],0x1f
7011 ; MIPS32: sll [[T1]],[[T1]],0x1f
7012 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
7013 ; MIPS32: srl [[T11]],[[T11]],0x18
7014 ; MIPS32: sll [[T0]],[[T0]],0x8
7015 ; MIPS32: srl [[T0]],[[T0]],0x8
7016 ; MIPS32: or [[T11]],[[T11]],[[T0]]
7017 ; MIPS32: move [[T0]],a2
7018 ; MIPS32: andi [[T0]],[[T0]],0xff
7019 ; MIPS32: andi [[T0]],[[T0]],0x1
7020 ; MIPS32: move [[T1]],[[T2]]
7021 ; MIPS32: andi [[T1]],[[T1]],0xff
6259 ; MIPS32: andi [[T1]],[[T1]],0x1 7022 ; MIPS32: andi [[T1]],[[T1]],0x1
6260 ; MIPS32: sll [[T0]],[[T0]],0x1f 7023 ; MIPS32: sll [[T0]],[[T0]],0x1f
6261 ; MIPS32: sll [[T1]],[[T1]],0x1f 7024 ; MIPS32: sll [[T1]],[[T1]],0x1f
6262 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 7025 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
6263 ; MIPS32: andi [[T0]],[[T0]],0xff 7026 ; MIPS32: andi [[T0]],[[T0]],0xff
6264 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 7027 ; MIPS32: srl [[T6]],[[T6]],0x8
6265 ; MIPS32: sll [[T2]],[[T2]],0x8 7028 ; MIPS32: sll [[T6]],[[T6]],0x8
6266 ; MIPS32: or [[T0]],[[T0]],[[T2]] 7029 ; MIPS32: or [[T0]],[[T0]],[[T6]]
6267 ; MIPS32: srl [[T2]],a0,0x8 7030 ; MIPS32: move [[T1]],a2
7031 ; MIPS32: srl [[T1]],[[T1]],0x8
7032 ; MIPS32: andi [[T1]],[[T1]],0xff
7033 ; MIPS32: andi [[T1]],[[T1]],0x1
7034 ; MIPS32: move [[T4]],[[T2]]
7035 ; MIPS32: srl [[T4]],[[T4]],0x8
7036 ; MIPS32: andi [[T4]],[[T4]],0xff
7037 ; MIPS32: andi [[T4]],[[T4]],0x1
7038 ; MIPS32: sll [[T1]],[[T1]],0x1f
7039 ; MIPS32: sll [[T4]],[[T4]],0x1f
7040 ; MIPS32: sltu [[T1]],[[T1]],[[T4]]
7041 ; MIPS32: andi [[T1]],[[T1]],0xff
7042 ; MIPS32: sll [[T1]],[[T1]],0x8
7043 ; MIPS32: lui [[T4]],0xffff
7044 ; MIPS32: ori [[T4]],[[T4]],0xff
7045 ; MIPS32: and [[T0]],[[T0]],[[T4]]
7046 ; MIPS32: or [[T1]],[[T1]],[[T0]]
7047 ; MIPS32: move [[T0]],a2
7048 ; MIPS32: srl [[T0]],[[T0]],0x10
7049 ; MIPS32: andi [[T0]],[[T0]],0xff
7050 ; MIPS32: andi [[T0]],[[T0]],0x1
7051 ; MIPS32: move [[T4]],[[T2]]
7052 ; MIPS32: srl [[T4]],[[T4]],0x10
7053 ; MIPS32: andi [[T4]],[[T4]],0xff
7054 ; MIPS32: andi [[T4]],[[T4]],0x1
7055 ; MIPS32: sll [[T0]],[[T0]],0x1f
7056 ; MIPS32: sll [[T4]],[[T4]],0x1f
7057 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
7058 ; MIPS32: andi [[T0]],[[T0]],0xff
7059 ; MIPS32: sll [[T0]],[[T0]],0x10
7060 ; MIPS32: lui [[T4]],0xff00
7061 ; MIPS32: ori [[T4]],[[T4]],0xffff
7062 ; MIPS32: and [[T1]],[[T1]],[[T4]]
7063 ; MIPS32: or [[T0]],[[T0]],[[T1]]
7064 ; MIPS32: srl [[T12:.*]],a2,0x18
7065 ; MIPS32: andi [[T12]],[[T12]],0x1
7066 ; MIPS32: srl [[T2]],[[T2]],0x18
7067 ; MIPS32: andi [[T2]],[[T2]],0x1
7068 ; MIPS32: sll [[T12]],[[T12]],0x1f
7069 ; MIPS32: sll [[T2]],[[T2]],0x1f
7070 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
7071 ; MIPS32: srl [[T12]],[[T12]],0x18
7072 ; MIPS32: sll [[T0]],[[T0]],0x8
7073 ; MIPS32: srl [[T0]],[[T0]],0x8
7074 ; MIPS32: or [[T12]],[[T12]],[[T0]]
7075 ; MIPS32: move [[T0]],a3
7076 ; MIPS32: andi [[T0]],[[T0]],0xff
7077 ; MIPS32: andi [[T0]],[[T0]],0x1
7078 ; MIPS32: move [[T1]],[[T3]]
7079 ; MIPS32: andi [[T1]],[[T1]],0xff
7080 ; MIPS32: andi [[T1]],[[T1]],0x1
7081 ; MIPS32: sll [[T0]],[[T0]],0x1f
7082 ; MIPS32: sll [[T1]],[[T1]],0x1f
7083 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
7084 ; MIPS32: andi [[T0]],[[T0]],0xff
7085 ; MIPS32: srl [[T7]],[[T7]],0x8
7086 ; MIPS32: sll [[T7]],[[T7]],0x8
7087 ; MIPS32: or [[T0]],[[T0]],[[T7]]
7088 ; MIPS32: move [[T1]],a3
7089 ; MIPS32: srl [[T1]],[[T1]],0x8
7090 ; MIPS32: andi [[T1]],[[T1]],0xff
7091 ; MIPS32: andi [[T1]],[[T1]],0x1
7092 ; MIPS32: move [[T2]],[[T3]]
7093 ; MIPS32: srl [[T2]],[[T2]],0x8
6268 ; MIPS32: andi [[T2]],[[T2]],0xff 7094 ; MIPS32: andi [[T2]],[[T2]],0xff
6269 ; MIPS32: andi [[T2]],[[T2]],0x1 7095 ; MIPS32: andi [[T2]],[[T2]],0x1
6270 ; MIPS32: srl [[T1]],[[BV_E0]],0x8 7096 ; MIPS32: sll [[T1]],[[T1]],0x1f
6271 ; MIPS32: andi [[T1]],[[T1]],0xff
6272 ; MIPS32: andi [[T1]],[[T1]],0x1
6273 ; MIPS32: sll [[T2]],[[T2]],0x1f 7097 ; MIPS32: sll [[T2]],[[T2]],0x1f
6274 ; MIPS32: sll [[T1]],[[T1]],0x1f 7098 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
6275 ; MIPS32: sltu [[T2]],[[T2]],[[T1]] 7099 ; MIPS32: andi [[T1]],[[T1]],0xff
7100 ; MIPS32: sll [[T1]],[[T1]],0x8
7101 ; MIPS32: lui [[T2]],0xffff
7102 ; MIPS32: ori [[T2]],[[T2]],0xff
7103 ; MIPS32: and [[T0]],[[T0]],[[T2]]
7104 ; MIPS32: or [[T1]],[[T1]],[[T0]]
7105 ; MIPS32: move [[T0]],a3
7106 ; MIPS32: srl [[T0]],[[T0]],0x10
7107 ; MIPS32: andi [[T0]],[[T0]],0xff
7108 ; MIPS32: andi [[T0]],[[T0]],0x1
7109 ; MIPS32: move [[T2]],[[T3]]
7110 ; MIPS32: srl [[T2]],[[T2]],0x10
6276 ; MIPS32: andi [[T2]],[[T2]],0xff 7111 ; MIPS32: andi [[T2]],[[T2]],0xff
6277 ; MIPS32: sll [[T2]],[[T2]],0x8 7112 ; MIPS32: andi [[T2]],[[T2]],0x1
6278 ; MIPS32: lui [[T1]],0xffff 7113 ; MIPS32: sll [[T0]],[[T0]],0x1f
6279 ; MIPS32: ori [[T1]],[[T1]],0xff 7114 ; MIPS32: sll [[T2]],[[T2]],0x1f
6280 ; MIPS32: and [[T0]],[[T0]],[[T1]] 7115 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
6281 ; MIPS32: or [[T2]],[[T2]],[[T0]]
6282 ; MIPS32: srl [[T0]],a0,0x10
6283 ; MIPS32: andi [[T0]],[[T0]],0xff
6284 ; MIPS32: andi [[T0]],[[T0]],0x1
6285 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
6286 ; MIPS32: andi [[T1]],[[T1]],0xff
6287 ; MIPS32: andi [[T1]],[[T1]],0x1
6288 ; MIPS32: sll [[T0]],[[T0]],0x1f
6289 ; MIPS32: sll [[T1]],[[T1]],0x1f
6290 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
6291 ; MIPS32: andi [[T0]],[[T0]],0xff 7116 ; MIPS32: andi [[T0]],[[T0]],0xff
6292 ; MIPS32: sll [[T0]],[[T0]],0x10 7117 ; MIPS32: sll [[T0]],[[T0]],0x10
6293 ; MIPS32: lui [[T1]],0xff00 7118 ; MIPS32: lui [[T2]],0xff00
6294 ; MIPS32: ori [[T1]],[[T1]],0xffff 7119 ; MIPS32: ori [[T2]],[[T2]],0xffff
6295 ; MIPS32: and [[T2]],[[T2]],[[T1]] 7120 ; MIPS32: and [[T1]],[[T1]],[[T2]]
6296 ; MIPS32: or [[T0]],[[T0]],[[T2]] 7121 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6297 ; MIPS32: srl [[T3:.*]],a0,0x18 7122 ; MIPS32: srl [[T13:.*]],a3,0x18
7123 ; MIPS32: andi [[T13]],[[T13]],0x1
7124 ; MIPS32: srl [[T3]],[[T3]],0x18
6298 ; MIPS32: andi [[T3]],[[T3]],0x1 7125 ; MIPS32: andi [[T3]],[[T3]],0x1
6299 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 7126 ; MIPS32: sll [[T13]],[[T13]],0x1f
6300 ; MIPS32: andi [[T4]],[[T4]],0x1
6301 ; MIPS32: sll [[T3]],[[T3]],0x1f 7127 ; MIPS32: sll [[T3]],[[T3]],0x1f
6302 ; MIPS32: sll [[T4]],[[T4]],0x1f 7128 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
6303 ; MIPS32: sltu [[T3]],[[T3]],[[T4]] 7129 ; MIPS32: srl [[T13]],[[T13]],0x18
6304 ; MIPS32: srl [[T3]],[[T3]],0x18
6305 ; MIPS32: sll [[T0]],[[T0]],0x8 7130 ; MIPS32: sll [[T0]],[[T0]],0x8
6306 ; MIPS32: srl [[T0]],[[T0]],0x8 7131 ; MIPS32: srl [[T0]],[[T0]],0x8
6307 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] 7132 ; MIPS32: or [[T13]],[[T13]],[[T0]]
6308 ; MIPS32: andi [[T4]],a1,0xff 7133 ; MIPS32: move v0,[[T10]]
6309 ; MIPS32: andi [[T4]],[[T4]],0x1 7134 ; MIPS32: move v1,[[T11]]
6310 ; MIPS32: andi [[T2]],[[BV_E1]],0xff 7135 ; MIPS32: move a0,[[T12]]
6311 ; MIPS32: andi [[T2]],[[T2]],0x1 7136 ; MIPS32: move a1,[[T13]]
6312 ; MIPS32: sll [[T4]],[[T4]],0x1f
6313 ; MIPS32: sll [[T2]],[[T2]],0x1f
6314 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
6315 ; MIPS32: andi [[T4]],[[T4]],0xff
6316 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
6317 ; MIPS32: sll [[T5]],[[T5]],0x8
6318 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6319 ; MIPS32: srl [[T2]],a1,0x8
6320 ; MIPS32: andi [[T2]],[[T2]],0xff
6321 ; MIPS32: andi [[T2]],[[T2]],0x1
6322 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
6323 ; MIPS32: andi [[T5]],[[T5]],0xff
6324 ; MIPS32: andi [[T5]],[[T5]],0x1
6325 ; MIPS32: sll [[T2]],[[T2]],0x1f
6326 ; MIPS32: sll [[T5]],[[T5]],0x1f
6327 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
6328 ; MIPS32: andi [[T2]],[[T2]],0xff
6329 ; MIPS32: sll [[T2]],[[T2]],0x8
6330 ; MIPS32: lui [[T5]],0xffff
6331 ; MIPS32: ori [[T5]],[[T5]],0xff
6332 ; MIPS32: and [[T4]],[[T4]],[[T5]]
6333 ; MIPS32: or [[T2]],[[T2]],[[T4]]
6334 ; MIPS32: srl [[T4]],a1,0x10
6335 ; MIPS32: andi [[T4]],[[T4]],0xff
6336 ; MIPS32: andi [[T4]],[[T4]],0x1
6337 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
6338 ; MIPS32: andi [[T5]],[[T5]],0xff
6339 ; MIPS32: andi [[T5]],[[T5]],0x1
6340 ; MIPS32: sll [[T4]],[[T4]],0x1f
6341 ; MIPS32: sll [[T5]],[[T5]],0x1f
6342 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
6343 ; MIPS32: andi [[T4]],[[T4]],0xff
6344 ; MIPS32: sll [[T4]],[[T4]],0x10
6345 ; MIPS32: lui [[T5]],0xff00
6346 ; MIPS32: ori [[T5]],[[T5]],0xffff
6347 ; MIPS32: and [[T2]],[[T2]],[[T5]]
6348 ; MIPS32: or [[T4]],[[T4]],[[T2]]
6349 ; MIPS32: srl [[T6:.*]],a1,0x18
6350 ; MIPS32: andi [[T6]],[[T6]],0x1
6351 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
6352 ; MIPS32: andi [[T7]],[[T7]],0x1
6353 ; MIPS32: sll [[T6]],[[T6]],0x1f
6354 ; MIPS32: sll [[T7]],[[T7]],0x1f
6355 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
6356 ; MIPS32: srl [[T6]],[[T6]],0x18
6357 ; MIPS32: sll [[T4]],[[T4]],0x8
6358 ; MIPS32: srl [[T4]],[[T4]],0x8
6359 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
6360 ; MIPS32: andi [[T4]],a2,0xff
6361 ; MIPS32: andi [[T4]],[[T4]],0x1
6362 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
6363 ; MIPS32: andi [[T7]],[[T7]],0x1
6364 ; MIPS32: sll [[T4]],[[T4]],0x1f
6365 ; MIPS32: sll [[T7]],[[T7]],0x1f
6366 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
6367 ; MIPS32: andi [[T4]],[[T4]],0xff
6368 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
6369 ; MIPS32: sll [[T8]],[[T8]],0x8
6370 ; MIPS32: or [[T4]],[[T4]],[[T8]]
6371 ; MIPS32: srl [[T7]],a2,0x8
6372 ; MIPS32: andi [[T7]],[[T7]],0xff
6373 ; MIPS32: andi [[T7]],[[T7]],0x1
6374 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
6375 ; MIPS32: andi [[T2]],[[T2]],0xff
6376 ; MIPS32: andi [[T2]],[[T2]],0x1
6377 ; MIPS32: sll [[T7]],[[T7]],0x1f
6378 ; MIPS32: sll [[T2]],[[T2]],0x1f
6379 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
6380 ; MIPS32: andi [[T7]],[[T7]],0xff
6381 ; MIPS32: sll [[T7]],[[T7]],0x8
6382 ; MIPS32: lui [[T2]],0xffff
6383 ; MIPS32: ori [[T2]],[[T2]],0xff
6384 ; MIPS32: and [[T4]],[[T4]],[[T2]]
6385 ; MIPS32: or [[T7]],[[T7]],[[T4]]
6386 ; MIPS32: srl [[T4]],a2,0x10
6387 ; MIPS32: andi [[T4]],[[T4]],0xff
6388 ; MIPS32: andi [[T4]],[[T4]],0x1
6389 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
6390 ; MIPS32: andi [[T2]],[[T2]],0xff
6391 ; MIPS32: andi [[T2]],[[T2]],0x1
6392 ; MIPS32: sll [[T4]],[[T4]],0x1f
6393 ; MIPS32: sll [[T2]],[[T2]],0x1f
6394 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
6395 ; MIPS32: andi [[T4]],[[T4]],0xff
6396 ; MIPS32: sll [[T4]],[[T4]],0x10
6397 ; MIPS32: lui [[T2]],0xff00
6398 ; MIPS32: ori [[T2]],[[T2]],0xffff
6399 ; MIPS32: and [[T7]],[[T7]],[[T2]]
6400 ; MIPS32: or [[T4]],[[T4]],[[T7]]
6401 ; MIPS32: srl [[T9:.*]],a2,0x18
6402 ; MIPS32: andi [[T9]],[[T9]],0x1
6403 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
6404 ; MIPS32: andi [[T10]],[[T10]],0x1
6405 ; MIPS32: sll [[T9]],[[T9]],0x1f
6406 ; MIPS32: sll [[T10]],[[T10]],0x1f
6407 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
6408 ; MIPS32: srl [[T9]],[[T9]],0x18
6409 ; MIPS32: sll [[T4]],[[T4]],0x8
6410 ; MIPS32: srl [[T4]],[[T4]],0x8
6411 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
6412 ; MIPS32: andi [[T4]],a3,0xff
6413 ; MIPS32: andi [[T4]],[[T4]],0x1
6414 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
6415 ; MIPS32: andi [[T7]],[[T7]],0x1
6416 ; MIPS32: sll [[T4]],[[T4]],0x1f
6417 ; MIPS32: sll [[T7]],[[T7]],0x1f
6418 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
6419 ; MIPS32: andi [[T4]],[[T4]],0xff
6420 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
6421 ; MIPS32: sll [[T11]],[[T11]],0x8
6422 ; MIPS32: or [[T4]],[[T4]],[[T11]]
6423 ; MIPS32: srl [[T7]],a3,0x8
6424 ; MIPS32: andi [[T7]],[[T7]],0xff
6425 ; MIPS32: andi [[T7]],[[T7]],0x1
6426 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
6427 ; MIPS32: andi [[T10]],[[T10]],0xff
6428 ; MIPS32: andi [[T10]],[[T10]],0x1
6429 ; MIPS32: sll [[T7]],[[T7]],0x1f
6430 ; MIPS32: sll [[T10]],[[T10]],0x1f
6431 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
6432 ; MIPS32: andi [[T7]],[[T7]],0xff
6433 ; MIPS32: sll [[T7]],[[T7]],0x8
6434 ; MIPS32: lui [[T10]],0xffff
6435 ; MIPS32: ori [[T10]],[[T10]],0xff
6436 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6437 ; MIPS32: or [[T7]],[[T7]],[[T4]]
6438 ; MIPS32: srl [[T4]],a3,0x10
6439 ; MIPS32: andi [[T4]],[[T4]],0xff
6440 ; MIPS32: andi [[T4]],[[T4]],0x1
6441 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
6442 ; MIPS32: andi [[T10]],[[T10]],0xff
6443 ; MIPS32: andi [[T10]],[[T10]],0x1
6444 ; MIPS32: sll [[T4]],[[T4]],0x1f
6445 ; MIPS32: sll [[T10]],[[T10]],0x1f
6446 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6447 ; MIPS32: andi [[T4]],[[T4]],0xff
6448 ; MIPS32: sll [[T4]],[[T4]],0x10
6449 ; MIPS32: lui [[T10]],0xff00
6450 ; MIPS32: ori [[T10]],[[T10]],0xffff
6451 ; MIPS32: and [[T7]],[[T7]],[[T10]]
6452 ; MIPS32: or [[T4]],[[T4]],[[T7]]
6453 ; MIPS32: srl [[T12:.*]],a3,0x18
6454 ; MIPS32: andi [[T12]],[[T12]],0x1
6455 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
6456 ; MIPS32: andi [[T13]],[[T13]],0x1
6457 ; MIPS32: sll [[T12]],[[T12]],0x1f
6458 ; MIPS32: sll [[T13]],[[T13]],0x1f
6459 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
6460 ; MIPS32: srl [[T12]],[[T12]],0x18
6461 ; MIPS32: sll [[T4]],[[T4]],0x8
6462 ; MIPS32: srl [[T4]],[[T4]],0x8
6463 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
6464 } 7137 }
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