[SubZero] Fix code generation for vector type

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 3229 matching lines @@
     }
   }
 
   if (Dest == nullptr)
     return;
 
   // Assign the result of the call to Dest.
   if (ReturnReg) {
     if (RetVecFloat) {
       auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
+      auto *TBase = legalizeToReg(RetVecFloat);
       for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
         auto *Var = DestVecOn32->getContainers()[i];
+        auto *TVar = makeReg(IceType_i32);
         OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
-            Func, IceType_i32, RetVecFloat,
+            Func, IceType_i32, TBase,
             llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
-        _lw(Var, Mem);
+        _lw(TVar, Mem);
+        _mov(Var, TVar);
       }
     } else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) {
       auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
       for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
         _mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]);
       }
     } else if (ReturnRegHi) {
       assert(Dest->getType() == IceType_i64);
       auto *Dest64On32 = llvm::cast<Variable64On32>(Dest);
       Variable *DestLo = Dest64On32->getLo();
@@ skipping 265 matching lines @@
   Operand *Src1 = Instr->getSrc(1);
   if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) {
     const uint32_t Index = Imm->getValue();
     Variable *TDest = makeReg(DestTy);
     Variable *TReg = makeReg(DestTy);
     auto *Src0 = legalizeUndef(Instr->getSrc(0));
     auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
     // Number of elements in each container
     uint32_t ElemPerCont =
         typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
-    auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
+    auto *Src = Src0R->getContainers()[Index / ElemPerCont];
+    auto *SrcE = legalizeToReg(Src);
     // Position of the element in the container
     uint32_t PosInCont = Index % ElemPerCont;
     if (ElemPerCont == 1) {
       _mov(TDest, SrcE);
     } else if (ElemPerCont == 2) {
       switch (PosInCont) {
       case 0:
         _andi(TDest, SrcE, 0xffff);
         break;
       case 1:
@@ skipping 491 matching lines @@
   Operand *Src2 = Instr->getSrc(2);
   if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
     const uint32_t Index = Imm->getValue();
     // Vector to insert in
     auto *Src0 = legalizeUndef(Instr->getSrc(0));
     auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
     // Number of elements in each container
     uint32_t ElemPerCont =
         typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
     // Source Element
-    auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
+    auto *Src = Src0R->getContainers()[Index / ElemPerCont];
+    auto *SrcE = Src;
+    if (ElemPerCont > 1)
+      SrcE = legalizeToReg(Src);
     // Dest is a vector
     auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
     VDest->initVecElement(Func);
     // Temp vector variable
     auto *TDest = makeReg(DestTy);
     auto *TVDest = llvm::dyn_cast<VariableVecOn32>(TDest);
     TVDest->initVecElement(Func);
     // Destination element
     auto *DstE = TVDest->getContainers()[Index / ElemPerCont];
     // Element to insert
     auto *Src1R = legalizeToReg(Instr->getSrc(1));
     auto *TReg1 = makeReg(Src1R->getType());
     auto *TReg2 = makeReg(Src1R->getType());
     auto *TReg3 = makeReg(Src1R->getType());
     auto *TReg4 = makeReg(Src1R->getType());
     auto *TReg5 = makeReg(Src1R->getType());
+    auto *TDReg = makeReg(Src1R->getType());
     // Position of the element in the container
     uint32_t PosInCont = Index % ElemPerCont;
     // Load source vector in a temporary vector
     for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) {
       auto *DCont = TVDest->getContainers()[i];
       // Do not define DstE as we are going to redefine it
       if (DCont == DstE)
         continue;
       auto *SCont = Src0R->getContainers()[i];
       auto *TReg = makeReg(IceType_i32);
       _mov(TReg, SCont);
       _mov(DCont, TReg);
     }
     // Insert the element
     if (ElemPerCont == 1) {
       _mov(DstE, Src1R);
     } else if (ElemPerCont == 2) {
       switch (PosInCont) {
       case 0:
         _andi(TReg1, Src1R, 0xffff); // Clear upper 16-bits of source
         _srl(TReg2, SrcE, 16);
         _sll(TReg3, TReg2, 16); // Clear lower 16-bits of element
-        _or(DstE, TReg1, TReg3);
+        _or(TDReg, TReg1, TReg3);
+        _mov(DstE, TDReg);
         break;
       case 1:
         _sll(TReg1, Src1R, 16); // Clear lower 16-bits  of source
         _sll(TReg2, SrcE, 16);
         _srl(TReg3, TReg2, 16); // Clear upper 16-bits of element
-        _or(DstE, TReg1, TReg3);
+        _or(TDReg, TReg1, TReg3);
+        _mov(DstE, TDReg);
         break;
       default:
         llvm::report_fatal_error("InsertElement: Invalid PosInCont");
         break;
       }
     } else if (ElemPerCont == 4) {
       switch (PosInCont) {
       case 0:
         _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
         _srl(TReg2, SrcE, 8);
         _sll(TReg3, TReg2, 8); // Clear bits[7:0] of element
-        _or(DstE, TReg1, TReg3);
+        _or(TDReg, TReg1, TReg3);
+        _mov(DstE, TDReg);
         break;
       case 1:
         _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
         _sll(TReg5, TReg1, 8);     // Position in the destination
         _lui(TReg2, Ctx->getConstantInt32(0xffff));
         _ori(TReg3, TReg2, 0x00ff);
         _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element
-        _or(DstE, TReg5, TReg4);
+        _or(TDReg, TReg5, TReg4);
+        _mov(DstE, TDReg);
         break;
       case 2:
         _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
         _sll(TReg5, TReg1, 16);    // Position in the destination
         _lui(TReg2, Ctx->getConstantInt32(0xff00));
         _ori(TReg3, TReg2, 0xffff);
         _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element
-        _or(DstE, TReg5, TReg4);
+        _or(TDReg, TReg5, TReg4);
+        _mov(DstE, TDReg);
         break;
       case 3:
         _srl(TReg1, Src1R, 24); // Position in the destination
         _sll(TReg2, SrcE, 8);
         _srl(TReg3, TReg2, 8); // Clear bits[31:24] of element
-        _or(DstE, TReg1, TReg3);
+        _or(TDReg, TReg1, TReg3);
+        _mov(DstE, TDReg);
         break;
       default:
         llvm::report_fatal_error("InsertElement: Invalid PosInCont");
         break;
       }
     }
     // Write back temporary vector to the destination
     auto *Assign = InstAssign::create(Func, Dest, TDest);
     lowerAssign(Assign);
     return;
@@ skipping 596 matching lines @@
       Reg = R0;
       Context.insert<InstFakeUse>(R1);
       break;
     }
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32: {
-      auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0);
+      auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0));
       Variable *V0 =
           legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0);
       Variable *V1 =
           legalizeToReg(SrcVec->getContainers()[1], RegMIPS32::Reg_V1);
       Variable *A0 =
           legalizeToReg(SrcVec->getContainers()[2], RegMIPS32::Reg_A0);
       Variable *A1 =
           legalizeToReg(SrcVec->getContainers()[3], RegMIPS32::Reg_A1);
       Reg = V0;
       Context.insert<InstFakeUse>(V1);
       Context.insert<InstFakeUse>(A0);
       Context.insert<InstFakeUse>(A1);
       break;
     }
     case IceType_v4f32: {
-      auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0);
+      auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0));
       Reg = getImplicitRet();
       auto *RegT = legalizeToReg(Reg);
       // Return the vector through buffer in implicit argument a0
       for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) {
         OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
             Func, IceType_f32, RegT,
             llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
         Variable *Var = legalizeToReg(SrcVec->getContainers()[i]);
         _sw(Var, Mem);
       }
@@ skipping 23 matching lines @@
   Variable *DestR = nullptr;
   Variable *DestHiR = nullptr;
   Variable *SrcTR = nullptr;
   Variable *SrcTHiR = nullptr;
   Variable *SrcFR = nullptr;
   Variable *SrcFHiR = nullptr;
 
   if (DestTy == IceType_i64) {
     DestR = llvm::cast<Variable>(loOperand(Dest));
     DestHiR = llvm::cast<Variable>(hiOperand(Dest));
-    SrcTR = legalizeToReg(loOperand(Instr->getTrueOperand()));
-    SrcTHiR = legalizeToReg(hiOperand(Instr->getTrueOperand()));
-    SrcFR = legalizeToReg(loOperand(Instr->getFalseOperand()));
-    SrcFHiR = legalizeToReg(hiOperand(Instr->getFalseOperand()));
+    SrcTR = legalizeToReg(loOperand(legalizeUndef(Instr->getTrueOperand())));
+    SrcTHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getTrueOperand())));
+    SrcFR = legalizeToReg(loOperand(legalizeUndef(Instr->getFalseOperand())));
+    SrcFHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getFalseOperand())));
   } else {
-    SrcTR = legalizeToReg(Instr->getTrueOperand());
-    SrcFR = legalizeToReg(Instr->getFalseOperand());
+    SrcTR = legalizeToReg(legalizeUndef(Instr->getTrueOperand()));
+    SrcFR = legalizeToReg(legalizeUndef(Instr->getFalseOperand()));
   }
 
   Variable *ConditionR = legalizeToReg(Instr->getCondition());
 
   assert(Instr->getCondition()->getType() == IceType_i1);
 
   switch (DestTy) {
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
@@ skipping 506 matching lines @@
   Str << "\t.set\t"
       << "noat\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice