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1 // | 1 // |
2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
3 // | 3 // |
4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
6 // | 6 // |
7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
8 /// | 8 /// |
9 /// \file | 9 /// \file |
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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3240 } | 3240 } |
3241 } | 3241 } |
3242 | 3242 |
3243 if (Dest == nullptr) | 3243 if (Dest == nullptr) |
3244 return; | 3244 return; |
3245 | 3245 |
3246 // Assign the result of the call to Dest. | 3246 // Assign the result of the call to Dest. |
3247 if (ReturnReg) { | 3247 if (ReturnReg) { |
3248 if (RetVecFloat) { | 3248 if (RetVecFloat) { |
3249 auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); | 3249 auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); |
| 3250 auto *TBase = legalizeToReg(RetVecFloat); |
3250 for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) { | 3251 for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) { |
3251 auto *Var = DestVecOn32->getContainers()[i]; | 3252 auto *Var = DestVecOn32->getContainers()[i]; |
| 3253 auto *TVar = makeReg(IceType_i32); |
3252 OperandMIPS32Mem *Mem = OperandMIPS32Mem::create( | 3254 OperandMIPS32Mem *Mem = OperandMIPS32Mem::create( |
3253 Func, IceType_i32, RetVecFloat, | 3255 Func, IceType_i32, TBase, |
3254 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4))); | 3256 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4))); |
3255 _lw(Var, Mem); | 3257 _lw(TVar, Mem); |
| 3258 _mov(Var, TVar); |
3256 } | 3259 } |
3257 } else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) { | 3260 } else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) { |
3258 auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); | 3261 auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); |
3259 for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) { | 3262 for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) { |
3260 _mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]); | 3263 _mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]); |
3261 } | 3264 } |
3262 } else if (ReturnRegHi) { | 3265 } else if (ReturnRegHi) { |
3263 assert(Dest->getType() == IceType_i64); | 3266 assert(Dest->getType() == IceType_i64); |
3264 auto *Dest64On32 = llvm::cast<Variable64On32>(Dest); | 3267 auto *Dest64On32 = llvm::cast<Variable64On32>(Dest); |
3265 Variable *DestLo = Dest64On32->getLo(); | 3268 Variable *DestLo = Dest64On32->getLo(); |
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3531 Operand *Src1 = Instr->getSrc(1); | 3534 Operand *Src1 = Instr->getSrc(1); |
3532 if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) { | 3535 if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) { |
3533 const uint32_t Index = Imm->getValue(); | 3536 const uint32_t Index = Imm->getValue(); |
3534 Variable *TDest = makeReg(DestTy); | 3537 Variable *TDest = makeReg(DestTy); |
3535 Variable *TReg = makeReg(DestTy); | 3538 Variable *TReg = makeReg(DestTy); |
3536 auto *Src0 = legalizeUndef(Instr->getSrc(0)); | 3539 auto *Src0 = legalizeUndef(Instr->getSrc(0)); |
3537 auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0); | 3540 auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0); |
3538 // Number of elements in each container | 3541 // Number of elements in each container |
3539 uint32_t ElemPerCont = | 3542 uint32_t ElemPerCont = |
3540 typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; | 3543 typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; |
3541 auto *SrcE = Src0R->getContainers()[Index / ElemPerCont]; | 3544 auto *Src = Src0R->getContainers()[Index / ElemPerCont]; |
| 3545 auto *SrcE = legalizeToReg(Src); |
3542 // Position of the element in the container | 3546 // Position of the element in the container |
3543 uint32_t PosInCont = Index % ElemPerCont; | 3547 uint32_t PosInCont = Index % ElemPerCont; |
3544 if (ElemPerCont == 1) { | 3548 if (ElemPerCont == 1) { |
3545 _mov(TDest, SrcE); | 3549 _mov(TDest, SrcE); |
3546 } else if (ElemPerCont == 2) { | 3550 } else if (ElemPerCont == 2) { |
3547 switch (PosInCont) { | 3551 switch (PosInCont) { |
3548 case 0: | 3552 case 0: |
3549 _andi(TDest, SrcE, 0xffff); | 3553 _andi(TDest, SrcE, 0xffff); |
3550 break; | 3554 break; |
3551 case 1: | 3555 case 1: |
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4043 Operand *Src2 = Instr->getSrc(2); | 4047 Operand *Src2 = Instr->getSrc(2); |
4044 if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) { | 4048 if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) { |
4045 const uint32_t Index = Imm->getValue(); | 4049 const uint32_t Index = Imm->getValue(); |
4046 // Vector to insert in | 4050 // Vector to insert in |
4047 auto *Src0 = legalizeUndef(Instr->getSrc(0)); | 4051 auto *Src0 = legalizeUndef(Instr->getSrc(0)); |
4048 auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0); | 4052 auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0); |
4049 // Number of elements in each container | 4053 // Number of elements in each container |
4050 uint32_t ElemPerCont = | 4054 uint32_t ElemPerCont = |
4051 typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; | 4055 typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; |
4052 // Source Element | 4056 // Source Element |
4053 auto *SrcE = Src0R->getContainers()[Index / ElemPerCont]; | 4057 auto *Src = Src0R->getContainers()[Index / ElemPerCont]; |
| 4058 auto *SrcE = Src; |
| 4059 if (ElemPerCont > 1) |
| 4060 SrcE = legalizeToReg(Src); |
4054 // Dest is a vector | 4061 // Dest is a vector |
4055 auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest); | 4062 auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest); |
4056 VDest->initVecElement(Func); | 4063 VDest->initVecElement(Func); |
4057 // Temp vector variable | 4064 // Temp vector variable |
4058 auto *TDest = makeReg(DestTy); | 4065 auto *TDest = makeReg(DestTy); |
4059 auto *TVDest = llvm::dyn_cast<VariableVecOn32>(TDest); | 4066 auto *TVDest = llvm::dyn_cast<VariableVecOn32>(TDest); |
4060 TVDest->initVecElement(Func); | 4067 TVDest->initVecElement(Func); |
4061 // Destination element | 4068 // Destination element |
4062 auto *DstE = TVDest->getContainers()[Index / ElemPerCont]; | 4069 auto *DstE = TVDest->getContainers()[Index / ElemPerCont]; |
4063 // Element to insert | 4070 // Element to insert |
4064 auto *Src1R = legalizeToReg(Instr->getSrc(1)); | 4071 auto *Src1R = legalizeToReg(Instr->getSrc(1)); |
4065 auto *TReg1 = makeReg(Src1R->getType()); | 4072 auto *TReg1 = makeReg(Src1R->getType()); |
4066 auto *TReg2 = makeReg(Src1R->getType()); | 4073 auto *TReg2 = makeReg(Src1R->getType()); |
4067 auto *TReg3 = makeReg(Src1R->getType()); | 4074 auto *TReg3 = makeReg(Src1R->getType()); |
4068 auto *TReg4 = makeReg(Src1R->getType()); | 4075 auto *TReg4 = makeReg(Src1R->getType()); |
4069 auto *TReg5 = makeReg(Src1R->getType()); | 4076 auto *TReg5 = makeReg(Src1R->getType()); |
| 4077 auto *TDReg = makeReg(Src1R->getType()); |
4070 // Position of the element in the container | 4078 // Position of the element in the container |
4071 uint32_t PosInCont = Index % ElemPerCont; | 4079 uint32_t PosInCont = Index % ElemPerCont; |
4072 // Load source vector in a temporary vector | 4080 // Load source vector in a temporary vector |
4073 for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) { | 4081 for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) { |
4074 auto *DCont = TVDest->getContainers()[i]; | 4082 auto *DCont = TVDest->getContainers()[i]; |
4075 // Do not define DstE as we are going to redefine it | 4083 // Do not define DstE as we are going to redefine it |
4076 if (DCont == DstE) | 4084 if (DCont == DstE) |
4077 continue; | 4085 continue; |
4078 auto *SCont = Src0R->getContainers()[i]; | 4086 auto *SCont = Src0R->getContainers()[i]; |
4079 auto *TReg = makeReg(IceType_i32); | 4087 auto *TReg = makeReg(IceType_i32); |
4080 _mov(TReg, SCont); | 4088 _mov(TReg, SCont); |
4081 _mov(DCont, TReg); | 4089 _mov(DCont, TReg); |
4082 } | 4090 } |
4083 // Insert the element | 4091 // Insert the element |
4084 if (ElemPerCont == 1) { | 4092 if (ElemPerCont == 1) { |
4085 _mov(DstE, Src1R); | 4093 _mov(DstE, Src1R); |
4086 } else if (ElemPerCont == 2) { | 4094 } else if (ElemPerCont == 2) { |
4087 switch (PosInCont) { | 4095 switch (PosInCont) { |
4088 case 0: | 4096 case 0: |
4089 _andi(TReg1, Src1R, 0xffff); // Clear upper 16-bits of source | 4097 _andi(TReg1, Src1R, 0xffff); // Clear upper 16-bits of source |
4090 _srl(TReg2, SrcE, 16); | 4098 _srl(TReg2, SrcE, 16); |
4091 _sll(TReg3, TReg2, 16); // Clear lower 16-bits of element | 4099 _sll(TReg3, TReg2, 16); // Clear lower 16-bits of element |
4092 _or(DstE, TReg1, TReg3); | 4100 _or(TDReg, TReg1, TReg3); |
| 4101 _mov(DstE, TDReg); |
4093 break; | 4102 break; |
4094 case 1: | 4103 case 1: |
4095 _sll(TReg1, Src1R, 16); // Clear lower 16-bits of source | 4104 _sll(TReg1, Src1R, 16); // Clear lower 16-bits of source |
4096 _sll(TReg2, SrcE, 16); | 4105 _sll(TReg2, SrcE, 16); |
4097 _srl(TReg3, TReg2, 16); // Clear upper 16-bits of element | 4106 _srl(TReg3, TReg2, 16); // Clear upper 16-bits of element |
4098 _or(DstE, TReg1, TReg3); | 4107 _or(TDReg, TReg1, TReg3); |
| 4108 _mov(DstE, TDReg); |
4099 break; | 4109 break; |
4100 default: | 4110 default: |
4101 llvm::report_fatal_error("InsertElement: Invalid PosInCont"); | 4111 llvm::report_fatal_error("InsertElement: Invalid PosInCont"); |
4102 break; | 4112 break; |
4103 } | 4113 } |
4104 } else if (ElemPerCont == 4) { | 4114 } else if (ElemPerCont == 4) { |
4105 switch (PosInCont) { | 4115 switch (PosInCont) { |
4106 case 0: | 4116 case 0: |
4107 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source | 4117 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source |
4108 _srl(TReg2, SrcE, 8); | 4118 _srl(TReg2, SrcE, 8); |
4109 _sll(TReg3, TReg2, 8); // Clear bits[7:0] of element | 4119 _sll(TReg3, TReg2, 8); // Clear bits[7:0] of element |
4110 _or(DstE, TReg1, TReg3); | 4120 _or(TDReg, TReg1, TReg3); |
| 4121 _mov(DstE, TDReg); |
4111 break; | 4122 break; |
4112 case 1: | 4123 case 1: |
4113 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source | 4124 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source |
4114 _sll(TReg5, TReg1, 8); // Position in the destination | 4125 _sll(TReg5, TReg1, 8); // Position in the destination |
4115 _lui(TReg2, Ctx->getConstantInt32(0xffff)); | 4126 _lui(TReg2, Ctx->getConstantInt32(0xffff)); |
4116 _ori(TReg3, TReg2, 0x00ff); | 4127 _ori(TReg3, TReg2, 0x00ff); |
4117 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element | 4128 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element |
4118 _or(DstE, TReg5, TReg4); | 4129 _or(TDReg, TReg5, TReg4); |
| 4130 _mov(DstE, TDReg); |
4119 break; | 4131 break; |
4120 case 2: | 4132 case 2: |
4121 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source | 4133 _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source |
4122 _sll(TReg5, TReg1, 16); // Position in the destination | 4134 _sll(TReg5, TReg1, 16); // Position in the destination |
4123 _lui(TReg2, Ctx->getConstantInt32(0xff00)); | 4135 _lui(TReg2, Ctx->getConstantInt32(0xff00)); |
4124 _ori(TReg3, TReg2, 0xffff); | 4136 _ori(TReg3, TReg2, 0xffff); |
4125 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element | 4137 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element |
4126 _or(DstE, TReg5, TReg4); | 4138 _or(TDReg, TReg5, TReg4); |
| 4139 _mov(DstE, TDReg); |
4127 break; | 4140 break; |
4128 case 3: | 4141 case 3: |
4129 _srl(TReg1, Src1R, 24); // Position in the destination | 4142 _srl(TReg1, Src1R, 24); // Position in the destination |
4130 _sll(TReg2, SrcE, 8); | 4143 _sll(TReg2, SrcE, 8); |
4131 _srl(TReg3, TReg2, 8); // Clear bits[31:24] of element | 4144 _srl(TReg3, TReg2, 8); // Clear bits[31:24] of element |
4132 _or(DstE, TReg1, TReg3); | 4145 _or(TDReg, TReg1, TReg3); |
| 4146 _mov(DstE, TDReg); |
4133 break; | 4147 break; |
4134 default: | 4148 default: |
4135 llvm::report_fatal_error("InsertElement: Invalid PosInCont"); | 4149 llvm::report_fatal_error("InsertElement: Invalid PosInCont"); |
4136 break; | 4150 break; |
4137 } | 4151 } |
4138 } | 4152 } |
4139 // Write back temporary vector to the destination | 4153 // Write back temporary vector to the destination |
4140 auto *Assign = InstAssign::create(Func, Dest, TDest); | 4154 auto *Assign = InstAssign::create(Func, Dest, TDest); |
4141 lowerAssign(Assign); | 4155 lowerAssign(Assign); |
4142 return; | 4156 return; |
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4739 Reg = R0; | 4753 Reg = R0; |
4740 Context.insert<InstFakeUse>(R1); | 4754 Context.insert<InstFakeUse>(R1); |
4741 break; | 4755 break; |
4742 } | 4756 } |
4743 case IceType_v4i1: | 4757 case IceType_v4i1: |
4744 case IceType_v8i1: | 4758 case IceType_v8i1: |
4745 case IceType_v16i1: | 4759 case IceType_v16i1: |
4746 case IceType_v16i8: | 4760 case IceType_v16i8: |
4747 case IceType_v8i16: | 4761 case IceType_v8i16: |
4748 case IceType_v4i32: { | 4762 case IceType_v4i32: { |
4749 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0); | 4763 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); |
4750 Variable *V0 = | 4764 Variable *V0 = |
4751 legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0); | 4765 legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0); |
4752 Variable *V1 = | 4766 Variable *V1 = |
4753 legalizeToReg(SrcVec->getContainers()[1], RegMIPS32::Reg_V1); | 4767 legalizeToReg(SrcVec->getContainers()[1], RegMIPS32::Reg_V1); |
4754 Variable *A0 = | 4768 Variable *A0 = |
4755 legalizeToReg(SrcVec->getContainers()[2], RegMIPS32::Reg_A0); | 4769 legalizeToReg(SrcVec->getContainers()[2], RegMIPS32::Reg_A0); |
4756 Variable *A1 = | 4770 Variable *A1 = |
4757 legalizeToReg(SrcVec->getContainers()[3], RegMIPS32::Reg_A1); | 4771 legalizeToReg(SrcVec->getContainers()[3], RegMIPS32::Reg_A1); |
4758 Reg = V0; | 4772 Reg = V0; |
4759 Context.insert<InstFakeUse>(V1); | 4773 Context.insert<InstFakeUse>(V1); |
4760 Context.insert<InstFakeUse>(A0); | 4774 Context.insert<InstFakeUse>(A0); |
4761 Context.insert<InstFakeUse>(A1); | 4775 Context.insert<InstFakeUse>(A1); |
4762 break; | 4776 break; |
4763 } | 4777 } |
4764 case IceType_v4f32: { | 4778 case IceType_v4f32: { |
4765 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0); | 4779 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); |
4766 Reg = getImplicitRet(); | 4780 Reg = getImplicitRet(); |
4767 auto *RegT = legalizeToReg(Reg); | 4781 auto *RegT = legalizeToReg(Reg); |
4768 // Return the vector through buffer in implicit argument a0 | 4782 // Return the vector through buffer in implicit argument a0 |
4769 for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) { | 4783 for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) { |
4770 OperandMIPS32Mem *Mem = OperandMIPS32Mem::create( | 4784 OperandMIPS32Mem *Mem = OperandMIPS32Mem::create( |
4771 Func, IceType_f32, RegT, | 4785 Func, IceType_f32, RegT, |
4772 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4))); | 4786 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4))); |
4773 Variable *Var = legalizeToReg(SrcVec->getContainers()[i]); | 4787 Variable *Var = legalizeToReg(SrcVec->getContainers()[i]); |
4774 _sw(Var, Mem); | 4788 _sw(Var, Mem); |
4775 } | 4789 } |
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4799 Variable *DestR = nullptr; | 4813 Variable *DestR = nullptr; |
4800 Variable *DestHiR = nullptr; | 4814 Variable *DestHiR = nullptr; |
4801 Variable *SrcTR = nullptr; | 4815 Variable *SrcTR = nullptr; |
4802 Variable *SrcTHiR = nullptr; | 4816 Variable *SrcTHiR = nullptr; |
4803 Variable *SrcFR = nullptr; | 4817 Variable *SrcFR = nullptr; |
4804 Variable *SrcFHiR = nullptr; | 4818 Variable *SrcFHiR = nullptr; |
4805 | 4819 |
4806 if (DestTy == IceType_i64) { | 4820 if (DestTy == IceType_i64) { |
4807 DestR = llvm::cast<Variable>(loOperand(Dest)); | 4821 DestR = llvm::cast<Variable>(loOperand(Dest)); |
4808 DestHiR = llvm::cast<Variable>(hiOperand(Dest)); | 4822 DestHiR = llvm::cast<Variable>(hiOperand(Dest)); |
4809 SrcTR = legalizeToReg(loOperand(Instr->getTrueOperand())); | 4823 SrcTR = legalizeToReg(loOperand(legalizeUndef(Instr->getTrueOperand()))); |
4810 SrcTHiR = legalizeToReg(hiOperand(Instr->getTrueOperand())); | 4824 SrcTHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getTrueOperand()))); |
4811 SrcFR = legalizeToReg(loOperand(Instr->getFalseOperand())); | 4825 SrcFR = legalizeToReg(loOperand(legalizeUndef(Instr->getFalseOperand()))); |
4812 SrcFHiR = legalizeToReg(hiOperand(Instr->getFalseOperand())); | 4826 SrcFHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getFalseOperand()))); |
4813 } else { | 4827 } else { |
4814 SrcTR = legalizeToReg(Instr->getTrueOperand()); | 4828 SrcTR = legalizeToReg(legalizeUndef(Instr->getTrueOperand())); |
4815 SrcFR = legalizeToReg(Instr->getFalseOperand()); | 4829 SrcFR = legalizeToReg(legalizeUndef(Instr->getFalseOperand())); |
4816 } | 4830 } |
4817 | 4831 |
4818 Variable *ConditionR = legalizeToReg(Instr->getCondition()); | 4832 Variable *ConditionR = legalizeToReg(Instr->getCondition()); |
4819 | 4833 |
4820 assert(Instr->getCondition()->getType() == IceType_i1); | 4834 assert(Instr->getCondition()->getType() == IceType_i1); |
4821 | 4835 |
4822 switch (DestTy) { | 4836 switch (DestTy) { |
4823 case IceType_i1: | 4837 case IceType_i1: |
4824 case IceType_i8: | 4838 case IceType_i8: |
4825 case IceType_i16: | 4839 case IceType_i16: |
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5332 Str << "\t.set\t" | 5346 Str << "\t.set\t" |
5333 << "noat\n"; | 5347 << "noat\n"; |
5334 } | 5348 } |
5335 | 5349 |
5336 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 5350 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
5337 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 5351 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
5338 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 5352 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
5339 | 5353 |
5340 } // end of namespace MIPS32 | 5354 } // end of namespace MIPS32 |
5341 } // end of namespace Ice | 5355 } // end of namespace Ice |
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