[SubZero] Fix code generation for vector type

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 627 matching lines @@
   Asm->store(position(), (Inst & ~ImmMask) | (Imm & ImmMask));
 }
 
 void AssemblerMIPS32::jal(const ConstantRelocatable *Target) {
   IValueT Opcode = 0x0C000000;
   emitFixup(createMIPS32Fixup(RelocOp::RO_Jal, Target));
   emitInst(Opcode);
   nop();
 }
 
+void AssemblerMIPS32::jalr(const Operand *OpRs, const Operand *OpRd) {
+  IValueT Opcode = 0x00000009;
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr");
+  const IValueT Rd =
+      (OpRd == nullptr) ? 31 : encodeGPRegister(OpRd, "Rd", "jalr");
+  Opcode |= Rd << 16;
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+  nop();
+}
+
 void AssemblerMIPS32::lui(const Operand *OpRt, const Operand *OpImm,
                           const RelocOp Reloc) {
   IValueT Opcode = 0x3C000000;
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");
   IValueT Imm16 = 0;
 
   if (const auto *OpRel = llvm::dyn_cast<ConstantRelocatable>(OpImm)) {
     emitFixup(createMIPS32Fixup(Reloc, OpRel));
   } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(OpImm)) {
     Imm16 = C32->getValue();
@@ skipping 168 matching lines @@
 
 void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs,
                            const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x0000000B;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn");
 }
 
 void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
-  emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
+  emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
 }
 
 void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
-  emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
+  emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
 }
 
 void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs,
                            const Operand *OpCc) {
   IValueT Opcode = 0x00000001;
   const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt");
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt");
   OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0;
   if (const auto *OpFCC = llvm::dyn_cast<OperandMIPS32FCC>(OpCc)) {
     Cc = OpFCC->getFCC();
@@ skipping 370 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice