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Side by Side Diff: runtime/vm/stub_code_mips.cc

Issue 2463083002: Remove default monomorphic check code from functions and stubs that do not need it. (Closed)
Patch Set: address comment Created 4 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/code_generator.h" 9 #include "vm/code_generator.h"
10 #include "vm/compiler.h" 10 #include "vm/compiler.h"
(...skipping 2160 matching lines...) Expand 10 before | Expand all | Expand 10 after
2171 } 2171 }
2172 2172
2173 2173
2174 // Called from megamorphic calls. 2174 // Called from megamorphic calls.
2175 // T0: receiver 2175 // T0: receiver
2176 // S5: MegamorphicCache (preserved) 2176 // S5: MegamorphicCache (preserved)
2177 // Passed to target: 2177 // Passed to target:
2178 // CODE_REG: target Code object 2178 // CODE_REG: target Code object
2179 // S4: arguments descriptor 2179 // S4: arguments descriptor
2180 void StubCode::GenerateMegamorphicCallStub(Assembler* assembler) { 2180 void StubCode::GenerateMegamorphicCallStub(Assembler* assembler) {
2181 __ NoMonomorphicCheckedEntry();
2182
2183 __ LoadTaggedClassIdMayBeSmi(T0, T0); 2181 __ LoadTaggedClassIdMayBeSmi(T0, T0);
2184 // T0: class ID of the receiver (smi). 2182 // T0: class ID of the receiver (smi).
2185 __ lw(S4, FieldAddress(S5, MegamorphicCache::arguments_descriptor_offset())); 2183 __ lw(S4, FieldAddress(S5, MegamorphicCache::arguments_descriptor_offset()));
2186 __ lw(T2, FieldAddress(S5, MegamorphicCache::buckets_offset())); 2184 __ lw(T2, FieldAddress(S5, MegamorphicCache::buckets_offset()));
2187 __ lw(T1, FieldAddress(S5, MegamorphicCache::mask_offset())); 2185 __ lw(T1, FieldAddress(S5, MegamorphicCache::mask_offset()));
2188 // T2: cache buckets array. 2186 // T2: cache buckets array.
2189 // T1: mask. 2187 // T1: mask.
2190 __ LoadImmediate(TMP, MegamorphicCache::kSpreadFactor); 2188 __ LoadImmediate(TMP, MegamorphicCache::kSpreadFactor);
2191 __ mult(TMP, T0); 2189 __ mult(TMP, T0);
2192 __ mflo(T3); 2190 __ mflo(T3);
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after
2224 } 2222 }
2225 2223
2226 2224
2227 // Called from switchable IC calls. 2225 // Called from switchable IC calls.
2228 // T0: receiver 2226 // T0: receiver
2229 // S5: ICData (preserved) 2227 // S5: ICData (preserved)
2230 // Passed to target: 2228 // Passed to target:
2231 // CODE_REG: target Code object 2229 // CODE_REG: target Code object
2232 // S4: arguments descriptor 2230 // S4: arguments descriptor
2233 void StubCode::GenerateICCallThroughFunctionStub(Assembler* assembler) { 2231 void StubCode::GenerateICCallThroughFunctionStub(Assembler* assembler) {
2234 __ NoMonomorphicCheckedEntry();
2235
2236 Label loop, found, miss; 2232 Label loop, found, miss;
2237 __ lw(T6, FieldAddress(S5, ICData::ic_data_offset())); 2233 __ lw(T6, FieldAddress(S5, ICData::ic_data_offset()));
2238 __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset())); 2234 __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
2239 __ AddImmediate(T6, T6, Array::data_offset() - kHeapObjectTag); 2235 __ AddImmediate(T6, T6, Array::data_offset() - kHeapObjectTag);
2240 // T6: first IC entry. 2236 // T6: first IC entry.
2241 __ LoadTaggedClassIdMayBeSmi(T1, T0); 2237 __ LoadTaggedClassIdMayBeSmi(T1, T0);
2242 // T1: receiver cid as Smi 2238 // T1: receiver cid as Smi
2243 2239
2244 __ Bind(&loop); 2240 __ Bind(&loop);
2245 __ lw(T2, Address(T6, 0)); 2241 __ lw(T2, Address(T6, 0));
(...skipping 14 matching lines...) Expand all
2260 2256
2261 __ Bind(&miss); 2257 __ Bind(&miss);
2262 __ LoadIsolate(T2); 2258 __ LoadIsolate(T2);
2263 __ lw(CODE_REG, Address(T2, Isolate::ic_miss_code_offset())); 2259 __ lw(CODE_REG, Address(T2, Isolate::ic_miss_code_offset()));
2264 __ lw(T1, FieldAddress(CODE_REG, Code::entry_point_offset())); 2260 __ lw(T1, FieldAddress(CODE_REG, Code::entry_point_offset()));
2265 __ jr(T1); 2261 __ jr(T1);
2266 } 2262 }
2267 2263
2268 2264
2269 void StubCode::GenerateICCallThroughCodeStub(Assembler* assembler) { 2265 void StubCode::GenerateICCallThroughCodeStub(Assembler* assembler) {
2270 __ NoMonomorphicCheckedEntry();
2271
2272 Label loop, found, miss; 2266 Label loop, found, miss;
2273 __ lw(T6, FieldAddress(S5, ICData::ic_data_offset())); 2267 __ lw(T6, FieldAddress(S5, ICData::ic_data_offset()));
2274 __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset())); 2268 __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
2275 __ AddImmediate(T6, T6, Array::data_offset() - kHeapObjectTag); 2269 __ AddImmediate(T6, T6, Array::data_offset() - kHeapObjectTag);
2276 // T6: first IC entry. 2270 // T6: first IC entry.
2277 __ LoadTaggedClassIdMayBeSmi(T1, T0); 2271 __ LoadTaggedClassIdMayBeSmi(T1, T0);
2278 // T1: receiver cid as Smi 2272 // T1: receiver cid as Smi
2279 2273
2280 __ Bind(&loop); 2274 __ Bind(&loop);
2281 __ lw(T2, Address(T6, 0)); 2275 __ lw(T2, Address(T6, 0));
(...skipping 17 matching lines...) Expand all
2299 __ lw(CODE_REG, Address(T2, Isolate::ic_miss_code_offset())); 2293 __ lw(CODE_REG, Address(T2, Isolate::ic_miss_code_offset()));
2300 __ lw(T1, FieldAddress(CODE_REG, Code::entry_point_offset())); 2294 __ lw(T1, FieldAddress(CODE_REG, Code::entry_point_offset()));
2301 __ jr(T1); 2295 __ jr(T1);
2302 } 2296 }
2303 2297
2304 2298
2305 // Called from switchable IC calls. 2299 // Called from switchable IC calls.
2306 // T0: receiver 2300 // T0: receiver
2307 // S5: SingleTargetCache 2301 // S5: SingleTargetCache
2308 void StubCode::GenerateUnlinkedCallStub(Assembler* assembler) { 2302 void StubCode::GenerateUnlinkedCallStub(Assembler* assembler) {
2309 __ NoMonomorphicCheckedEntry();
2310
2311 __ EnterStubFrame(); 2303 __ EnterStubFrame();
2312 __ Push(T0); // Preserve receiver. 2304 __ Push(T0); // Preserve receiver.
2313 2305
2314 __ Push(ZR); // Result slot. 2306 __ Push(ZR); // Result slot.
2315 __ Push(T0); // Arg0: Receiver 2307 __ Push(T0); // Arg0: Receiver
2316 __ Push(S5); // Arg1: UnlinkedCall 2308 __ Push(S5); // Arg1: UnlinkedCall
2317 __ CallRuntime(kUnlinkedCallRuntimeEntry, 2); 2309 __ CallRuntime(kUnlinkedCallRuntimeEntry, 2);
2318 __ Drop(2); 2310 __ Drop(2);
2319 __ Pop(S5); // result = IC 2311 __ Pop(S5); // result = IC
2320 2312
2321 __ Pop(T0); // Restore receiver. 2313 __ Pop(T0); // Restore receiver.
2322 __ LeaveStubFrame(); 2314 __ LeaveStubFrame();
2323 2315
2324 __ lw(CODE_REG, Address(THR, Thread::ic_lookup_through_code_stub_offset())); 2316 __ lw(CODE_REG, Address(THR, Thread::ic_lookup_through_code_stub_offset()));
2325 __ lw(T1, FieldAddress(CODE_REG, Code::checked_entry_point_offset())); 2317 __ lw(T1, FieldAddress(CODE_REG, Code::checked_entry_point_offset()));
2326 __ jr(T1); 2318 __ jr(T1);
2327 } 2319 }
2328 2320
2329 2321
2330 // Called from switchable IC calls. 2322 // Called from switchable IC calls.
2331 // T0: receiver 2323 // T0: receiver
2332 // S5: SingleTargetCache 2324 // S5: SingleTargetCache
2333 // Passed to target: 2325 // Passed to target:
2334 // CODE_REG: target Code object 2326 // CODE_REG: target Code object
2335 void StubCode::GenerateSingleTargetCallStub(Assembler* assembler) { 2327 void StubCode::GenerateSingleTargetCallStub(Assembler* assembler) {
2336 __ NoMonomorphicCheckedEntry();
2337
2338 Label miss; 2328 Label miss;
2339
2340 __ LoadClassIdMayBeSmi(T1, T0); 2329 __ LoadClassIdMayBeSmi(T1, T0);
2341 __ lhu(T2, FieldAddress(S5, SingleTargetCache::lower_limit_offset())); 2330 __ lhu(T2, FieldAddress(S5, SingleTargetCache::lower_limit_offset()));
2342 __ lhu(T3, FieldAddress(S5, SingleTargetCache::upper_limit_offset())); 2331 __ lhu(T3, FieldAddress(S5, SingleTargetCache::upper_limit_offset()));
2343 2332
2344 __ BranchUnsignedLess(T1, T2, &miss); 2333 __ BranchUnsignedLess(T1, T2, &miss);
2345 __ BranchUnsignedGreater(T1, T3, &miss); 2334 __ BranchUnsignedGreater(T1, T3, &miss);
2346 2335
2347 __ lw(T1, FieldAddress(S5, SingleTargetCache::entry_point_offset())); 2336 __ lw(T1, FieldAddress(S5, SingleTargetCache::entry_point_offset()));
2348 __ lw(CODE_REG, FieldAddress(S5, SingleTargetCache::target_offset())); 2337 __ lw(CODE_REG, FieldAddress(S5, SingleTargetCache::target_offset()));
2349 __ jr(T1); 2338 __ jr(T1);
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
2389 } 2378 }
2390 2379
2391 2380
2392 void StubCode::GenerateFrameAwaitingMaterializationStub(Assembler* assembler) { 2381 void StubCode::GenerateFrameAwaitingMaterializationStub(Assembler* assembler) {
2393 __ break_(0); 2382 __ break_(0);
2394 } 2383 }
2395 2384
2396 } // namespace dart 2385 } // namespace dart
2397 2386
2398 #endif // defined TARGET_ARCH_MIPS 2387 #endif // defined TARGET_ARCH_MIPS
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