Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(450)

Side by Side Diff: base/cpu.cc

Issue 2458333002: Add popcnt support for pnacl (Closed)
Patch Set: Add popcnt test for clang Created 4 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « base/cpu.h ('k') | base/cpu_unittest.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 2012 The Chromium Authors. All rights reserved. 1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "base/cpu.h" 5 #include "base/cpu.h"
6 6
7 #include <limits.h> 7 #include <limits.h>
8 #include <stddef.h> 8 #include <stddef.h>
9 #include <stdint.h> 9 #include <stdint.h>
10 #include <string.h> 10 #include <string.h>
(...skipping 25 matching lines...) Expand all
36 stepping_(0), 36 stepping_(0),
37 ext_model_(0), 37 ext_model_(0),
38 ext_family_(0), 38 ext_family_(0),
39 has_mmx_(false), 39 has_mmx_(false),
40 has_sse_(false), 40 has_sse_(false),
41 has_sse2_(false), 41 has_sse2_(false),
42 has_sse3_(false), 42 has_sse3_(false),
43 has_ssse3_(false), 43 has_ssse3_(false),
44 has_sse41_(false), 44 has_sse41_(false),
45 has_sse42_(false), 45 has_sse42_(false),
46 has_popcnt_(false),
46 has_avx_(false), 47 has_avx_(false),
47 has_avx2_(false), 48 has_avx2_(false),
48 has_aesni_(false), 49 has_aesni_(false),
49 has_non_stop_time_stamp_counter_(false), 50 has_non_stop_time_stamp_counter_(false),
50 cpu_vendor_("unknown") { 51 cpu_vendor_("unknown") {
51 Initialize(); 52 Initialize();
52 } 53 }
53 54
54 namespace { 55 namespace {
55 56
(...skipping 114 matching lines...) Expand 10 before | Expand all | Expand 10 after
170 type_ = (cpu_info[0] >> 12) & 0x3; 171 type_ = (cpu_info[0] >> 12) & 0x3;
171 ext_model_ = (cpu_info[0] >> 16) & 0xf; 172 ext_model_ = (cpu_info[0] >> 16) & 0xf;
172 ext_family_ = (cpu_info[0] >> 20) & 0xff; 173 ext_family_ = (cpu_info[0] >> 20) & 0xff;
173 has_mmx_ = (cpu_info[3] & 0x00800000) != 0; 174 has_mmx_ = (cpu_info[3] & 0x00800000) != 0;
174 has_sse_ = (cpu_info[3] & 0x02000000) != 0; 175 has_sse_ = (cpu_info[3] & 0x02000000) != 0;
175 has_sse2_ = (cpu_info[3] & 0x04000000) != 0; 176 has_sse2_ = (cpu_info[3] & 0x04000000) != 0;
176 has_sse3_ = (cpu_info[2] & 0x00000001) != 0; 177 has_sse3_ = (cpu_info[2] & 0x00000001) != 0;
177 has_ssse3_ = (cpu_info[2] & 0x00000200) != 0; 178 has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;
178 has_sse41_ = (cpu_info[2] & 0x00080000) != 0; 179 has_sse41_ = (cpu_info[2] & 0x00080000) != 0;
179 has_sse42_ = (cpu_info[2] & 0x00100000) != 0; 180 has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
181 has_popcnt_ = (cpu_info[2] & 0x00800000) != 0;
182
180 // AVX instructions will generate an illegal instruction exception unless 183 // AVX instructions will generate an illegal instruction exception unless
181 // a) they are supported by the CPU, 184 // a) they are supported by the CPU,
182 // b) XSAVE is supported by the CPU and 185 // b) XSAVE is supported by the CPU and
183 // c) XSAVE is enabled by the kernel. 186 // c) XSAVE is enabled by the kernel.
184 // See http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled 187 // See http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
185 // 188 //
186 // In addition, we have observed some crashes with the xgetbv instruction 189 // In addition, we have observed some crashes with the xgetbv instruction
187 // even after following Intel's example code. (See crbug.com/375968.) 190 // even after following Intel's example code. (See crbug.com/375968.)
188 // Because of that, we also test the XSAVE bit because its description in 191 // Because of that, we also test the XSAVE bit because its description in
189 // the CPUID documentation suggests that it signals xgetbv support. 192 // the CPUID documentation suggests that it signals xgetbv support.
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
229 if (has_sse42()) return SSE42; 232 if (has_sse42()) return SSE42;
230 if (has_sse41()) return SSE41; 233 if (has_sse41()) return SSE41;
231 if (has_ssse3()) return SSSE3; 234 if (has_ssse3()) return SSSE3;
232 if (has_sse3()) return SSE3; 235 if (has_sse3()) return SSE3;
233 if (has_sse2()) return SSE2; 236 if (has_sse2()) return SSE2;
234 if (has_sse()) return SSE; 237 if (has_sse()) return SSE;
235 return PENTIUM; 238 return PENTIUM;
236 } 239 }
237 240
238 } // namespace base 241 } // namespace base
OLDNEW
« no previous file with comments | « base/cpu.h ('k') | base/cpu_unittest.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698