[Turbofan] SIMD tests for Int32x4Add, Sub, ReplaceLane.

src/compiler/x64/code-generator-x64.cc

Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc
index 0c2412fc5cfeaf7863f3dbe4491c50386afdf66c..fac54d7a3a6768efe4a3eb8cf6d5bcbf0b6ba05f 100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -2122,6 +2122,32 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Pextrd(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
       break;
     }
+    case kX64Int32x4ReplaceLane: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      if (instr->InputAt(2)->IsRegister()) {
+        __ Pinsrd(i.InputSimd128Register(0), i.InputRegister(2),
+                  i.InputInt8(1));
+      } else {
+        __ Pinsrd(i.InputSimd128Register(0), i.InputOperand(2), i.InputInt8(1));
+      }
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
+    case kX64Int32x4Add: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      __ paddd(i.InputSimd128Register(0), i.InputSimd128Register(1));
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
+    case kX64Int32x4Sub: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      __ psubd(i.InputSimd128Register(0), i.InputSimd128Register(1));
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movsxbl);
       break;