Support unaligned integer loads on ARM and MIPS.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2824 matching lines @@
 
 void Assembler::LoadMultipleDFromOffset(DRegister first,
                                         intptr_t count,
                                         Register base,
                                         int32_t offset) {
   ASSERT(base != IP);
   AddImmediate(IP, base, offset);
   vldmd(IA, IP, first, count);
 }
 
+
 void Assembler::StoreMultipleDToOffset(DRegister first,
                                        intptr_t count,
                                        Register base,
                                        int32_t offset) {
   ASSERT(base != IP);
   AddImmediate(IP, base, offset);
   vstmd(IA, IP, first, count);
 }
 
 
@@ skipping 619 matching lines @@
   if (Address::CanHoldImmediateOffset(is_load, cid, offset)) {
     return Address(array, static_cast<int32_t>(offset));
   } else {
     ASSERT(Address::CanHoldImmediateOffset(is_load, cid, offset - offset_base));
     AddImmediate(temp, array, static_cast<int32_t>(offset_base));
     return Address(temp, static_cast<int32_t>(offset - offset_base));
   }
 }
 
 
+void Assembler::LoadElementAddressForIntIndex(Register address,
+                                              bool is_load,
+                                              bool is_external,
+                                              intptr_t cid,
+                                              intptr_t index_scale,
+                                              Register array,
+                                              intptr_t index) {
+  const int64_t offset_base =
+      (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
+  const int64_t offset = offset_base +
+      static_cast<int64_t>(index) * index_scale;
+  ASSERT(Utils::IsInt(32, offset));
+  AddImmediate(address, array, offset);
+}
+
+
 Address Assembler::ElementAddressForRegIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              Register index) {
   // Note that index is expected smi-tagged, (i.e, LSL 1) for all arrays.
   const intptr_t shift = Utils::ShiftForPowerOfTwo(index_scale) - kSmiTagShift;
   int32_t offset =
       is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag);
@@ skipping 24 matching lines @@
       (!is_load && !Address::CanHoldStoreOffset(size,
                                                 offset,
                                                 &offset_mask))) {
     AddImmediate(base, offset & ~offset_mask);
     offset = offset & offset_mask;
   }
   return Address(base, offset);
 }
 
 
+void Assembler::LoadElementAddressForRegIndex(Register address,
+                                              bool is_load,
+                                              bool is_external,
+                                              intptr_t cid,
+                                              intptr_t index_scale,
+                                              Register array,
+                                              Register index) {
+  // Note that index is expected smi-tagged, (i.e, LSL 1) for all arrays.
+  const intptr_t shift = Utils::ShiftForPowerOfTwo(index_scale) - kSmiTagShift;
+  int32_t offset =
+      is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag);
+  if (shift < 0) {
+    ASSERT(shift == -1);
+    add(address, array, Operand(index, ASR, 1));
+  } else {
+    add(address, array, Operand(index, LSL, shift));
+  }
+  if (offset != 0) {
+    AddImmediate(address, offset);
+  }
+}
+
+
+void Assembler::LoadHalfWordUnaligned(Register dst,
+                                      Register addr,
+                                      Register tmp) {
+  ASSERT(dst != addr);
+  ldrb(dst, Address(addr, 0));
+  ldrsb(tmp, Address(addr, 1));
+  orr(dst, dst, Operand(tmp, LSL, 8));
+}
+
+
+void Assembler::LoadHalfWordUnsignedUnaligned(Register dst,
+                                              Register addr,
+                                              Register tmp) {
+  ASSERT(dst != addr);
+  ldrb(dst, Address(addr, 0));
+  ldrb(tmp, Address(addr, 1));
+  orr(dst, dst, Operand(tmp, LSL, 8));
+}
+
+
+void Assembler::StoreHalfWordUnaligned(Register src,
+                                       Register addr,
+                                       Register tmp) {
+  strb(src, Address(addr, 0));
+  Lsr(tmp, src, Operand(8));
+  strb(tmp, Address(addr, 1));
+}
+
+
+void Assembler::LoadWordUnaligned(Register dst, Register addr, Register tmp) {
+  ASSERT(dst != addr);
+  ldrb(dst, Address(addr, 0));
+  ldrb(tmp, Address(addr, 1));
+  orr(dst, dst, Operand(tmp, LSL, 8));
+  ldrb(tmp, Address(addr, 2));
+  orr(dst, dst, Operand(tmp, LSL, 16));
+  ldrb(tmp, Address(addr, 3));
+  orr(dst, dst, Operand(tmp, LSL, 24));
+}
+
+
+void Assembler::StoreWordUnaligned(Register src, Register addr, Register tmp) {
+  strb(src, Address(addr, 0));
+  Lsr(tmp, src, Operand(8));
+  strb(tmp, Address(addr, 1));
+  Lsr(tmp, src, Operand(16));
+  strb(tmp, Address(addr, 2));
+  Lsr(tmp, src, Operand(24));
+  strb(tmp, Address(addr, 3));
+}
+
+
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
   "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
 };
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
 #if defined(VFPv3_D32)
   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
 #endif
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM