Subzero, MIPS32: Enable MIPS support in lit tests

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 102 matching lines @@
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
 ; MIPS32-LABEL: pass64BitArg
+; MIPS32-O2:    sw      a3,{{.*}}(sp)
+; MIPS32-O2:    sw      a2,{{.*}}(sp)
+; MIPS32-O2:    li      a2,123
+; MIPS32-O2:    jal     {{.*}}  ignore64BitArgNoInline
+; MIPS32-O2:    nop
+; MIPS32-O2:    move    s0,v0
+; MIPS32-O2:    sw      s3,{{.*}}(sp)
+; MIPS32-O2:    sw      s2,{{.*}}(sp)
+; MIPS32-O2:    lw      a0,{{.*}}(sp)
+; MIPS32-O2:    move    a1,s1
+; MIPS32-O2:    li      a2,123
+; MIPS32-O2:    jal     {{.*}}  ignore64BitArgNoInline
+; MIPS32-O2:    nop
+; MIPS32-O2:    move    s1,v0
+; MIPS32-O2:    sw      s7,{{.*}}(sp)
+; MIPS32-O2:    sw      s6,{{.*}}(sp)
+; MIPS32-O2:    move    a0,s4
+; MIPS32-O2:    move    a1,s5
+; MIPS32-O2:    li      a2,123
+; MIPS32-O2:    jal     {{.*}}  ignore64BitArgNoInline
+; MIPS32-O2:    nop
 
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -2401053092306725256)
   ret i32 %call
 }
 ; CHECK-LABEL: pass64BitConstArg
@@ skipping 24 matching lines @@
 ; ARM32:      movt    [[REG1]], {{.*}}     ; 0xdead
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
 ; ARM32:      movt    [[REG2]], {{.*}}     ; 0x1234
 ; ARM32:      str     [[REG1]], [sp, #4]
 ; ARM32:      str     [[REG2]], [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
+; MIPS32-LABEL: pass64BitConstArg
+; MIPS32-O2:    lui     [[REG:.*]],0xdead
+; MIPS32-O2:    ori     [[REG1:.*]],[[REG]],0xbeef
+; MIPS32-O2:    lui     [[REG:.*]],0x1234
+; MIPS32-O2:    ori     [[REG2:.*]],[[REG]],0x5678
+; MIPS32-O2:    sw      [[REG1]],{{.*}}(sp)
+; MIPS32-O2:    sw      [[REG2]],{{.*}}(sp)
+; MIPS32-O2:    move    a0,a2
+; MIPS32-O2:    move    a1,a3
+; MIPS32-O2:    li      a2,123
+; MIPS32-O2:    jal     {{.*}}  ignore64BitArgNoInline
+
 define internal i32 @pass64BitUndefArg() {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
   ret i32 %call
 }
 ; CHECK-LABEL: pass64BitUndefArg
 ; CHECK: sub esp
 ; CHECK: mov DWORD PTR{{.*}},0x7b
 ; CHECK: mov DWORD PTR{{.*}},0x0
 ; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
@@ skipping 382 matching lines @@
 ;
 ; OPTM1-LABEL: shl64BitSignedTrunc
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
 ; ARM32-LABEL: shl64BitSignedTrunc
 ; ARM32: lsl r
 
+; MIPS32-LABEL: shl64BitSignedTrunc
+; MIPS32-O2:    sllv
+; MIPS32-O2:    andi    {{.*}},0x20
+; MIPS32-O2:    movn
+
 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitUnsigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
@@ skipping 89 matching lines @@
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: shr64BitSignedTrunc
 ; ARM32: lsr
 ; ARM32: rsb
 ; ARM32: orr
 ; ARM32: sub
 ; ARM32: cmp
 ; ARM32: asrge
 
+; MIPS32-LABEL: shr64BitSignedTrunc
+; MIPS32-O2:    srlv
+; MIPS32-O2:    nor
+; MIPS32-O2:    sll
+; MIPS32-O2:    sllv
+; MIPS32-O2:    or
+; MIPS32-O2:    srav
+; MIPS32-O2:    andi    {{.*}},0x20
+; MIPS32-O2:    movn
+
 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitUnsigned
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
@@ skipping 44 matching lines @@
 ; OPTM1: je
 
 ; ARM32-LABEL: shr64BitUnsignedTrunc
 ; ARM32: lsr
 ; ARM32: rsb
 ; ARM32: orr
 ; ARM32: sub
 ; ARM32: cmp
 ; ARM32: lsrge
 
+; MIPS32-LABEL: shr64BitUnsignedTrunc
+; MIPS32-O2:    srlv
+; MIPS32-O2:    nor
+; MIPS32-O2:    sll
+; MIPS32-O2:    sllv
+; MIPS32-O2:    or
+; MIPS32-O2:    srlv
+; MIPS32-O2:    andi
+; MIPS32-O2:    movn
+
 define internal i64 @and64BitSigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitSigned
 ; CHECK: and
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitSigned
@@ skipping 1414 matching lines @@
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
 ;
 ; OPTM1-LABEL: load64
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}]
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}+0x4]
 
 ; ARM32-LABEL: load64
 ; ARM32: ldr r{{.*}}, [r[[REG:.*]]]
 ; ARM32: ldr r{{.*}}, [r[[REG]], #4]
 
+; MIPS32-LABEL: load64
+; MIPS32-O2:    lw      {{.*}},0([[REG:.*]])
+; MIPS32-O2:    lw      [[REG]],4([[REG]])
+
 define internal void @store64(i32 %a, i64 %value) {
 entry:
   %__2 = inttoptr i32 %a to i64*
   store i64 %value, i64* %__2, align 1
   ret void
 }
 ; CHECK-LABEL: store64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],
 ; CHECK: mov DWORD PTR [e[[REGISTER]]],
 ;
 ; OPTM1-LABEL: store64
 ; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],
 ; OPTM1: mov DWORD PTR [e[[REGISTER]]],
 
 ; ARM32-LABEL: store64
 ; ARM32: str r{{.*}}, [r[[REG:.*]], #4]
 ; ARM32: str r{{.*}}, [r[[REG]]]
 
+; MIPS32-LABEL: store64
+; MIPS32-O2:    sw      {{.*}},4([[REG:.*]])
+; MIPS32-O2:    sw      {{.*}},0([[REG]])
+
 define internal void @store64Const(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   store i64 -2401053092306725256, i64* %__1, align 1
   ret void
 }
 ; CHECK-LABEL: store64Const
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],0xdeadbeef
 ; CHECK: mov DWORD PTR [e[[REGISTER]]],0x12345678
 ;
 ; OPTM1-LABEL: store64Const
 ; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],0xdeadbeef
 ; OPTM1: mov DWORD PTR [e[[REGISTER]]],0x12345678
 
 ; ARM32-LABEL: store64Const
 ; ARM32: movw [[REG1:.*]], #48879 ; 0xbeef
 ; ARM32: movt [[REG1:.*]], #57005 ; 0xdead
 ; ARM32: movw [[REG2:.*]], #22136 ; 0x5678
 ; ARM32: movt [[REG2:.*]], #4660  ; 0x1234
 ; ARM32: str [[REG1]], [r[[REG:.*]], #4]
 ; ARM32: str [[REG2]], [r[[REG]]]
 
+; MIPS32-LABEL: store64Const
+; MIPS32-O2:    lui     [[REG1:.*]],0xdead
+; MIPS32-O2:    ori     [[REG1:.*]],[[REG1]],0xbeef
+; MIPS32-O2:    lui     [[REG2:.*]],0x1234
+; MIPS32-O2:    ori     [[REG2:.*]],[[REG2]],0x5678
+; MIPS32-O2:    sw      [[REG1]],4([[REG:.*]])
+; MIPS32-O2:    sw      [[REG2]],0([[REG]])
+
 define internal i64 @select64VarVar(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 ; CHECK-LABEL: select64VarVar
 ; CHECK: mov
 ; CHECK: mov
 ; CHECK: cmp
@@ skipping 233 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }