Adds Runtime call stub and Dart entry stub to ARM64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 360 matching lines @@
   static void InitializeMemoryWithBreakpoints(uword data, intptr_t length);
 
   void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
 
   const Code::Comments& GetCodeComments() const;
 
   static const char* RegisterName(Register reg);
 
   static const char* FpuRegisterName(FpuRegister reg);
 
+  void SetPrologueOffset() {
+    if (prologue_offset_ == -1) {
+      prologue_offset_ = CodeSize();
+    }
+  }
+
+  void ReserveAlignedFrameSpace(intptr_t frame_space);
+
   // TODO(zra): Make sure this is right.
   // Instruction pattern from entrypoint is used in Dart frame prologs
   // to set up the frame and save a PC which can be used to figure out the
   // RawInstruction object corresponding to the code running in the frame.
   static const intptr_t kEntryPointToPcMarkerOffset = 0;
 
   // Emit data (e.g encoded instruction or immediate) in instruction stream.
   void Emit(int32_t value);
 
   // On some other platforms, we draw a distinction between safe and unsafe
@@ skipping 203 matching lines @@
     ldr(PP, Address(SP, 1 * kWordSize, Address::PostIndex));
     sub(PP, PP, Operand(kHeapObjectTag));
   }
   void tst(Register rn, Operand o) {
     ands(ZR, rn, o);
   }
   void tsti(Register rn, uint64_t imm) {
     andis(ZR, rn, imm);
   }
 
+  void SmiUntag(Register reg) {
+    add(reg, ZR, Operand(reg, ASR, kSmiTagSize));
+  }
+
   // Branching to ExternalLabels.
   void Branch(const ExternalLabel* label) {
     LoadExternalLabel(TMP, label, kPatchable, PP);
     br(TMP);
   }
 
   void BranchPatchable(const ExternalLabel* label) {
     LoadPatchableImmediate(TMP, label->address());
     br(TMP);
   }
 
   void BranchLink(const ExternalLabel* label, Register pp) {
     if (Isolate::Current() == Dart::vm_isolate()) {
       LoadImmediate(TMP, label->address(), kNoRegister);
       blr(TMP);
     } else {
       LoadExternalLabel(TMP, label, kNotPatchable, pp);
       blr(TMP);
     }
   }
 
   void BranchLinkPatchable(const ExternalLabel* label) {
     LoadExternalLabel(TMP, label, kPatchable, PP);
     blr(TMP);
   }
 
+  // Macros accepting a pp Register argument may attempt to load values from
+  // the object pool when possible. Unless you are sure that the untagged object
+  // pool pointer is in another register, or that it is not available at all,
+  // PP should be passed for pp.
+  void AddImmediate(Register dest, Register rn, int64_t imm, Register pp);
+  void CompareImmediate(Register rn, int64_t imm, Register pp);
+  void LoadFromOffset(Register dest, Register base, int32_t offset);
+  void LoadFieldFromOffset(Register dest, Register base, int32_t offset) {
+    LoadFromOffset(dest, base, offset - kHeapObjectTag);
+  }
+  void StoreToOffset(Register dest, Register base, int32_t offset);
+  void StoreFieldToOffset(Register dest, Register base, int32_t offset) {
+    StoreToOffset(dest, base, offset - kHeapObjectTag);
+  }
+
   // Object pool, loading from pool, etc.
-  void LoadPoolPointer(Register pp) {
-    const intptr_t object_pool_pc_dist =
-      Instructions::HeaderSize() - Instructions::object_pool_offset() +
-      CodeSize();
-    // PP <- Read(PC - object_pool_pc_dist).
-    ldr(pp, Address::PC(-object_pool_pc_dist));
-
-    // When in the PP register, the pool pointer is untagged. When we
-    // push it on the stack with PushPP it is tagged again. PopPP then untags
-    // when restoring from the stack. This will make loading from the object
-    // pool only one instruction for the first 4096 entries. Otherwise, because
-    // the offset wouldn't be aligned, it would always be at least two
-    // instructions.
-    sub(pp, pp, Operand(kHeapObjectTag));
-  }
+  void LoadPoolPointer(Register pp);
 
   enum Patchability {
     kPatchable,
     kNotPatchable,
   };
 
   void LoadWordFromPoolOffset(Register dst, Register pp, uint32_t offset);
   intptr_t FindExternalLabel(const ExternalLabel* label,
                              Patchability patchable);
   intptr_t FindObject(const Object& obj, Patchability patchable);
   intptr_t FindImmediate(int64_t imm);
   bool CanLoadObjectFromPool(const Object& object);
   bool CanLoadImmediateFromPool(int64_t imm, Register pp);
   void LoadExternalLabel(Register dst, const ExternalLabel* label,
                          Patchability patchable, Register pp);
   void LoadObject(Register dst, const Object& obj, Register pp);
   void LoadDecodableImmediate(Register reg, int64_t imm, Register pp);
   void LoadPatchableImmediate(Register reg, int64_t imm);
   void LoadImmediate(Register reg, int64_t imm, Register pp);
 
+  void PushObject(const Object& object, Register pp) {
+    LoadObject(TMP, object, pp);
+    Push(TMP);
+  }
+
+  void EnterFrame(intptr_t frame_size);
+  void LeaveFrame();
+
+  void EnterDartFrame(intptr_t frame_size);
+  void LeaveDartFrame();
+
+  void CallRuntime(const RuntimeEntry& entry, intptr_t argument_count);
+
  private:
   AssemblerBuffer buffer_;  // Contains position independent code.
 
   // Objects and patchable jump targets.
   GrowableObjectArray& object_pool_;
 
   // Patchability of pool entries.
   GrowableArray<Patchability> patchable_pool_entries_;
 
   // Pair type parameter for DirectChainedHashMap.
@@ skipping 147 matching lines @@
 
   int64_t DecodeImm19BranchOffset(int32_t instr) {
     const int32_t off = (((instr >> kImm19Shift) & kImm19Shift) << 13) >> 13;
     return static_cast<int64_t>(off);
   }
 
   void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
                             OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
+    ASSERT((rt != SP) && (rt != R31));
+    const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoded_offset = EncodeImm19BranchOffset(imm, 0);
     const int32_t encoding =
         op | size |
-        (static_cast<int32_t>(rt) << kRtShift) |
+        (static_cast<int32_t>(crt) << kRtShift) |
         encoded_offset;
     Emit(encoding);
   }
 
   void EmitConditionalBranch(ConditionalBranchOp op, Condition cond,
                              int64_t imm) {
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     const int32_t encoding =
         op |
         (static_cast<int32_t>(cond) << kCondShift) |
@@ skipping 14 matching lines @@
       EmitConditionalBranch(op, cond, dest);
     } else {
       const int64_t position = buffer_.Size();
       ASSERT(CanEncodeImm19BranchOffset(position));
       EmitConditionalBranch(op, cond, label->position_);
       label->LinkTo(position);
     }
   }
 
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
+    ASSERT((rn != SP) && (rn != R31));
+    const Register crn = ConcreteRegister(rn);
     const int32_t encoding =
-        op | (static_cast<int32_t>(rn) << kRnShift);
+        op | (static_cast<int32_t>(crn) << kRnShift);
     Emit(encoding);
   }
 
   void EmitExceptionGenOp(ExceptionGenOp op, uint16_t imm) {
     const int32_t encoding =
         op | (static_cast<int32_t>(imm) << kImm16Shift);
     Emit(encoding);
   }
 
   void EmitMoveWideOp(MoveWideOp op, Register rd, uint16_t imm, int hw_idx,
                       OperandSize sz) {
     ASSERT((hw_idx >= 0) && (hw_idx <= 3));
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(hw_idx) << kHWShift) |
         (static_cast<int32_t>(imm) << kImm16Shift);
     Emit(encoding);
   }
 
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
+    const Register crt = ConcreteRegister(rt);
     const int32_t size = Log2OperandSizeBytes(sz);
     const int32_t encoding =
         op | (size << kSzShift) |
-        (static_cast<int32_t>(rt) << kRtShift) |
+        (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitLoadRegLiteral(LoadRegLiteralOp op, Register rt, Address a,
                           OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord));
+    ASSERT((rt != SP) && (rt != R31));
+    const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B30 : 0;
     const int32_t encoding =
         op | size |
-        (static_cast<int32_t>(rt) << kRtShift) |
+        (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitPCRelOp(PCRelOp op, Register rd, int64_t imm) {
     ASSERT(Utils::IsInt(21, imm));
     ASSERT((rd != R31) && (rd != SP));
     const Register crd = ConcreteRegister(rd);
     const int32_t loimm = (imm & 0x3) << 29;
     const int32_t hiimm = ((imm >> 2) << kImm19Shift) & kImm19Mask;
@@ skipping 37 matching lines @@
     Emit(encoding);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_