Adds Runtime call stub and Dart entry stub to ARM64.

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 239 matching lines @@
       imm_s_fixed >>= 1;
       continue;
     }
 
     // 6. Otherwise, the value can't be encoded.
     return false;
   }
 }
 
 
+void Assembler::LoadPoolPointer(Register pp) {
+  const intptr_t object_pool_pc_dist =
+    Instructions::HeaderSize() - Instructions::object_pool_offset() +
+    CodeSize();
+  // PP <- Read(PC - object_pool_pc_dist).
+  ldr(pp, Address::PC(-object_pool_pc_dist));
+
+  // When in the PP register, the pool pointer is untagged. When we
+  // push it on the stack with PushPP it is tagged again. PopPP then untags
+  // when restoring from the stack. This will make loading from the object
+  // pool only one instruction for the first 4096 entries. Otherwise, because
+  // the offset wouldn't be aligned, it would always be at least two
+  // instructions.
+  sub(pp, pp, Operand(kHeapObjectTag));
+}
+
 void Assembler::LoadWordFromPoolOffset(Register dst, Register pp,
                                        uint32_t offset) {
   ASSERT(dst != pp);
   if (Address::CanHoldOffset(offset)) {
     ldr(dst, Address(pp, offset));
   } else {
     const uint16_t offset_low = Utils::Low16Bits(offset);
     const uint16_t offset_high = Utils::High16Bits(offset);
     movz(dst, offset_low, 0);
     if (offset_high != 0) {
@@ skipping 230 matching lines @@
     if (h3 != 0) {
       if (initialized) {
         movk(reg, h3, 3);
       } else {
         movz(reg, h3, 3);
       }
     }
   }
 }
 
+
+void Assembler::AddImmediate(
+    Register dest, Register rn, int64_t imm, Register pp) {
+  ASSERT(rn != TMP2);
+  Operand op;
+  if (Operand::CanHold(imm, kXRegSizeInBits, &op) == Operand::Immediate) {
+    add(dest, rn, op);
+  } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
+             Operand::Immediate) {
+    sub(dest, rn, op);
+  } else {
+    LoadImmediate(TMP2, imm, pp);
+    add(dest, rn, Operand(TMP2));
+  }
+}
+
+
+void Assembler::CompareImmediate(Register rn, int64_t imm, Register pp) {
+  ASSERT(rn != TMP2);
+  Operand op;
+  if (Operand::CanHold(imm, kXRegSizeInBits, &op) == Operand::Immediate) {
+    cmp(rn, op);
+  } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
+             Operand::Immediate) {
+    cmn(rn, op);
+  } else {
+    LoadImmediate(TMP2, imm, pp);
+    cmp(rn, Operand(TMP2));
+  }
+}
+
+
+void Assembler::LoadFromOffset(Register dest, Register base, int32_t offset) {
+  ASSERT(base != TMP2);
+  if (Address::CanHoldOffset(offset)) {
+    ldr(dest, Address(base, offset));
+  } else if (Address::CanHoldOffset(offset, Address::PreIndex)) {
+    mov(TMP2, base);
+    ldr(dest, Address(TMP2, offset, Address::PreIndex));
+  } else {
+    // Since offset is 32-bits, it won't be loaded from the pool.
+    AddImmediate(TMP2, base, offset, kNoRegister);
+    ldr(dest, Address(TMP2));
+  }
+}
+
+
+void Assembler::StoreToOffset(Register src, Register base, int32_t offset) {
+  ASSERT(src != TMP2);
+  ASSERT(base != TMP2);
+  if (Address::CanHoldOffset(offset)) {
+    str(src, Address(base, offset));
+  } else if (Address::CanHoldOffset(offset, Address::PreIndex)) {
+    mov(TMP2, base);
+    str(src, Address(TMP2, offset, Address::PreIndex));
+  } else {
+    // Since offset is 32-bits, it won't be loaded from the pool.
+    AddImmediate(TMP2, base, offset, kNoRegister);
+    str(src, Address(TMP2));
+  }
+}
+
+
+void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
+  // Reserve space for arguments and align frame before entering
+  // the C++ world.
+  AddImmediate(SP, SP, -frame_space, kNoRegister);
+  if (OS::ActivationFrameAlignment() > 1) {
+    mov(TMP, SP);  // SP can't be register operand of andi.
+    andi(SP, TMP, ~(OS::ActivationFrameAlignment() - 1));
+  }
+}
+
+
+void Assembler::EnterDartFrame(intptr_t frame_size) {
+  adr(TMP, 0);  // TMP gets PC of this instruction.
+  Push(TMP);  // Save PC Marker.
+  Push(LR);  // Save return address.
+  Push(FP);  // Save FP.
+  PushPP();  // Save PP.
+
+  // Set FP to saved previous FP.
+  add(FP, SP, Operand(1 * kWordSize));
+
+  // Load the pool pointer.
+  LoadPoolPointer(PP);
+
+  // Reserve space.
+  sub(SP, SP, Operand(frame_size));
+}
+
+
+void Assembler::LeaveDartFrame() {
+  sub(SP, FP, Operand(1 * kWordSize));
+  PopPP();  // Restore pool pointer.
+  Pop(FP);  // Restore frame pointer.
+  Pop(LR);  // Restore return address.
+  Pop(TMP);  // Pop PC marker, and restore SP.
+}
+
+
+void Assembler::CallRuntime(const RuntimeEntry& entry,
+                            intptr_t argument_count) {
+  entry.Call(this, argument_count);
+}
+
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64