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1 // | 1 // |
2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
3 // | 3 // |
4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
6 // | 6 // |
7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
8 /// | 8 /// |
9 /// \file | 9 /// \file |
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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4055 lowerAssign(Assign); | 4055 lowerAssign(Assign); |
4056 return; | 4056 return; |
4057 } | 4057 } |
4058 llvm::report_fatal_error("InsertElement requires a constant index"); | 4058 llvm::report_fatal_error("InsertElement requires a constant index"); |
4059 } | 4059 } |
4060 | 4060 |
4061 void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) { | 4061 void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) { |
4062 Variable *Dest = Instr->getDest(); | 4062 Variable *Dest = Instr->getDest(); |
4063 Type DestTy = (Dest == nullptr) ? IceType_void : Dest->getType(); | 4063 Type DestTy = (Dest == nullptr) ? IceType_void : Dest->getType(); |
4064 switch (Instr->getIntrinsicInfo().ID) { | 4064 switch (Instr->getIntrinsicInfo().ID) { |
4065 default: | |
4066 llvm::report_fatal_error("Unexpected intrinsic"); | |
4067 return; | |
4068 case Intrinsics::AtomicCmpxchg: { | 4065 case Intrinsics::AtomicCmpxchg: { |
4069 UnimplementedLoweringError(this, Instr); | 4066 UnimplementedLoweringError(this, Instr); |
4070 return; | 4067 return; |
4071 } | 4068 } |
4072 case Intrinsics::AtomicFence: | 4069 case Intrinsics::AtomicFence: |
4073 UnimplementedLoweringError(this, Instr); | 4070 UnimplementedLoweringError(this, Instr); |
4074 return; | 4071 return; |
4075 case Intrinsics::AtomicFenceAll: | 4072 case Intrinsics::AtomicFenceAll: |
4076 // NOTE: FenceAll should prevent and load/store from being moved across the | 4073 // NOTE: FenceAll should prevent and load/store from being moved across the |
4077 // fence (both atomic and non-atomic). The InstMIPS32Mfence instruction is | 4074 // fence (both atomic and non-atomic). The InstMIPS32Mfence instruction is |
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4356 return; | 4353 return; |
4357 } | 4354 } |
4358 case Intrinsics::LoadSubVector: { | 4355 case Intrinsics::LoadSubVector: { |
4359 UnimplementedLoweringError(this, Instr); // Not required for PNaCl | 4356 UnimplementedLoweringError(this, Instr); // Not required for PNaCl |
4360 return; | 4357 return; |
4361 } | 4358 } |
4362 case Intrinsics::StoreSubVector: { | 4359 case Intrinsics::StoreSubVector: { |
4363 UnimplementedLoweringError(this, Instr); // Not required for PNaCl | 4360 UnimplementedLoweringError(this, Instr); // Not required for PNaCl |
4364 return; | 4361 return; |
4365 } | 4362 } |
4366 case Intrinsics::UnknownIntrinsic: | 4363 default: // UnknownIntrinsic |
4367 Func->setError("Should not be lowering UnknownIntrinsic"); | 4364 Func->setError("Unexpected intrinsic"); |
4368 return; | 4365 return; |
4369 } | 4366 } |
4370 return; | 4367 return; |
4371 } | 4368 } |
4372 | 4369 |
4373 void TargetMIPS32::lowerLoad(const InstLoad *Instr) { | 4370 void TargetMIPS32::lowerLoad(const InstLoad *Instr) { |
4374 // A Load instruction can be treated the same as an Assign instruction, after | 4371 // A Load instruction can be treated the same as an Assign instruction, after |
4375 // the source operand is transformed into an OperandMIPS32Mem operand. | 4372 // the source operand is transformed into an OperandMIPS32Mem operand. |
4376 Type Ty = Instr->getDest()->getType(); | 4373 Type Ty = Instr->getDest()->getType(); |
4377 Operand *Src0 = formMemoryOperand(Instr->getSourceAddress(), Ty); | 4374 Operand *Src0 = formMemoryOperand(Instr->getSourceAddress(), Ty); |
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5245 Str << "\t.set\t" | 5242 Str << "\t.set\t" |
5246 << "nomips16\n"; | 5243 << "nomips16\n"; |
5247 } | 5244 } |
5248 | 5245 |
5249 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 5246 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
5250 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 5247 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
5251 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 5248 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
5252 | 5249 |
5253 } // end of namespace MIPS32 | 5250 } // end of namespace MIPS32 |
5254 } // end of namespace Ice | 5251 } // end of namespace Ice |
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