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Side by Side Diff: runtime/vm/constants_dbc.h

Issue 2433813002: Reland "Add DoubleTestOp instruction" (Closed)
Patch Set: Created 4 years, 2 months ago
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1 // Copyright (c) 2016, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2016, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_CONSTANTS_DBC_H_ 5 #ifndef VM_CONSTANTS_DBC_H_
6 #define VM_CONSTANTS_DBC_H_ 6 #define VM_CONSTANTS_DBC_H_
7 7
8 #include "platform/globals.h" 8 #include "platform/globals.h"
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 #include "platform/utils.h" 10 #include "platform/utils.h"
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223 // - DTruncate, DFloor, DCeil rA, rD 223 // - DTruncate, DFloor, DCeil rA, rD
224 // 224 //
225 // Applies trunc(), floor(), or ceil() to the unboxed double in FP[rD], and 225 // Applies trunc(), floor(), or ceil() to the unboxed double in FP[rD], and
226 // stores the result in FP[rA]. 226 // stores the result in FP[rA].
227 // 227 //
228 // - DoubleToFloat, FloatToDouble rA, rD 228 // - DoubleToFloat, FloatToDouble rA, rD
229 // 229 //
230 // Convert the unboxed float or double in FP[rD] as indicated, and store the 230 // Convert the unboxed float or double in FP[rD] as indicated, and store the
231 // result in FP[rA]. 231 // result in FP[rA].
232 // 232 //
233 // - DoubleIsNaN rA, rD
234 //
235 // If the unboxed double in FP[rD] is a NaN, then writes Bool::True().raw()
236 // into FP[rA], and Bool::False().raw() otherwise.
237 //
238 // - DoubleIsInfinite rA, rD
239 //
240 // If the unboxed double in FP[rD] is + or - infinity, then
241 // writes Bool::True().raw() into FP[rA], and Bool::False().raw() otherwise.
242 //
233 // - BitOr, BitAnd, BitXor rA, rB, rC 243 // - BitOr, BitAnd, BitXor rA, rB, rC
234 // 244 //
235 // FP[rA] <- FP[rB] op FP[rC]. These instructions expect their operands to be 245 // FP[rA] <- FP[rB] op FP[rC]. These instructions expect their operands to be
236 // Smis, but don't check that they are. 246 // Smis, but don't check that they are.
237 // 247 //
238 // - BitNot rA, rD 248 // - BitNot rA, rD
239 // 249 //
240 // FP[rA] <- ~FP[rD]. As above, assumes FP[rD] is a Smi. 250 // FP[rA] <- ~FP[rD]. As above, assumes FP[rD] is a Smi.
241 // 251 //
242 // - WriteIntoDouble rA, rD 252 // - WriteIntoDouble rA, rD
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712 V(DMax, A_B_C, reg, reg, reg) \ 722 V(DMax, A_B_C, reg, reg, reg) \
713 V(DCos, A_D, reg, reg, ___) \ 723 V(DCos, A_D, reg, reg, ___) \
714 V(DSin, A_D, reg, reg, ___) \ 724 V(DSin, A_D, reg, reg, ___) \
715 V(DPow, A_B_C, reg, reg, reg) \ 725 V(DPow, A_B_C, reg, reg, reg) \
716 V(DMod, A_B_C, reg, reg, reg) \ 726 V(DMod, A_B_C, reg, reg, reg) \
717 V(DTruncate, A_D, reg, reg, ___) \ 727 V(DTruncate, A_D, reg, reg, ___) \
718 V(DFloor, A_D, reg, reg, ___) \ 728 V(DFloor, A_D, reg, reg, ___) \
719 V(DCeil, A_D, reg, reg, ___) \ 729 V(DCeil, A_D, reg, reg, ___) \
720 V(DoubleToFloat, A_D, reg, reg, ___) \ 730 V(DoubleToFloat, A_D, reg, reg, ___) \
721 V(FloatToDouble, A_D, reg, reg, ___) \ 731 V(FloatToDouble, A_D, reg, reg, ___) \
732 V(DoubleIsNaN, A_D, reg, reg, ___) \
733 V(DoubleIsInfinite, A_D, reg, reg, ___) \
722 V(StoreStaticTOS, D, lit, ___, ___) \ 734 V(StoreStaticTOS, D, lit, ___, ___) \
723 V(PushStatic, D, lit, ___, ___) \ 735 V(PushStatic, D, lit, ___, ___) \
724 V(InitStaticTOS, 0, ___, ___, ___) \ 736 V(InitStaticTOS, 0, ___, ___, ___) \
725 V(IfNeStrictTOS, 0, ___, ___, ___) \ 737 V(IfNeStrictTOS, 0, ___, ___, ___) \
726 V(IfEqStrictTOS, 0, ___, ___, ___) \ 738 V(IfEqStrictTOS, 0, ___, ___, ___) \
727 V(IfNeStrictNumTOS, 0, ___, ___, ___) \ 739 V(IfNeStrictNumTOS, 0, ___, ___, ___) \
728 V(IfEqStrictNumTOS, 0, ___, ___, ___) \ 740 V(IfEqStrictNumTOS, 0, ___, ___, ___) \
729 V(IfNeStrict, A_D, reg, reg, ___) \ 741 V(IfNeStrict, A_D, reg, reg, ___) \
730 V(IfEqStrict, A_D, reg, reg, ___) \ 742 V(IfEqStrict, A_D, reg, reg, ___) \
731 V(IfLe, A_D, reg, reg, ___) \ 743 V(IfLe, A_D, reg, reg, ___) \
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948 960
949 // After a comparison, the condition NEXT_IS_TRUE means the following 961 // After a comparison, the condition NEXT_IS_TRUE means the following
950 // instruction is executed if the comparision is true and skipped over overwise. 962 // instruction is executed if the comparision is true and skipped over overwise.
951 // Conidition NEXT_IS_FALSE means the following instruction is executed if the 963 // Conidition NEXT_IS_FALSE means the following instruction is executed if the
952 // comparison is false and skipped over otherwise. 964 // comparison is false and skipped over otherwise.
953 enum Condition { NEXT_IS_TRUE, NEXT_IS_FALSE }; 965 enum Condition { NEXT_IS_TRUE, NEXT_IS_FALSE };
954 966
955 } // namespace dart 967 } // namespace dart
956 968
957 #endif // VM_CONSTANTS_DBC_H_ 969 #endif // VM_CONSTANTS_DBC_H_
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