| OLD | NEW |
| 1 ; This file checks support for comparing vector values with the icmp | 1 ; This file checks support for comparing vector values with the icmp |
| 2 ; instruction. | 2 ; instruction. |
| 3 | 3 |
| 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s | 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s |
| 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s |
| 6 | 6 |
| 7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ | 7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ |
| 8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ | 8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ |
| 9 ; RUN: -i %s --args -O2 --skip-unimplemented \ | 9 ; RUN: -i %s --args -O2 \ |
| 10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ | 10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ |
| 11 ; RUN: --command FileCheck --check-prefix MIPS32 %s | 11 ; RUN: --command FileCheck --check-prefix MIPS32 %s |
| 12 | 12 |
| 13 ; Check that sext elimination occurs when the result of the comparison | 13 ; Check that sext elimination occurs when the result of the comparison |
| 14 ; instruction is already sign extended. Sign extension to 4 x i32 uses | 14 ; instruction is already sign extended. Sign extension to 4 x i32 uses |
| 15 ; the pslld instruction on x86. | 15 ; the pslld instruction on x86. |
| 16 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) { | 16 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) { |
| 17 entry: | 17 entry: |
| 18 %res.trunc = icmp eq <4 x i32> %a, %b | 18 %res.trunc = icmp eq <4 x i32> %a, %b |
| 19 %res = sext <4 x i1> %res.trunc to <4 x i32> | 19 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| (...skipping 6435 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 6455 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 | 6455 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 |
| 6456 ; MIPS32: andi [[T13]],[[T13]],0x1 | 6456 ; MIPS32: andi [[T13]],[[T13]],0x1 |
| 6457 ; MIPS32: sll [[T12]],[[T12]],0x1f | 6457 ; MIPS32: sll [[T12]],[[T12]],0x1f |
| 6458 ; MIPS32: sll [[T13]],[[T13]],0x1f | 6458 ; MIPS32: sll [[T13]],[[T13]],0x1f |
| 6459 ; MIPS32: sltu [[T12]],[[T12]],[[T13]] | 6459 ; MIPS32: sltu [[T12]],[[T12]],[[T13]] |
| 6460 ; MIPS32: srl [[T12]],[[T12]],0x18 | 6460 ; MIPS32: srl [[T12]],[[T12]],0x18 |
| 6461 ; MIPS32: sll [[T4]],[[T4]],0x8 | 6461 ; MIPS32: sll [[T4]],[[T4]],0x8 |
| 6462 ; MIPS32: srl [[T4]],[[T4]],0x8 | 6462 ; MIPS32: srl [[T4]],[[T4]],0x8 |
| 6463 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] | 6463 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] |
| 6464 } | 6464 } |
| OLD | NEW |