tests_lit/llvm2ice_tests/bitcast.ll - Issue 2432373002: [SubZero] Fix f64 to/from i64 moves

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Issue 2432373002: [SubZero] Fix f64 to/from i64 moves (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Addressed review comments Created 4 years, 1 month ago

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1 ; Trivial smoke test of bitcast between integer and FP types.	1 ; Trivial smoke test of bitcast between integer and FP types.

2	2

3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \| FileCheck %s	3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \| FileCheck %s

4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \| FileCheck %s	4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \| FileCheck %s

5	5

6 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \	6 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \

7 ; RUN: --target arm32 -i %s --args -O2 \	7 ; RUN: --target arm32 -i %s --args -O2 \

8 ; RUN: \| %if --need=target_ARM32 --command FileCheck %s \	8 ; RUN: \| %if --need=target_ARM32 --command FileCheck %s \

9 ; RUN: --check-prefix=ARM32	9 ; RUN: --check-prefix=ARM32

10	10

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82 ; ARM32-LABEL: cast_d2ll_const	82 ; ARM32-LABEL: cast_d2ll_const

83 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}}	83 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}}

84 ; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}}	84 ; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}}

85 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}	85 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}

86 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]	86 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]

87 ; MIPS32-LABEL: cast_d2ll_const	87 ; MIPS32-LABEL: cast_d2ll_const

88 ; MIPS32: lui {{.*}}, %hi(.L$double$0012345678901234)	88 ; MIPS32: lui {{.*}}, %hi(.L$double$0012345678901234)

89 ; MIPS32: ldc1 {{.}}, %lo(.L$double$0012345678901234)({{.}})	89 ; MIPS32: ldc1 {{.}}, %lo(.L$double$0012345678901234)({{.}})

90 ; MIPS32-O2: mfc1 $v1, $f{{[0-9]+}}	90 ; MIPS32-O2: mfc1 $v1, $f{{[0-9]+}}

91 ; MIPS32-O2: mfc1 $v0, $f{{[0-9]+}}	91 ; MIPS32-O2: mfc1 $v0, $f{{[0-9]+}}

92 ; MIPS32-OM1: sdc1	92 ; MIPS32-OM1: mfc1

	93 ; MIPS32-OM1: mfc1

93 ; MIPS32-OM1: lw	94 ; MIPS32-OM1: lw

94 ; MIPS32-OM1: lw	95 ; MIPS32-OM1: lw

95	96

96 define internal double @cast_ll2d(i64 %ll) {	97 define internal double @cast_ll2d(i64 %ll) {

97 entry:	98 entry:

98 %v0 = bitcast i64 %ll to double	99 %v0 = bitcast i64 %ll to double

99 ret double %v0	100 ret double %v0

100 }	101 }

101 ; CHECK-LABEL: cast_ll2d	102 ; CHECK-LABEL: cast_ll2d

102 ; CHECK: fld QWORD PTR	103 ; CHECK: fld QWORD PTR

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125 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]	126 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]

126 ; MIPS32-LABEL: cast_ll2d_const	127 ; MIPS32-LABEL: cast_ll2d_const

127 ; MIPS32: lui {{.*}}, 29646	128 ; MIPS32: lui {{.*}}, 29646

128 ; MIPS32: ori {{.}}, {{.}}, 12274	129 ; MIPS32: ori {{.}}, {{.}}, 12274

129 ; MIPS32: addiu {{.*}}, $zero, 2874	130 ; MIPS32: addiu {{.*}}, $zero, 2874

130 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}	131 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}

131 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}	132 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}

132 ; MIPS32-OM1: sw	133 ; MIPS32-OM1: sw

133 ; MIPS32-OM1: sw	134 ; MIPS32-OM1: sw

134 ; MIPS32-OM1: ldc1	135 ; MIPS32-OM1: ldc1

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